mirror of https://github.com/mgba-emu/mgba.git
Filler for more instructions
This commit is contained in:
Jeffrey Pfau
parent
a01fc986a3
commit
cb2469c4f4
227
src/arm.c
227
src/arm.c
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@ -31,7 +31,7 @@ static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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}
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}
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static const ARMInstruction armTable[0xF000];
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static const ARMInstruction armTable[0x10000];
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static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
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if (executionMode == cpu->executionMode) {
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@ -193,6 +193,28 @@ inline void ARMCycle(struct ARMCore* cpu) {
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY, POST_BODY) \
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DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY, POST_BODY)
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#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME ## ADDRESS, \
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BODY;)
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#define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, , BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, W, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, U, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, UW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, P, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PU, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, PUW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, I, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IU, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IUW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IP, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPW, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPU, BODY) \
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DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, IPUW, BODY)
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// Begin ALU definitions
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DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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@ -267,14 +289,14 @@ DEFINE_INSTRUCTION_ARM(UMULLS,)
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// Begin load/store definitions
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DEFINE_INSTRUCTION_ARM(LDR,)
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DEFINE_INSTRUCTION_ARM(LDRB,)
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DEFINE_INSTRUCTION_ARM(LDRH,)
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DEFINE_INSTRUCTION_ARM(LDRSB,)
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DEFINE_INSTRUCTION_ARM(LDRSH,)
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DEFINE_INSTRUCTION_ARM(STR,)
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DEFINE_INSTRUCTION_ARM(STRB,)
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DEFINE_INSTRUCTION_ARM(STRH,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRH,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRSB,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRSH,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB,)
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRH,)
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DEFINE_INSTRUCTION_ARM(SWP,)
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DEFINE_INSTRUCTION_ARM(SWPB,)
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@ -318,39 +340,43 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
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DECLARE_INSTRUCTION_ARM(COND, ALU), \
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DECLARE_INSTRUCTION_ARM(COND, EX4)
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#define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, NAME, P, U, W) \
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DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)) \
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DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W))
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#define DECLARE_COND_BLOCK(COND) \
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DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRHW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRHW, LDRSBW, LDRSHW), \
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DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
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DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRHIW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRHIW, LDRSBIW, LDRSHIW), \
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DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
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DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRHUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRHUW, LDRSBUW, LDRSHUW), \
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DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
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DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRHIUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRHIUW, LDRSBIUW, LDRSHIUW), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
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DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHPW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, TEQ, ILL, LDRHPW, LDRSBPW, LDRSHPW), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWPB, STRHIP, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, CMP, ILL, LDRHIP, LDRSBIP, LDRSHIP), \
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DECLARE_ARM_ALU_BLOCK(COND, MSR, ILL, STRHIPW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, CMN, ILL, LDRHIPW, LDRSBIPW, LDRSHIPW), \
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DECLARE_ARM_ALU_BLOCK(COND, ORR, SMLAL, STRHPU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ORRS, SMLALS, LDRHPU, LDRSBPU, LDRSHPU), \
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DECLARE_ARM_ALU_BLOCK(COND, MOV, SMLAL, STRHPUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, MOVS, SMLALS, LDRHPUW, LDRSBPUW, LDRSHPUW), \
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DECLARE_ARM_ALU_BLOCK(COND, BIC, SMLAL, STRHIPU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, BICS, SMLALS, LDRHIPU, LDRSBIPU, LDRSHIPU), \
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DECLARE_ARM_ALU_BLOCK(COND, MVN, SMLAL, STRHIPUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, MVNS, SMLALS, LDRHIPUW, LDRSBIPUW, LDRSHIPUW), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, AND), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, ANDS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, EOR), \
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@ -382,9 +408,125 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)
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DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)//, \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, , W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , U, W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , U, W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, , W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, , W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, ), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, P, U, W), \
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// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, P, U, W), \
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// DECLARE_ARM_BRANCH_BLOCK(COND, B), \
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// DECLARE_ARM_BRANCH_BLOCK(COND, BL), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , , W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , , W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , , N, W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , , N, W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, , W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, , W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, ), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, , U, N, W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, , U, N, W), \
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// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , , W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , , W), \
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||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, , N, W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, , N, W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, ), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, STC, P, U, N, W), \
|
||||
// DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(COND, LDC, P, U, N, W), \
|
||||
// DECLARE_ARM_COPROCESSOR_BLOCK(CDP, MCR), \
|
||||
// DECLARE_ARM_SWI_BLOCK
|
||||
|
||||
static const ARMInstruction armTable[0xF000] = {
|
||||
static const ARMInstruction armTable[0x10000] = {
|
||||
DECLARE_COND_BLOCK(EQ),
|
||||
DECLARE_COND_BLOCK(NE),
|
||||
DECLARE_COND_BLOCK(CS),
|
||||
|
|
@ -399,5 +541,6 @@ static const ARMInstruction armTable[0xF000] = {
|
|||
DECLARE_COND_BLOCK(LT),
|
||||
DECLARE_COND_BLOCK(GT),
|
||||
DECLARE_COND_BLOCK(LE),
|
||||
DECLARE_COND_BLOCK(AL)
|
||||
DECLARE_COND_BLOCK(AL)//,
|
||||
//DECLARE_EMPTY_BLOCK
|
||||
};
|
||||
Loading…
Reference in New Issue