mirror of https://github.com/mgba-emu/mgba.git
Start cycle counting
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parent
9b2cd97505
commit
c8a2f595d4
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@ -17,6 +17,15 @@
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buffer += AMOUNT; \
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blen -= AMOUNT;
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#define LOAD_CYCLES \
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info->iCycles = 1; \
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info->nDataCycles = 1;
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#define STORE_CYCLES \
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info->sInstructionCycles = 0; \
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info->nInstructionCycles = 1; \
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info->nDataCycles = 1;
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static int _decodeRegister(int reg, char* buffer, int blen);
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static int _decodeRegisterList(int list, char* buffer, int blen);
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static int _decodePCRelative(uint32_t address, uint32_t pc, char* buffer, int blen);
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@ -26,7 +26,7 @@
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, CYCLES) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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@ -35,7 +35,14 @@
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_IMMEDIATE_OFFSET;)
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ARM_MEMORY_IMMEDIATE_OFFSET; \
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CYCLES)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_LOAD_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, LOAD_CYCLES)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_STORE_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, STORE_CYCLES)
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#define DEFINE_IMMEDIATE_5_DECODER_THUMB(NAME, MNEMONIC, TYPE) \
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COUNT_5(DEFINE_IMMEDIATE_5_DECODER_ ## TYPE ## _THUMB, NAME ## _, MNEMONIC)
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@ -43,12 +50,12 @@
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSL1, LSL, DATA)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSR1, LSR, DATA)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(ASR1, ASR, DATA)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDRB, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDRH, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STRB, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STRH, MEM)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM_LOAD)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDRB, MEM_LOAD)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDRH, MEM_LOAD)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM_STORE)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STRB, MEM_STORE)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STRH, MEM_STORE)
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#define DEFINE_DATA_FORM_1_DECODER_EX_THUMB(NAME, RM, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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@ -159,7 +166,7 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG) \
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, CYCLES) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->memory.baseReg = REG; \
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@ -169,19 +176,26 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_IMMEDIATE_OFFSET;)
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ARM_MEMORY_IMMEDIATE_OFFSET; \
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CYCLES;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_LOAD_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, LOAD_CYCLES)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_STORE_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, STORE_CYCLES)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, MNEMONIC, TYPE, REG) \
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COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_ ## TYPE ## _THUMB, NAME ## _R, MNEMONIC, REG)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM_LOAD, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM_LOAD, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM_STORE, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ADD, DATA, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC) \
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC, CYCLES) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.offset.reg = RM; \
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info->op1.reg = opcode & 0x0007; \
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@ -190,19 +204,20 @@ DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_MEMORY_2; \
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info->memory.format = ARM_MEMORY_REGISTER_BASE | \
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ARM_MEMORY_REGISTER_OFFSET;)
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ARM_MEMORY_REGISTER_OFFSET; \
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CYCLES;)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC) \
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COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES) \
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COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC, CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDRB)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDRH)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDRSB)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDRSH)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STRB)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDRB, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDRH, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, LDRSB, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, LDRSH, LOAD_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, STR, STORE_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, STRB, STORE_CYCLES)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STRH, STORE_CYCLES)
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, MNEMONIC, SPECIAL_REG, ADDITIONAL_REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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@ -303,6 +318,12 @@ void _decodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info) {
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info->accessesSpecialRegisters = 0;
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info->affectsCPSR = 0;
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info->condition = ARM_CONDITION_AL;
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info->sDataCycles = 0;
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info->nDataCycles = 0;
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info->sInstructionCycles = 1;
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info->nInstructionCycles = 0;
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info->iCycles = 0;
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info->cCycles = 0;
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ThumbDecoder decoder = _thumbDecoderTable[opcode >> 6];
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decoder(opcode, info);
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}
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@ -139,6 +139,12 @@ struct ThumbInstructionInfo {
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int accessesSpecialRegisters;
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int affectsCPSR;
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int condition;
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int sDataCycles;
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int nDataCycles;
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int sInstructionCycles;
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int nInstructionCycles;
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int iCycles;
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int cCycles;
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};
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void ARMDecodeThumb(uint16_t opcode, struct ThumbInstructionInfo* info);
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