diff --git a/src/arm.c b/src/arm.c
index 4e315e497..357acf5ef 100644
--- a/src/arm.c
+++ b/src/arm.c
@@ -12,7 +12,7 @@ static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) {
 	return mode != MODE_SYSTEM && mode != MODE_USER;
 }
 
-static const ARMInstruction armTable[0x100000];
+static const ARMInstruction armTable[0xF000];
 
 static inline void _ARMSetMode(struct ARMCore* cpu, enum ExecutionMode executionMode) {
 	if (executionMode == cpu->executionMode) {
@@ -167,16 +167,14 @@ DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand
 	cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand; \
 )
 
+DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
+	cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand; \
+)
+
 #define DECLARE_INSTRUCTION_ARM(COND, NAME) \
 	_ARMInstruction ## NAME ## COND
 
-#define DO_16(DIRECTIVE) \
-	DIRECTIVE, \
-	DIRECTIVE, \
-	DIRECTIVE, \
-	DIRECTIVE, \
-	DIRECTIVE, \
-	DIRECTIVE, \
+#define DO_8(DIRECTIVE) \
 	DIRECTIVE, \
 	DIRECTIVE, \
 	DIRECTIVE, \
@@ -188,33 +186,48 @@ DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand
 	DIRECTIVE, \
 	DIRECTIVE \
 
-#define DO_128(DIRECTIVE) \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE), \
-	DO_16(DIRECTIVE) \
-
 // TODO: MUL
-#define DECLARE_ARM_ALU_MUL_BLOCK(COND, ALU, MUL) \
-	DO_128(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(0), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
-	DO_16(DECLARE_INSTRUCTION_ARM(COND, ALU))
+#define DECLARE_ARM_ALU_EX_BLOCK(COND, ALU, EX1, EX2, EX3, EX4) \
+	DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0, \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0, \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0, \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0
+
+#define DECLARE_ARM_ALU_BLOCK(COND, ALU) \
+	DO_8(DECLARE_INSTRUCTION_ARM(COND, ALU)), \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0, \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0, \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0, \
+	DECLARE_INSTRUCTION_ARM(COND, ALU), \
+	0
 
 #define DECLARE_COND_BLOCK(COND) \
-	DECLARE_ARM_ALU_MUL_BLOCK(COND, AND, MUL), \
-	DECLARE_ARM_ALU_MUL_BLOCK(COND, ANDS, MULS)
+	DECLARE_ARM_ALU_EX_BLOCK(COND, AND, MUL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, EOR, MLA, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, EORS, MLAS, LDRH, LDRSB, LDRSH)/*, \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, SUB, 0, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, SUBS, 0, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, RSB, 0, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, RSBS, 0, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, ADD, UMULL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, ADDS, UMULLS, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, ADC, UMLAL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, ADCS, UMLALS, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, SBC, SMULL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, SBCS, SMULLS, LDRH, LDRSB, LDRSH), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, RSC, SMLAL, STRH, 0, 0), \
+	DECLARE_ARM_ALU_EX_BLOCK(COND, RSCS, SMLALS, LDRH, LDRSB, LDRSH)*/
 
-static const ARMInstruction armTable[0x100000] = {
+static const ARMInstruction armTable[0xF000] = {
 	DECLARE_COND_BLOCK(EQ),
 	DECLARE_COND_BLOCK(NE),
 	DECLARE_COND_BLOCK(CS),