diff --git a/CHANGES b/CHANGES
index 7cd8e1e8b..10677d6ea 100644
--- a/CHANGES
+++ b/CHANGES
@@ -12,6 +12,7 @@ Bugfixes:
  - DS GX: Fix incorrect W values
  - DS Video: Fix 2D/3D blending alpha values
  - DS I/O: Enable POWCNT1 bit 1 at boot (fixes mgba.io/i/616)
+ - DS Slot-1: Reply to IR 0x08 command properly (fixes mgba.io/i/666)
 Misc:
  - DS GX: Clean up and unify texture mapping
  - DS Core: Add symbol loading
@@ -23,11 +24,8 @@ Features:
 Bugfixes:
  - GB Audio: Make audio unsigned with bias (fixes mgba.io/i/749)
  - Python: Fix importing .gb or .gba before .core
-<<<<<<< HEAD
-=======
  - GBA: Reset active region as needed when loading a ROM
  - Qt: Fix command line debugger closing second game
->>>>>>> feature/input-revamp
 Misc:
  - GBA Timer: Use global cycles for timers
  - GBA: Extend oddly-sized ROMs to full address space (fixes mgba.io/i/722)
diff --git a/include/mgba/internal/ds/slot1.h b/include/mgba/internal/ds/slot1.h
index cb4a2e88c..883685a4f 100644
--- a/include/mgba/internal/ds/slot1.h
+++ b/include/mgba/internal/ds/slot1.h
@@ -51,6 +51,7 @@ struct DSSlot1 {
 	int dmaSource;
 
 	enum DSSavedataType savedataType;
+	bool hasIR;
 	struct mTimingEvent spiEvent;
 	bool spiHoldEnabled;
 	uint8_t spiCommand;
diff --git a/src/ds/slot1.c b/src/ds/slot1.c
index 0157db962..b5393f816 100644
--- a/src/ds/slot1.c
+++ b/src/ds/slot1.c
@@ -27,6 +27,7 @@ void DSSlot1SPIInit(struct DS* ds, struct VFile* vf) {
 	ds->memory.slot1.transferEvent.context = ds;
 	ds->memory.slot1.transferEvent.callback = _transferEvent;
 	ds->memory.slot1.savedataType = DS_SAVEDATA_AUTODETECT;
+	ds->memory.slot1.hasIR = false;
 	ds->memory.slot1.spiVf = vf;
 	ds->memory.slot1.spiRealVf = vf;
 	ds->memory.slot1.spiData = NULL;
@@ -358,7 +359,11 @@ static void _slot1SPI(struct mTiming* timing, void* context, uint32_t cyclesLate
 		} else {
 			dscore->p->memory.slot1.spiAddress = 0;
 		}
-		dscore->p->memory.slot1.spiAddressingRemaining = dscore->p->memory.slot1.spiAddressingBits;
+		if (oldValue == 0x08 && dscore->p->memory.slot1.hasIR) {
+			dscore->p->memory.slot1.spiCommand |= 0x80; // TODO: Move to a separate variable
+		} else {
+			dscore->p->memory.slot1.spiAddressingRemaining = dscore->p->memory.slot1.spiAddressingBits;
+		}
 	} else {
 		switch (dscore->p->memory.slot1.spiCommand) {
 		case 0x04: // WRDI
@@ -371,6 +376,10 @@ static void _slot1SPI(struct mTiming* timing, void* context, uint32_t cyclesLate
 			dscore->p->memory.slot1.statusReg |= 2;
 			break;
 		default:
+			if (dscore->p->memory.slot1.hasIR && dscore->p->memory.slot1.spiCommand == 0x88) {
+				newValue = 0xAA;
+				break;
+			}
 			switch (dscore->p->memory.slot1.savedataType) {
 			case DS_SAVEDATA_AUTODETECT:
 				newValue = _slot1SPIAutodetect(dscore, oldValue);
@@ -449,6 +458,9 @@ void DSSlot1ConfigureSPI(struct DS* ds, uint32_t paramPtr) {
 	} else {
 		ds->memory.slot1.spiAddressingBits = 16;
 	}
+	if (saveParams & 0xFF0000) {
+		ds->memory.slot1.hasIR = true;
+	}
 	ds->memory.slot1.spiAddress = size - 1;
 	ds->memory.slot1.spiSize = size;
 	_slot1GuaranteeSize(&ds->memory.slot1);