mirror of https://github.com/mgba-emu/mgba.git
ARM7: Reduce the size of the Thumb instruction table
This commit is contained in:
Jeffrey Pfau
parent
4388e36ddc
commit
bdb7635156
1
CHANGES
1
CHANGES
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@ -81,6 +81,7 @@ Misc:
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- GBA Video: Refactor software renderer into separate files
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- ARM7: Add emulation for Undefined CPU mode
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- GBA: More accurate cycle estimation for ROM prefetch and flash save chips
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- ARM7: Reduce the size of the Thumb instruction table
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0.2.1: (2015-05-13)
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Bugfixes:
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@ -16,9 +16,9 @@
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BODY; \
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}
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#define DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(NAME, IMMEDIATE, MNEMONIC, WIDTH) \
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#define DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(NAME, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op3.immediate = IMMEDIATE; \
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info->op3.immediate = (opcode >> 6) & 0x0007; \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->affectsCPSR = 1; \
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@ -27,11 +27,11 @@
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, CYCLES, WIDTH) \
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, MNEMONIC, CYCLES, WIDTH) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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info->memory.offset.immediate = IMMEDIATE * WIDTH; \
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info->memory.offset.immediate = ((opcode >> 6) & 0x0007) * WIDTH; \
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info->memory.width = (enum ARMMemoryAccessType) WIDTH; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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@ -40,71 +40,53 @@
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ARM_MEMORY_IMMEDIATE_OFFSET; \
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CYCLES)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_LOAD_THUMB(NAME, IMMEDIATE, MNEMONIC, WIDTH) \
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, LOAD_CYCLES, WIDTH)
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DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(LSL1, LSL)
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DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(LSR1, LSR)
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DEFINE_IMMEDIATE_5_DECODER_DATA_THUMB(ASR1, ASR)
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(LDR1, LDR, LOAD_CYCLES, 4)
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(LDRB1, LDR, LOAD_CYCLES, 1)
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(LDRH1, LDR, LOAD_CYCLES, 2)
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(STR1, STR, STORE_CYCLES, 4)
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(STRB1, STR, STORE_CYCLES, 1)
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(STRH1, STR, STORE_CYCLES, 2)
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#define DEFINE_IMMEDIATE_5_DECODER_MEM_STORE_THUMB(NAME, IMMEDIATE, MNEMONIC, WIDTH) \
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DEFINE_IMMEDIATE_5_DECODER_MEM_THUMB(NAME, IMMEDIATE, MNEMONIC, STORE_CYCLES, WIDTH)
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#define DEFINE_IMMEDIATE_5_DECODER_THUMB(NAME, MNEMONIC, TYPE, WIDTH) \
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COUNT_CALL_5(DEFINE_IMMEDIATE_5_DECODER_ ## TYPE ## _THUMB, NAME ## _, MNEMONIC, WIDTH)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSL1, LSL, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LSR1, LSR, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(ASR1, ASR, DATA,)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDR1, LDR, MEM_LOAD, 4)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRB1, LDR, MEM_LOAD, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(LDRH1, LDR, MEM_LOAD, 2)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STR1, STR, MEM_STORE, 4)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRB1, STR, MEM_STORE, 1)
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DEFINE_IMMEDIATE_5_DECODER_THUMB(STRH1, STR, MEM_STORE, 2)
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#define DEFINE_DATA_FORM_1_DECODER_EX_THUMB(NAME, RM, MNEMONIC) \
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#define DEFINE_DATA_FORM_1_DECODER_THUMB(NAME, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->op3.reg = RM; \
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info->op3.reg = (opcode >> 6) & 0x0007; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_REGISTER_3;)
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#define DEFINE_DATA_FORM_1_DECODER_THUMB(NAME) \
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COUNT_CALL_3(DEFINE_DATA_FORM_1_DECODER_EX_THUMB, NAME ## 3_R, NAME)
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DEFINE_DATA_FORM_1_DECODER_THUMB(ADD3, ADD)
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DEFINE_DATA_FORM_1_DECODER_THUMB(SUB3, SUB)
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DEFINE_DATA_FORM_1_DECODER_THUMB(ADD)
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DEFINE_DATA_FORM_1_DECODER_THUMB(SUB)
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#define DEFINE_DATA_FORM_2_DECODER_EX_THUMB(NAME, IMMEDIATE, MNEMONIC) \
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#define DEFINE_DATA_FORM_2_DECODER_THUMB(NAME, MNEMONIC) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = opcode & 0x0007; \
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info->op2.reg = (opcode >> 3) & 0x0007; \
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info->op3.immediate = IMMEDIATE; \
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info->op3.immediate = (opcode >> 6) & 0x0007; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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ARM_OPERAND_AFFECTED_1 | \
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_DATA_FORM_2_DECODER_THUMB(NAME) \
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COUNT_CALL_3(DEFINE_DATA_FORM_2_DECODER_EX_THUMB, NAME ## 1_, NAME)
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DEFINE_DATA_FORM_2_DECODER_THUMB(ADD1, ADD)
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DEFINE_DATA_FORM_2_DECODER_THUMB(SUB1, SUB)
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DEFINE_DATA_FORM_2_DECODER_THUMB(ADD)
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DEFINE_DATA_FORM_2_DECODER_THUMB(SUB)
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#define DEFINE_DATA_FORM_3_DECODER_EX_THUMB(NAME, RD, MNEMONIC, AFFECTED) \
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#define DEFINE_DATA_FORM_3_DECODER_THUMB(NAME, MNEMONIC, AFFECTED) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op1.reg = (opcode >> 8) & 0x0007; \
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info->op2.immediate = opcode & 0x00FF; \
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info->affectsCPSR = 1; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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AFFECTED | \
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ARM_OPERAND_IMMEDIATE_2;)
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#define DEFINE_DATA_FORM_3_DECODER_THUMB(NAME, MNEMONIC, AFFECTED) \
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COUNT_CALL_3(DEFINE_DATA_FORM_3_DECODER_EX_THUMB, NAME ## _R, MNEMONIC, AFFECTED)
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DEFINE_DATA_FORM_3_DECODER_THUMB(ADD2, ADD, ARM_OPERAND_AFFECTED_1)
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DEFINE_DATA_FORM_3_DECODER_THUMB(CMP1, CMP, ARM_OPERAND_NONE)
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DEFINE_DATA_FORM_3_DECODER_THUMB(MOV1, MOV, ARM_OPERAND_AFFECTED_1)
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@ -159,9 +141,9 @@ DEFINE_DECODER_WITH_HIGH_THUMB(ADD4, ADD, ARM_OPERAND_AFFECTED_1, 0)
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DEFINE_DECODER_WITH_HIGH_THUMB(CMP3, CMP, ARM_OPERAND_NONE, 1)
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DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(NAME, RD, MNEMONIC, REG) \
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#define DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(NAME, MNEMONIC, REG) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op1.reg = (opcode >> 6) & 0x0007; \
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info->op2.reg = REG; \
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info->op3.immediate = (opcode & 0x00FF) << 2; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 | \
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@ -169,9 +151,9 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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ARM_OPERAND_REGISTER_2 | \
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ARM_OPERAND_IMMEDIATE_3;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, CYCLES) \
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, MNEMONIC, REG, CYCLES) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->op1.reg = RD; \
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info->op1.reg = (opcode >> 6) & 0x0007; \
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info->memory.baseReg = REG; \
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info->memory.offset.immediate = (opcode & 0x00FF) << 2; \
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info->memory.width = ARM_ACCESS_WORD; \
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@ -182,25 +164,16 @@ DEFINE_DECODER_WITH_HIGH_THUMB(MOV3, MOV, ARM_OPERAND_AFFECTED_1, 0)
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ARM_MEMORY_IMMEDIATE_OFFSET; \
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CYCLES;)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_LOAD_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, LOAD_CYCLES)
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(LDR3, LDR, ARM_PC, LOAD_CYCLES)
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(LDR4, LDR, ARM_SP, LOAD_CYCLES)
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(STR3, STR, ARM_SP, STORE_CYCLES)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_MEM_STORE_THUMB(NAME, RD, MNEMONIC, REG) \
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DEFINE_IMMEDIATE_WITH_REGISTER_MEM_THUMB(NAME, RD, MNEMONIC, REG, STORE_CYCLES)
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DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(ADD5, ADD, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_DATA_THUMB(ADD6, ADD, ARM_SP)
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#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, MNEMONIC, TYPE, REG) \
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COUNT_CALL_3(DEFINE_IMMEDIATE_WITH_REGISTER_ ## TYPE ## _THUMB, NAME ## _R, MNEMONIC, REG)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, LDR, MEM_LOAD, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, LDR, MEM_LOAD, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, STR, MEM_STORE, ARM_SP)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ADD, DATA, ARM_PC)
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, MNEMONIC, CYCLES, TYPE) \
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES, TYPE) \
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DEFINE_THUMB_DECODER(NAME, MNEMONIC, \
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info->memory.offset.reg = RM; \
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info->memory.offset.reg = (opcode >> 6) & 0x0007; \
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info->op1.reg = opcode & 0x0007; \
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info->memory.baseReg = (opcode >> 3) & 0x0007; \
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info->memory.width = TYPE; \
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@ -211,9 +184,6 @@ DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ADD, DATA, ARM_SP)
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ARM_MEMORY_REGISTER_OFFSET; \
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CYCLES;)
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, MNEMONIC, CYCLES, TYPE) \
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COUNT_CALL_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, MNEMONIC, CYCLES, TYPE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, LDR, LOAD_CYCLES, ARM_ACCESS_WORD)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, LDR, LOAD_CYCLES, ARM_ACCESS_BYTE)
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, LDR, LOAD_CYCLES, ARM_ACCESS_HALFWORD)
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@ -237,7 +207,7 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, STR, STORE_CYCLES, ARM_ACCESS_HALFW
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DIRECTION;)
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#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME) \
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COUNT_CALL_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## IA_R, NAME, ARM_MEMORY_INCREMENT_AFTER, 0)
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME ## IA, (opcode >> 8) & 0x0007, NAME, ARM_MEMORY_INCREMENT_AFTER, 0)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDM)
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DEFINE_LOAD_STORE_MULTIPLE_THUMB(STM)
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@ -29,105 +29,4 @@
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LEFT, \
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RIGHT
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#define APPLY(F, ...) F(__VA_ARGS__)
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#define COUNT_CALL_1(EMITTER, PREFIX, ...) \
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EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
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EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
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#define COUNT_CALL_2(EMITTER, PREFIX, ...) \
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COUNT_CALL_1(EMITTER, PREFIX, __VA_ARGS__) \
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EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
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EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
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#define COUNT_CALL_3(EMITTER, PREFIX, ...) \
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COUNT_CALL_2(EMITTER, PREFIX, __VA_ARGS__) \
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EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
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EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
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EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
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EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
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#define COUNT_CALL_4(EMITTER, PREFIX, ...) \
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COUNT_CALL_3(EMITTER, PREFIX, __VA_ARGS__) \
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EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
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EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
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EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
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EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
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EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
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EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
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EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
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EMITTER(PREFIX ## F, 15, __VA_ARGS__)
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#define COUNT_CALL_5(EMITTER, PREFIX, ...) \
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COUNT_CALL_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
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EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
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EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
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EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
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EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
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EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
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EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
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EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
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EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
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EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
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EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
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EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
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EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
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EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
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EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
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EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
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EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
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#define COUNT_1(EMITTER, PREFIX) \
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EMITTER(PREFIX ## 0) \
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EMITTER(PREFIX ## 1)
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#define COUNT_2(EMITTER, PREFIX) \
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COUNT_1(EMITTER, PREFIX) \
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EMITTER(PREFIX ## 2) \
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EMITTER(PREFIX ## 3)
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#define COUNT_3(EMITTER, PREFIX) \
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COUNT_2(EMITTER, PREFIX) \
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EMITTER(PREFIX ## 4) \
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EMITTER(PREFIX ## 5) \
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EMITTER(PREFIX ## 6) \
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EMITTER(PREFIX ## 7)
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#define COUNT_4(EMITTER, PREFIX) \
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COUNT_3(EMITTER, PREFIX) \
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EMITTER(PREFIX ## 8) \
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EMITTER(PREFIX ## 9) \
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EMITTER(PREFIX ## A) \
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EMITTER(PREFIX ## B) \
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EMITTER(PREFIX ## C) \
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EMITTER(PREFIX ## D) \
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EMITTER(PREFIX ## E) \
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EMITTER(PREFIX ## F)
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#define COUNT_5(EMITTER, PREFIX) \
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COUNT_4(EMITTER, PREFIX ## 0) \
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EMITTER(PREFIX ## 10) \
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EMITTER(PREFIX ## 11) \
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EMITTER(PREFIX ## 12) \
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EMITTER(PREFIX ## 13) \
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EMITTER(PREFIX ## 14) \
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EMITTER(PREFIX ## 15) \
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EMITTER(PREFIX ## 16) \
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EMITTER(PREFIX ## 17) \
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EMITTER(PREFIX ## 18) \
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EMITTER(PREFIX ## 19) \
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EMITTER(PREFIX ## 1A) \
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EMITTER(PREFIX ## 1B) \
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EMITTER(PREFIX ## 1C) \
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EMITTER(PREFIX ## 1D) \
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EMITTER(PREFIX ## 1E) \
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EMITTER(PREFIX ## 1F) \
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#define ECHO(...) __VA_ARGS__,
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#define ECHO_4(...) \
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ECHO(__VA_ARGS__) \
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ECHO(__VA_ARGS__) \
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ECHO(__VA_ARGS__) \
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ECHO(__VA_ARGS__)
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#endif
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@ -18,17 +18,17 @@
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DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
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#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1))), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1)), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2))), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
|
||||
|
|
@ -52,25 +52,25 @@
|
|||
DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
|
||||
APPLY(COUNT_3, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
|
||||
APPLY(COUNT_5, ECHO, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3))), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STR2)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2)), \
|
||||
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH)), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STR1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STR3))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6))), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
|
||||
DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
|
||||
|
|
@ -87,8 +87,8 @@
|
|||
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
|
||||
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
|
||||
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
|
||||
APPLY(COUNT_3, ECHO_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA))), \
|
||||
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA))), \
|
||||
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
|
||||
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
|
||||
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
|
||||
|
|
|
|||
|
|
@ -54,16 +54,13 @@
|
|||
cpu->cycles += currentCycles; \
|
||||
}
|
||||
|
||||
#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
|
||||
#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int immediate = IMMEDIATE; \
|
||||
int immediate = (opcode >> 6) & 0x001F; \
|
||||
int rd = opcode & 0x0007; \
|
||||
int rm = (opcode >> 3) & 0x0007; \
|
||||
BODY;)
|
||||
|
||||
#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
|
||||
COUNT_CALL_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
|
||||
|
||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
|
||||
if (!immediate) {
|
||||
cpu->gprs[rd] = cpu->gprs[rm];
|
||||
|
|
@ -104,40 +101,31 @@ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, cpu->memory.store32(cpu, cpu->gprs[rm
|
|||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, cpu->memory.store8(cpu, cpu->gprs[rm] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
|
||||
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, cpu->memory.store16(cpu, cpu->gprs[rm] + immediate * 2, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
|
||||
|
||||
#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int rm = RM; \
|
||||
int rd = opcode & 0x0007; \
|
||||
int rn = (opcode >> 3) & 0x0007; \
|
||||
BODY;)
|
||||
|
||||
#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
|
||||
COUNT_CALL_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
|
||||
|
||||
DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
|
||||
DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
|
||||
|
||||
#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int immediate = IMMEDIATE; \
|
||||
int rm = (opcode >> 6) & 0x0007; \
|
||||
int rd = opcode & 0x0007; \
|
||||
int rn = (opcode >> 3) & 0x0007; \
|
||||
BODY;)
|
||||
|
||||
DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD3, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
|
||||
DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB3, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], cpu->gprs[rm]))
|
||||
|
||||
#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
|
||||
COUNT_CALL_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
|
||||
|
||||
DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
|
||||
DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
|
||||
|
||||
#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int rd = RD; \
|
||||
int immediate = opcode & 0x00FF; \
|
||||
int immediate = (opcode >> 6) & 0x0007; \
|
||||
int rd = opcode & 0x0007; \
|
||||
int rn = (opcode >> 3) & 0x0007; \
|
||||
BODY;)
|
||||
|
||||
DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD1, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rn], immediate))
|
||||
DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB1, THUMB_SUBTRACTION(cpu->gprs[rd], cpu->gprs[rn], immediate))
|
||||
|
||||
#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
|
||||
COUNT_CALL_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int rd = (opcode >> 8) & 0x0007; \
|
||||
int immediate = opcode & 0x00FF; \
|
||||
BODY;)
|
||||
|
||||
DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, THUMB_ADDITION(cpu->gprs[rd], cpu->gprs[rd], immediate))
|
||||
DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, int aluOut = cpu->gprs[rd] - immediate; THUMB_SUBTRACTION_S(cpu->gprs[rd], immediate, aluOut))
|
||||
|
|
@ -260,15 +248,12 @@ DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3,
|
|||
THUMB_WRITE_PC;
|
||||
})
|
||||
|
||||
#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
|
||||
#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int rd = RD; \
|
||||
int rd = (opcode >> 8) & 0x0007; \
|
||||
int immediate = (opcode & 0x00FF) << 2; \
|
||||
BODY;)
|
||||
|
||||
#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
|
||||
COUNT_CALL_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
|
||||
|
||||
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, cpu->gprs[rd] = cpu->memory.load32(cpu, (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
|
||||
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[ARM_SP] + immediate, ¤tCycles); THUMB_LOAD_POST_BODY;)
|
||||
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[ARM_SP] + immediate, cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
|
||||
|
|
@ -276,16 +261,13 @@ DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, cpu->memory.store32(cpu, cpu->gprs[AR
|
|||
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, cpu->gprs[rd] = (cpu->gprs[ARM_PC] & 0xFFFFFFFC) + immediate)
|
||||
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, cpu->gprs[rd] = cpu->gprs[ARM_SP] + immediate)
|
||||
|
||||
#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
|
||||
#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int rm = RM; \
|
||||
int rm = (opcode >> 6) & 0x0007; \
|
||||
int rd = opcode & 0x0007; \
|
||||
int rn = (opcode >> 3) & 0x0007; \
|
||||
BODY;)
|
||||
|
||||
#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
|
||||
COUNT_CALL_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
|
||||
|
||||
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, cpu->gprs[rd] = cpu->memory.load32(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
|
||||
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, cpu->gprs[rd] = cpu->memory.load8(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
|
||||
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, cpu->gprs[rd] = cpu->memory.load16(cpu, cpu->gprs[rn] + cpu->gprs[rm], ¤tCycles); THUMB_LOAD_POST_BODY;)
|
||||
|
|
@ -295,7 +277,7 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, cpu->memory.store32(cpu, cpu->gprs[r
|
|||
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, cpu->memory.store8(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
|
||||
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[rn] + cpu->gprs[rm], cpu->gprs[rd], ¤tCycles); THUMB_STORE_POST_BODY;)
|
||||
|
||||
#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
|
||||
#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, RN, LS, DIRECTION, PRE_BODY, WRITEBACK) \
|
||||
DEFINE_INSTRUCTION_THUMB(NAME, \
|
||||
int rn = RN; \
|
||||
UNUSED(rn); \
|
||||
|
|
@ -305,20 +287,21 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, cpu->memory.store16(cpu, cpu->gprs[
|
|||
address = cpu->memory. LS ## Multiple(cpu, address, rs, LSM_ ## DIRECTION, ¤tCycles); \
|
||||
WRITEBACK;)
|
||||
|
||||
#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, LS, DIRECTION, WRITEBACK) \
|
||||
COUNT_CALL_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, LS, DIRECTION, , WRITEBACK)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
|
||||
(opcode >> 8) & 0x0007,
|
||||
load,
|
||||
IA,
|
||||
,
|
||||
THUMB_LOAD_POST_BODY;
|
||||
if (!((1 << rn) & rs)) {
|
||||
cpu->gprs[rn] = address;
|
||||
})
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
|
||||
(opcode >> 8) & 0x0007,
|
||||
store,
|
||||
IA,
|
||||
,
|
||||
THUMB_STORE_POST_BODY;
|
||||
cpu->gprs[rn] = address;)
|
||||
|
||||
|
|
@ -348,7 +331,7 @@ DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
|
|||
DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
|
||||
DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(POP,
|
||||
ARM_SP,
|
||||
load,
|
||||
IA,
|
||||
|
|
@ -356,7 +339,7 @@ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
|
|||
THUMB_LOAD_POST_BODY;
|
||||
cpu->gprs[ARM_SP] = address)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(POPR,
|
||||
ARM_SP,
|
||||
load,
|
||||
IA,
|
||||
|
|
@ -365,7 +348,7 @@ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
|
|||
cpu->gprs[ARM_SP] = address;
|
||||
THUMB_WRITE_PC;)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSH,
|
||||
ARM_SP,
|
||||
store,
|
||||
DB,
|
||||
|
|
@ -373,7 +356,7 @@ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
|
|||
THUMB_STORE_POST_BODY;
|
||||
cpu->gprs[ARM_SP] = address)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(PUSHR,
|
||||
ARM_SP,
|
||||
store,
|
||||
DB,
|
||||
|
|
|
|||
Loading…
Reference in New Issue