mirror of https://github.com/mgba-emu/mgba.git
GB: Redo double speed emulation (closes #1515)
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CHANGES
1
CHANGES
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@ -96,6 +96,7 @@ Misc:
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- Core: Improve support for ROM patch cheats, supporting disabling overlapping patches
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- GB: Allow pausing event loop while CPU is blocked
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- GB: Add support for sleep and shutdown callbacks
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- GB: Redo double speed emulation (closes mgba.io/i/1515)
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- GB Core: Return the current number of banks for ROM/SRAM, not theoretical max
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- GB I/O: Implement preliminary support for PCM12/PCM34 (closes mgba.io/i/1468)
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- GBA: Allow pausing event loop while CPU is blocked
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@ -133,6 +133,7 @@ struct SM83Core {
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uint16_t index;
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int tMultiplier;
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int32_t cycles;
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int32_t nextEvent;
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enum SM83ExecutionState executionState;
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@ -65,7 +65,7 @@ void GBAudioInit(struct GBAudio* audio, size_t samples, uint8_t* nr52, enum GBAu
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if (style == GB_AUDIO_GBA) {
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audio->timingFactor = 4;
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} else {
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audio->timingFactor = 1;
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audio->timingFactor = 2;
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}
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audio->frameEvent.context = audio;
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@ -339,7 +339,7 @@ void GBAudioWriteNR34(struct GBAudio* audio, uint8_t value) {
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if (audio->playingCh3) {
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audio->ch3.readable = audio->style != GB_AUDIO_DMG;
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// TODO: Where does this cycle delay come from?
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mTimingSchedule(audio->timing, &audio->ch3Event, audio->timingFactor * 4 + 2 * (2048 - audio->ch3.rate));
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mTimingSchedule(audio->timing, &audio->ch3Event, audio->timingFactor * (4 + 2 * (2048 - audio->ch3.rate)));
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}
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*audio->nr52 &= ~0x0004;
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*audio->nr52 |= audio->playingCh3 << 2;
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@ -477,13 +477,10 @@ void GBAudioWriteNR52(struct GBAudio* audio, uint8_t value) {
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audio->skipFrame = false;
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audio->frame = 7;
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if (audio->p) {
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unsigned timingFactor = 0x400 >> !audio->p->doubleSpeed;
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if (audio->p->timer.internalDiv & timingFactor) {
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if (audio->p && audio->p->timer.internalDiv & 0x400) {
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audio->skipFrame = true;
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}
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}
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}
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}
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void _updateFrame(struct mTiming* timing, void* user, uint32_t cyclesLate) {
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@ -914,7 +911,7 @@ static void _updateChannel3(struct mTiming* timing, void* user, uint32_t cyclesL
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audio->ch3.readable = true;
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if (audio->style == GB_AUDIO_DMG) {
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mTimingDeschedule(audio->timing, &audio->ch3Fade);
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mTimingSchedule(timing, &audio->ch3Fade, 2 - cyclesLate);
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mTimingSchedule(timing, &audio->ch3Fade, 4 - cyclesLate);
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}
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int cycles = 2 * (2048 - ch->rate);
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mTimingSchedule(timing, &audio->ch3Event, audio->timingFactor * cycles - cyclesLate);
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@ -742,7 +742,7 @@ void GBSetInterrupts(struct SM83Core* cpu, bool enable) {
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gb->memory.ime = false;
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GBUpdateIRQs(gb);
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} else {
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mTimingSchedule(&gb->timing, &gb->eiPending, 4);
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mTimingSchedule(&gb->timing, &gb->eiPending, 4 * cpu->tMultiplier);
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}
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}
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@ -796,7 +796,7 @@ void GBStop(struct SM83Core* cpu) {
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struct GB* gb = (struct GB*) cpu->master;
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if (gb->model >= GB_MODEL_CGB && gb->memory.io[GB_REG_KEY1] & 1) {
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gb->doubleSpeed ^= 1;
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gb->audio.timingFactor = gb->doubleSpeed + 1;
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gb->cpu->tMultiplier = 2 - gb->doubleSpeed;
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gb->memory.io[GB_REG_KEY1] = 0;
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gb->memory.io[GB_REG_KEY1] |= gb->doubleSpeed << 7;
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} else {
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@ -417,15 +417,15 @@ void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) {
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}
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return;
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case GB_REG_TIMA:
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if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 1) {
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if (value && mTimingUntil(&gb->timing, &gb->timer.irq) > 2 - (int) gb->doubleSpeed) {
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mTimingDeschedule(&gb->timing, &gb->timer.irq);
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}
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if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
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if (mTimingUntil(&gb->timing, &gb->timer.irq) == (int) gb->doubleSpeed - 2) {
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return;
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}
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break;
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case GB_REG_TMA:
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if (mTimingUntil(&gb->timing, &gb->timer.irq) == -1) {
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if (mTimingUntil(&gb->timing, &gb->timer.irq) == (int) gb->doubleSpeed - 2) {
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gb->memory.io[GB_REG_TIMA] = value;
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}
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break;
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@ -531,10 +531,7 @@ void GBMemoryDMA(struct GB* gb, uint16_t base) {
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base &= 0xDFFF;
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}
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mTimingDeschedule(&gb->timing, &gb->memory.dmaEvent);
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mTimingSchedule(&gb->timing, &gb->memory.dmaEvent, 8);
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if (gb->cpu->cycles + 8 < gb->cpu->nextEvent) {
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gb->cpu->nextEvent = gb->cpu->cycles + 8;
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}
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mTimingSchedule(&gb->timing, &gb->memory.dmaEvent, 8 * (2 - gb->doubleSpeed));
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gb->memory.dmaSource = base;
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gb->memory.dmaDest = 0;
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gb->memory.dmaRemaining = 0xA0;
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@ -580,7 +577,7 @@ void _GBMemoryDMAService(struct mTiming* timing, void* context, uint32_t cyclesL
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++gb->memory.dmaDest;
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gb->memory.dmaRemaining = dmaRemaining - 1;
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if (gb->memory.dmaRemaining) {
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mTimingSchedule(timing, &gb->memory.dmaEvent, 4 - cyclesLate);
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mTimingSchedule(timing, &gb->memory.dmaEvent, 4 * (2 - gb->doubleSpeed) - cyclesLate);
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}
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}
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@ -594,7 +591,7 @@ void _GBMemoryHDMAService(struct mTiming* timing, void* context, uint32_t cycles
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--gb->memory.hdmaRemaining;
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if (gb->memory.hdmaRemaining) {
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mTimingDeschedule(timing, &gb->memory.hdmaEvent);
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mTimingSchedule(timing, &gb->memory.hdmaEvent, 2 - cyclesLate);
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mTimingSchedule(timing, &gb->memory.hdmaEvent, 4 - cyclesLate);
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} else {
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gb->cpuBlocked = false;
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gb->memory.io[GB_REG_HDMA1] = gb->memory.hdmaSource >> 8;
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@ -175,8 +175,6 @@ bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state) {
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gb->cpu->halted = GBSerializedCpuFlagsGetHalted(flags);
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gb->cpuBlocked = GBSerializedCpuFlagsGetBlocked(flags);
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gb->audio.timingFactor = gb->doubleSpeed + 1;
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LOAD_32LE(gb->cpu->cycles, 0, &state->cpu.cycles);
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LOAD_32LE(gb->cpu->nextEvent, 0, &state->cpu.nextEvent);
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gb->timing.root = NULL;
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@ -77,7 +77,7 @@ void _GBSIOProcessEvents(struct mTiming* timing, void* context, uint32_t cyclesL
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sio->pendingSB = 0xFF;
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}
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} else {
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mTimingSchedule(timing, &sio->event, sio->period);
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mTimingSchedule(timing, &sio->event, sio->period * (2 - sio->p->doubleSpeed));
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}
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}
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@ -93,7 +93,7 @@ void GBSIOWriteSC(struct GBSIO* sio, uint8_t sc) {
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if (GBRegisterSCIsEnable(sc)) {
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mTimingDeschedule(&sio->p->timing, &sio->event);
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if (GBRegisterSCIsShiftClock(sc)) {
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mTimingSchedule(&sio->p->timing, &sio->event, sio->period);
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mTimingSchedule(&sio->p->timing, &sio->event, sio->period * (2 - sio->p->doubleSpeed));
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sio->remainingBits = 8;
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}
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}
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@ -128,7 +128,7 @@ static int32_t _masterUpdate(struct GBSIOLockstepNode* node) {
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case TRANSFER_FINISHING:
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// Finish the transfer
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// We need to make sure the other GBs catch up so they don't get behind
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node->nextEvent += node->d.p->period - 8; // Split the cycles to avoid waiting too long
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node->nextEvent += node->d.p->period * (2 - node->d.p->p->doubleSpeed) - 8; // Split the cycles to avoid waiting too long
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#ifndef NDEBUG
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ATOMIC_ADD(node->p->d.transferId, 1);
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#endif
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@ -208,7 +208,7 @@ static void _GBSIOLockstepNodeProcessEvents(struct mTiming* timing, void* user,
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struct GBSIOLockstepNode* node = user;
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mLockstepLock(&node->p->d);
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if (node->p->d.attached < 2) {
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mTimingSchedule(timing, &node->event, (GBSIOCyclesPerTransfer[0] >> 1) - cyclesLate);
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mTimingSchedule(timing, &node->event, (GBSIOCyclesPerTransfer[0] >> 1) * (2 - node->d.p->p->doubleSpeed) - cyclesLate);
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mLockstepUnlock(&node->p->d);
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return;
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}
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@ -20,17 +20,18 @@ void _GBTimerIRQ(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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}
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static void _GBTimerDivIncrement(struct GBTimer* timer, uint32_t cyclesLate) {
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while (timer->nextDiv >= GB_DMG_DIV_PERIOD) {
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timer->nextDiv -= GB_DMG_DIV_PERIOD;
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int tMultiplier = 2 - timer->p->doubleSpeed;
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while (timer->nextDiv >= GB_DMG_DIV_PERIOD * tMultiplier) {
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timer->nextDiv -= GB_DMG_DIV_PERIOD * tMultiplier;
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// Make sure to trigger when the correct bit is a falling edge
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if (timer->timaPeriod > 0 && (timer->internalDiv & (timer->timaPeriod - 1)) == timer->timaPeriod - 1) {
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++timer->p->memory.io[GB_REG_TIMA];
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if (!timer->p->memory.io[GB_REG_TIMA]) {
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mTimingSchedule(&timer->p->timing, &timer->irq, 7 - ((timer->p->cpu->executionState - cyclesLate) & 3));
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mTimingSchedule(&timer->p->timing, &timer->irq, 7 * tMultiplier - ((timer->p->cpu->executionState * tMultiplier - cyclesLate) & (3 * tMultiplier)));
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}
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}
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unsigned timingFactor = 0x3FF >> !timer->p->doubleSpeed;
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unsigned timingFactor = 0x1FF;
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if ((timer->internalDiv & timingFactor) == timingFactor) {
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GBAudioUpdateFrame(&timer->p->audio, &timer->p->timing);
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}
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@ -52,7 +53,7 @@ void _GBTimerUpdate(struct mTiming* timing, void* context, uint32_t cyclesLate)
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if (timaToGo < divsToGo) {
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divsToGo = timaToGo;
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}
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timer->nextDiv = GB_DMG_DIV_PERIOD * divsToGo;
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timer->nextDiv = GB_DMG_DIV_PERIOD * divsToGo * (2 - timer->p->doubleSpeed);
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mTimingSchedule(timing, &timer->event, timer->nextDiv - cyclesLate);
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}
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@ -66,7 +67,7 @@ void GBTimerReset(struct GBTimer* timer) {
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timer->irq.callback = _GBTimerIRQ;
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timer->event.priority = 0x21;
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timer->nextDiv = GB_DMG_DIV_PERIOD; // TODO: GBC differences
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timer->nextDiv = GB_DMG_DIV_PERIOD * 2;
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timer->timaPeriod = 1024 >> 4;
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}
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@ -74,27 +75,27 @@ void GBTimerDivReset(struct GBTimer* timer) {
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timer->nextDiv -= mTimingUntil(&timer->p->timing, &timer->event);
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mTimingDeschedule(&timer->p->timing, &timer->event);
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_GBTimerDivIncrement(timer, 0);
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if (((timer->internalDiv << 1) | ((timer->nextDiv >> 3) & 1)) & timer->timaPeriod) {
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int tMultiplier = 2 - timer->p->doubleSpeed;
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if (((timer->internalDiv << 1) | ((timer->nextDiv >> (4 - timer->p->doubleSpeed)) & 1)) & timer->timaPeriod) {
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++timer->p->memory.io[GB_REG_TIMA];
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if (!timer->p->memory.io[GB_REG_TIMA]) {
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mTimingSchedule(&timer->p->timing, &timer->irq, 7 - (timer->p->cpu->executionState & 3));
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mTimingSchedule(&timer->p->timing, &timer->irq, (7 - (timer->p->cpu->executionState & 3)) * tMultiplier);
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}
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}
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unsigned timingFactor = 0x400 >> !timer->p->doubleSpeed;
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if (timer->internalDiv & timingFactor) {
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if (timer->internalDiv & 0x200) {
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GBAudioUpdateFrame(&timer->p->audio, &timer->p->timing);
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}
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timer->p->memory.io[GB_REG_DIV] = 0;
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timer->internalDiv = 0;
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timer->nextDiv = GB_DMG_DIV_PERIOD;
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mTimingSchedule(&timer->p->timing, &timer->event, timer->nextDiv - ((timer->p->cpu->executionState + 1) & 3));
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timer->nextDiv = GB_DMG_DIV_PERIOD * (2 - timer->p->doubleSpeed);
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mTimingSchedule(&timer->p->timing, &timer->event, timer->nextDiv - ((timer->p->cpu->executionState + 1) & 3) * tMultiplier);
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}
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uint8_t GBTimerUpdateTAC(struct GBTimer* timer, GBRegisterTAC tac) {
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if (GBRegisterTACIsRun(tac)) {
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timer->nextDiv -= mTimingUntil(&timer->p->timing, &timer->event);
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mTimingDeschedule(&timer->p->timing, &timer->event);
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_GBTimerDivIncrement(timer, (timer->p->cpu->executionState + 2) & 3);
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_GBTimerDivIncrement(timer, ((timer->p->cpu->executionState + 2) & 3) * (2 - timer->p->doubleSpeed));
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switch (GBRegisterTACGetClock(tac)) {
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case 0:
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@ -111,7 +112,7 @@ uint8_t GBTimerUpdateTAC(struct GBTimer* timer, GBRegisterTAC tac) {
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break;
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}
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timer->nextDiv += GB_DMG_DIV_PERIOD;
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timer->nextDiv += GB_DMG_DIV_PERIOD * (2 - timer->p->doubleSpeed);
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mTimingSchedule(&timer->p->timing, &timer->event, timer->nextDiv);
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} else {
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timer->timaPeriod = 0;
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@ -253,7 +253,7 @@ void GBVideoSkipBIOS(struct GBVideo* video) {
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GBUpdateIRQs(video->p);
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video->p->memory.io[GB_REG_STAT] = video->stat;
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mTimingDeschedule(&video->p->timing, &video->modeEvent);
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mTimingSchedule(&video->p->timing, &video->modeEvent, next);
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mTimingSchedule(&video->p->timing, &video->modeEvent, next << 1);
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}
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void _endMode0(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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@ -297,7 +297,7 @@ void _endMode0(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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GBUpdateIRQs(video->p);
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video->p->memory.io[GB_REG_STAT] = video->stat;
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mTimingSchedule(timing, &video->modeEvent, (next << video->p->doubleSpeed) - cyclesLate);
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mTimingSchedule(timing, &video->modeEvent, (next << 1) - cyclesLate);
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}
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void _endMode1(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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@ -334,14 +334,14 @@ void _endMode1(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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GBUpdateIRQs(video->p);
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}
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video->p->memory.io[GB_REG_STAT] = video->stat;
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mTimingSchedule(timing, &video->modeEvent, (next << video->p->doubleSpeed) - cyclesLate);
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mTimingSchedule(timing, &video->modeEvent, (next << 1) - cyclesLate);
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}
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void _endMode2(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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struct GBVideo* video = context;
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_cleanOAM(video, video->ly);
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video->x = -(video->p->memory.io[GB_REG_SCX] & 7);
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video->dotClock = mTimingCurrentTime(timing) - cyclesLate + 5 - (video->x << video->p->doubleSpeed);
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video->dotClock = mTimingCurrentTime(timing) - cyclesLate + 10 - (video->x << 1);
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int32_t next = GB_VIDEO_MODE_3_LENGTH_BASE + video->objMax * 6 - video->x;
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video->mode = 3;
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video->modeEvent.callback = _endMode3;
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@ -352,7 +352,7 @@ void _endMode2(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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GBUpdateIRQs(video->p);
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}
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video->p->memory.io[GB_REG_STAT] = video->stat;
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mTimingSchedule(timing, &video->modeEvent, (next << video->p->doubleSpeed) - cyclesLate);
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mTimingSchedule(timing, &video->modeEvent, (next << 1) - cyclesLate);
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}
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void _endMode3(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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@ -375,18 +375,18 @@ void _endMode3(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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video->p->memory.io[GB_REG_STAT] = video->stat;
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// TODO: Cache SCX & 7 in case it changes
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int32_t next = GB_VIDEO_MODE_0_LENGTH_BASE - video->objMax * 6 - (video->p->memory.io[GB_REG_SCX] & 7);
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mTimingSchedule(timing, &video->modeEvent, (next << video->p->doubleSpeed) - cyclesLate);
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mTimingSchedule(timing, &video->modeEvent, (next << 1) - cyclesLate);
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}
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void _updateFrameCount(struct mTiming* timing, void* context, uint32_t cyclesLate) {
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UNUSED(cyclesLate);
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struct GBVideo* video = context;
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if (video->p->cpu->executionState != SM83_CORE_FETCH) {
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mTimingSchedule(timing, &video->frameEvent, 4 - ((video->p->cpu->executionState + 1) & 3));
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mTimingSchedule(timing, &video->frameEvent, (4 - ((video->p->cpu->executionState + 1) & 3)) * (2 - video->p->doubleSpeed));
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return;
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}
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if (!GBRegisterLCDCIsEnable(video->p->memory.io[GB_REG_LCDC])) {
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mTimingSchedule(timing, &video->frameEvent, GB_VIDEO_TOTAL_LENGTH);
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mTimingSchedule(timing, &video->frameEvent, GB_VIDEO_TOTAL_LENGTH << 1);
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}
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--video->frameskipCounter;
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@ -424,7 +424,7 @@ void GBVideoProcessDots(struct GBVideo* video, uint32_t cyclesLate) {
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return;
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}
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int oldX = video->x;
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video->x = (int32_t) (mTimingCurrentTime(&video->p->timing) - cyclesLate - video->dotClock) >> video->p->doubleSpeed;
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video->x = ((int32_t) (mTimingCurrentTime(&video->p->timing) - cyclesLate - video->dotClock)) >> 1;
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if (video->x > GB_VIDEO_HORIZONTAL_PIXELS) {
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video->x = GB_VIDEO_HORIZONTAL_PIXELS;
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} else if (video->x < 0) {
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@ -444,7 +444,7 @@ void GBVideoWriteLCDC(struct GBVideo* video, GBRegisterLCDC value) {
|
|||
video->modeEvent.callback = _endMode2;
|
||||
int32_t next = GB_VIDEO_MODE_2_LENGTH - 5; // TODO: Why is this fudge factor needed? Might be related to T-cycles for load/store differing
|
||||
mTimingDeschedule(&video->p->timing, &video->modeEvent);
|
||||
mTimingSchedule(&video->p->timing, &video->modeEvent, next << video->p->doubleSpeed);
|
||||
mTimingSchedule(&video->p->timing, &video->modeEvent, next << 1);
|
||||
|
||||
video->ly = 0;
|
||||
video->p->memory.io[GB_REG_LY] = 0;
|
||||
|
@ -471,7 +471,7 @@ void GBVideoWriteLCDC(struct GBVideo* video, GBRegisterLCDC value) {
|
|||
|
||||
mTimingDeschedule(&video->p->timing, &video->modeEvent);
|
||||
mTimingDeschedule(&video->p->timing, &video->frameEvent);
|
||||
mTimingSchedule(&video->p->timing, &video->frameEvent, GB_VIDEO_TOTAL_LENGTH);
|
||||
mTimingSchedule(&video->p->timing, &video->frameEvent, GB_VIDEO_TOTAL_LENGTH << 1);
|
||||
}
|
||||
video->p->memory.io[GB_REG_STAT] = video->stat;
|
||||
}
|
||||
|
|
|
@ -61,6 +61,7 @@ void SM83Reset(struct SM83Core* cpu) {
|
|||
|
||||
cpu->instruction = 0;
|
||||
|
||||
cpu->tMultiplier = 2;
|
||||
cpu->cycles = 0;
|
||||
cpu->nextEvent = 0;
|
||||
cpu->executionState = SM83_CORE_FETCH;
|
||||
|
@ -102,7 +103,7 @@ static void _SM83InstructionIRQ(struct SM83Core* cpu) {
|
|||
}
|
||||
|
||||
static void _SM83Step(struct SM83Core* cpu) {
|
||||
++cpu->cycles;
|
||||
cpu->cycles += cpu->tMultiplier;
|
||||
enum SM83ExecutionState state = cpu->executionState;
|
||||
cpu->executionState = SM83_CORE_IDLE_0;
|
||||
switch (state) {
|
||||
|
@ -147,23 +148,31 @@ static void _SM83Step(struct SM83Core* cpu) {
|
|||
}
|
||||
}
|
||||
|
||||
static inline bool _SM83TickInternal(struct SM83Core* cpu) {
|
||||
bool running = true;
|
||||
_SM83Step(cpu);
|
||||
int t = cpu->tMultiplier;
|
||||
if (cpu->cycles + t * 2 >= cpu->nextEvent) {
|
||||
int32_t diff = cpu->nextEvent - cpu->cycles;
|
||||
cpu->cycles = cpu->nextEvent;
|
||||
cpu->executionState += diff >> (t - 1); // NB: This assumes tMultiplier is either 1 or 2
|
||||
cpu->irqh.processEvents(cpu);
|
||||
cpu->cycles += (SM83_CORE_EXECUTE - cpu->executionState) * t;
|
||||
running = false;
|
||||
} else {
|
||||
cpu->cycles += t * 2;
|
||||
}
|
||||
cpu->executionState = SM83_CORE_FETCH;
|
||||
cpu->instruction(cpu);
|
||||
cpu->cycles += t;
|
||||
return running;
|
||||
}
|
||||
|
||||
void SM83Tick(struct SM83Core* cpu) {
|
||||
while (cpu->cycles >= cpu->nextEvent) {
|
||||
cpu->irqh.processEvents(cpu);
|
||||
}
|
||||
_SM83Step(cpu);
|
||||
if (cpu->cycles + 2 >= cpu->nextEvent) {
|
||||
int32_t diff = cpu->nextEvent - cpu->cycles;
|
||||
cpu->cycles = cpu->nextEvent;
|
||||
cpu->executionState += diff;
|
||||
cpu->irqh.processEvents(cpu);
|
||||
cpu->cycles += SM83_CORE_EXECUTE - cpu->executionState;
|
||||
} else {
|
||||
cpu->cycles += 2;
|
||||
}
|
||||
cpu->executionState = SM83_CORE_FETCH;
|
||||
cpu->instruction(cpu);
|
||||
++cpu->cycles;
|
||||
_SM83TickInternal(cpu);
|
||||
}
|
||||
|
||||
void SM83Run(struct SM83Core* cpu) {
|
||||
|
@ -173,19 +182,6 @@ void SM83Run(struct SM83Core* cpu) {
|
|||
cpu->irqh.processEvents(cpu);
|
||||
break;
|
||||
}
|
||||
_SM83Step(cpu);
|
||||
if (cpu->cycles + 2 >= cpu->nextEvent) {
|
||||
int32_t diff = cpu->nextEvent - cpu->cycles;
|
||||
cpu->cycles = cpu->nextEvent;
|
||||
cpu->executionState += diff;
|
||||
cpu->irqh.processEvents(cpu);
|
||||
cpu->cycles += SM83_CORE_EXECUTE - cpu->executionState;
|
||||
running = false;
|
||||
} else {
|
||||
cpu->cycles += 2;
|
||||
}
|
||||
cpu->executionState = SM83_CORE_FETCH;
|
||||
cpu->instruction(cpu);
|
||||
++cpu->cycles;
|
||||
running = _SM83TickInternal(cpu) && running;
|
||||
}
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue