mirror of https://github.com/mgba-emu/mgba.git
Clean up extra backslashes
This commit is contained in:
Jeffrey Pfau
parent
2d0c3bf275
commit
bc9d0690bb
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@ -357,8 +357,7 @@ void ARMStep(struct ARMCore* cpu) {
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// TODO
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#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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BODY;)
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DEFINE_INSTRUCTION_ARM(NAME, BODY;)
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#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
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DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
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@ -380,55 +379,55 @@ void ARMStep(struct ARMCore* cpu) {
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// Begin ALU definitions
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DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \
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int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \
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DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
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int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
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cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
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int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
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int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = ~cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \
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DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \
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DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d),
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int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \
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int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \
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DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d),
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int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
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int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \
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int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \
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DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d),
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int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
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int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \
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DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d),
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int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
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int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
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int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
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// End ALU definitions
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@ -461,28 +460,28 @@ DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address
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DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
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DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, \
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enum PrivilegeMode priv = cpu->privilegeMode; \
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ARMSetPrivilegeMode(cpu, MODE_USER); \
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cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); \
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
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enum PrivilegeMode priv = cpu->privilegeMode;
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ARMSetPrivilegeMode(cpu, MODE_USER);
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cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
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ARMSetPrivilegeMode(cpu, priv);)
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, \
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enum PrivilegeMode priv = cpu->privilegeMode; \
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ARMSetPrivilegeMode(cpu, MODE_USER); \
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cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); \
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
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enum PrivilegeMode priv = cpu->privilegeMode;
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ARMSetPrivilegeMode(cpu, MODE_USER);
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cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
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ARMSetPrivilegeMode(cpu, priv);)
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, \
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enum PrivilegeMode priv = cpu->privilegeMode; \
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ARMSetPrivilegeMode(cpu, MODE_USER); \
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cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]); \
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
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enum PrivilegeMode priv = cpu->privilegeMode;
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ARMSetPrivilegeMode(cpu, MODE_USER);
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cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
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ARMSetPrivilegeMode(cpu, priv);)
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, \
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enum PrivilegeMode priv = cpu->privilegeMode; \
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ARMSetPrivilegeMode(cpu, MODE_USER); \
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cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]); \
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DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
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enum PrivilegeMode priv = cpu->privilegeMode;
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ARMSetPrivilegeMode(cpu, MODE_USER);
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cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
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ARMSetPrivilegeMode(cpu, priv);)
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DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM, ARM_STUB)
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@ -495,21 +494,21 @@ DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
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// Begin branch definitions
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DEFINE_INSTRUCTION_ARM(B, \
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int32_t offset = opcode << 8; \
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offset >>= 6; \
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cpu->gprs[ARM_PC] += offset; \
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DEFINE_INSTRUCTION_ARM(B,
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int32_t offset = opcode << 8;
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offset >>= 6;
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cpu->gprs[ARM_PC] += offset;
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ARM_WRITE_PC;)
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DEFINE_INSTRUCTION_ARM(BL, ARM_STUB)
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DEFINE_INSTRUCTION_ARM(BX, \
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int rm = opcode & 0x0000000F; \
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_ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001); \
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cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE; \
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if (cpu->executionMode == MODE_THUMB) { \
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DEFINE_INSTRUCTION_ARM(BX,
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int rm = opcode & 0x0000000F;
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_ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
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cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
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if (cpu->executionMode == MODE_THUMB) {
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THUMB_WRITE_PC;
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} else { \
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ARM_WRITE_PC; \
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} else {
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ARM_WRITE_PC;
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})
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// End branch definitions
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@ -519,28 +518,28 @@ DEFINE_INSTRUCTION_ARM(BX, \
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DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
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DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
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DEFINE_INSTRUCTION_ARM(MSR, \
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int c = opcode & 0x00010000; \
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int f = opcode & 0x00080000; \
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int32_t operand; \
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if (opcode & 0x02000000) { \
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int rotate = (opcode & 0x00000F00) >> 8; \
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operand = ARM_ROR(opcode & 0x000000FF, rotate); \
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} else { \
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operand = cpu->gprs[opcode & 0x0000000F]; \
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} \
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int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0); \
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if (opcode & 0x00400000) { \
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mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK; \
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cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask); \
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} else { \
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if (mask & PSR_USER_MASK) { \
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK); \
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} \
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if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { \
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ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); \
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK); \
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} \
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DEFINE_INSTRUCTION_ARM(MSR,
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int c = opcode & 0x00010000;
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int f = opcode & 0x00080000;
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int32_t operand;
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if (opcode & 0x02000000) {
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int rotate = (opcode & 0x00000F00) >> 8;
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operand = ARM_ROR(opcode & 0x000000FF, rotate);
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} else {
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operand = cpu->gprs[opcode & 0x0000000F];
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}
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int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
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if (opcode & 0x00400000) {
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mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
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cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);
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} else {
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if (mask & PSR_USER_MASK) {
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
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}
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if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
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ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
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cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
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}
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})
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DEFINE_INSTRUCTION_ARM(MRS, ARM_STUB)
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@ -108,23 +108,23 @@ void ThumbStep(struct ARMCore* cpu) {
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#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
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COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \
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if (!immediate) { \
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cpu->gprs[rd] = cpu->gprs[rm]; \
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} else { \
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cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \
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cpu->gprs[rd] = cpu->gprs[rm] << immediate; \
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} \
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
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if (!immediate) {
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cpu->gprs[rd] = cpu->gprs[rm];
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} else {
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cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate));
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cpu->gprs[rd] = cpu->gprs[rm] << immediate;
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}
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THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
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if (!immediate) { \
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cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \
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cpu->gprs[rd] = 0; \
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} else { \
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cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \
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cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \
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} \
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if (!immediate) {
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cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
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cpu->gprs[rd] = 0;
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} else {
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cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1));
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cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
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}
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THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
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@ -185,38 +185,38 @@ DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu-
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, \
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int rs = cpu->gprs[rn] & 0xFF; \
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if (rs) { \
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if (rs < 32) { \
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cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
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cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs; \
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} else { \
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if (rs > 32) { \
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cpu->cpsr.c = 0; \
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} else { \
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cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
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} \
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cpu->gprs[rd] = 0; \
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} \
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} \
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
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int rs = cpu->gprs[rn] & 0xFF;
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if (rs) {
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if (rs < 32) {
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cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1));
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cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
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} else {
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if (rs > 32) {
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cpu->cpsr.c = 0;
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} else {
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cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
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}
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cpu->gprs[rd] = 0;
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}
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}
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THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, \
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int rs = cpu->gprs[rn] & 0xFF; \
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if (rs) { \
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if (rs < 32) { \
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cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \
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cpu->gprs[rd] >>= rs; \
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} else { \
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cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \
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if (cpu->cpsr.c) { \
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cpu->gprs[rd] = 0xFFFFFFFF; \
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} else { \
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cpu->gprs[rd] = 0; \
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} \
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} \
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} \
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
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int rs = cpu->gprs[rn] & 0xFF;
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if (rs) {
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if (rs < 32) {
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cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1));
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||||
cpu->gprs[rd] >>= rs;
|
||||
} else {
|
||||
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
|
||||
if (cpu->cpsr.c) {
|
||||
cpu->gprs[rd] = 0xFFFFFFFF;
|
||||
} else {
|
||||
cpu->gprs[rd] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
|
||||
|
||||
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
|
||||
|
|
@ -302,14 +302,14 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
|
|||
#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
|
||||
COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
|
||||
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
|
||||
if (!((1 << rn) & rs)) { \
|
||||
cpu->gprs[rn] = address; \
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
|
||||
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
|
||||
if (!((1 << rn) & rs)) {
|
||||
cpu->gprs[rn] = address;
|
||||
})
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
|
||||
DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
|
||||
cpu->gprs[rn] = address)
|
||||
|
||||
#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
|
||||
|
|
@ -338,77 +338,77 @@ DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
|
|||
DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
|
||||
DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
|
||||
opcode & 0x00FF, \
|
||||
cpu->gprs[ARM_SP], \
|
||||
(m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
|
||||
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
|
||||
+=, \
|
||||
, , \
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
|
||||
opcode & 0x00FF,
|
||||
cpu->gprs[ARM_SP],
|
||||
(m = 0x01, i = 0; i < 8; m <<= 1, ++i),
|
||||
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
|
||||
+=,
|
||||
, ,
|
||||
cpu->gprs[ARM_SP] = address)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
|
||||
opcode & 0x00FF, \
|
||||
cpu->gprs[ARM_SP], \
|
||||
(m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
|
||||
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
|
||||
+=, \
|
||||
, \
|
||||
cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
|
||||
address += 4;, \
|
||||
cpu->gprs[ARM_SP] = address; \
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
|
||||
opcode & 0x00FF,
|
||||
cpu->gprs[ARM_SP],
|
||||
(m = 0x01, i = 0; i < 8; m <<= 1, ++i),
|
||||
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
|
||||
+=,
|
||||
,
|
||||
cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE;
|
||||
address += 4;,
|
||||
cpu->gprs[ARM_SP] = address;
|
||||
THUMB_WRITE_PC;)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
|
||||
opcode & 0x00FF, \
|
||||
cpu->gprs[ARM_SP] - 4, \
|
||||
(m = 0x80, i = 7; m; m >>= 1, --i), \
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
|
||||
-=, \
|
||||
, , \
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
|
||||
opcode & 0x00FF,
|
||||
cpu->gprs[ARM_SP] - 4,
|
||||
(m = 0x80, i = 7; m; m >>= 1, --i),
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
|
||||
-=,
|
||||
, ,
|
||||
cpu->gprs[ARM_SP] = address + 4)
|
||||
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
|
||||
opcode & 0x00FF, \
|
||||
cpu->gprs[ARM_SP] - 4, \
|
||||
(m = 0x80, i = 7; m; m >>= 1, --i), \
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
|
||||
-=, \
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
|
||||
address -= 4;, \
|
||||
, \
|
||||
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
|
||||
opcode & 0x00FF,
|
||||
cpu->gprs[ARM_SP] - 4,
|
||||
(m = 0x80, i = 7; m; m >>= 1, --i),
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
|
||||
-=,
|
||||
cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]);
|
||||
address -= 4;,
|
||||
,
|
||||
cpu->gprs[ARM_SP] = address + 4)
|
||||
|
||||
DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
|
||||
DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
|
||||
DEFINE_INSTRUCTION_THUMB(B, \
|
||||
int16_t immediate = (opcode & 0x07FF) << 5; \
|
||||
cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4); \
|
||||
DEFINE_INSTRUCTION_THUMB(B,
|
||||
int16_t immediate = (opcode & 0x07FF) << 5;
|
||||
cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
|
||||
THUMB_WRITE_PC;)
|
||||
|
||||
DEFINE_INSTRUCTION_THUMB(BL1, \
|
||||
int16_t immediate = (opcode & 0x07FF) << 5; \
|
||||
DEFINE_INSTRUCTION_THUMB(BL1,
|
||||
int16_t immediate = (opcode & 0x07FF) << 5;
|
||||
cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
|
||||
|
||||
DEFINE_INSTRUCTION_THUMB(BL2, \
|
||||
uint16_t immediate = (opcode & 0x07FF) << 1; \
|
||||
uint32_t pc = cpu->gprs[ARM_PC]; \
|
||||
cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
|
||||
cpu->gprs[ARM_LR] = pc - 1; \
|
||||
DEFINE_INSTRUCTION_THUMB(BL2,
|
||||
uint16_t immediate = (opcode & 0x07FF) << 1;
|
||||
uint32_t pc = cpu->gprs[ARM_PC];
|
||||
cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
|
||||
cpu->gprs[ARM_LR] = pc - 1;
|
||||
THUMB_WRITE_PC;)
|
||||
|
||||
DEFINE_INSTRUCTION_THUMB(BX, \
|
||||
int rm = (opcode >> 3) & 0xF; \
|
||||
DEFINE_INSTRUCTION_THUMB(BX,
|
||||
int rm = (opcode >> 3) & 0xF;
|
||||
_ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
|
||||
int misalign = 0;
|
||||
if (rm == ARM_PC) {
|
||||
misalign = cpu->gprs[rm] & 0x00000002;
|
||||
}
|
||||
cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign; \
|
||||
if (cpu->executionMode == MODE_THUMB) { \
|
||||
THUMB_WRITE_PC; \
|
||||
} else { \
|
||||
ARM_WRITE_PC; \
|
||||
cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign;
|
||||
if (cpu->executionMode == MODE_THUMB) {
|
||||
THUMB_WRITE_PC;
|
||||
} else {
|
||||
ARM_WRITE_PC;
|
||||
})
|
||||
|
||||
DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))
|
||||
|
|
|
|||
Loading…
Reference in New Issue