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Clean up extra backslashes

This commit is contained in:
Jeffrey Pfau 2013-04-16 19:29:00 -07:00
parent 2d0c3bf275
commit bc9d0690bb
2 changed files with 169 additions and 170 deletions
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139
src/arm/isa-arm.c
View File

@ -357,8 +357,7 @@ void ARMStep(struct ARMCore* cpu) {
// TODO // TODO
#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \ #define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME, ADDRESS, S_PRE, S_POST, BODY) \
DEFINE_INSTRUCTION_ARM(NAME, \ DEFINE_INSTRUCTION_ARM(NAME, BODY;)
BODY;)
#define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \ #define DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(NAME, BODY) \
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \ DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_EX_ARM(NAME ## DA, ADDR_MODE_4_DA, , , BODY) \
@ -380,55 +379,55 @@ void ARMStep(struct ARMCore* cpu) {
// Begin ALU definitions // Begin ALU definitions
DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, ) cpu->gprs[rd] = cpu->gprs[rn] + cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(cpu->gprs[rn], shifterOperand, cpu->gprs[rd]),
int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c; \ int32_t shifterOperand = cpu->shifterOperand + cpu->cpsr.c;
cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, ) cpu->gprs[rd] = cpu->gprs[rn] + shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, ) cpu->gprs[rd] = cpu->gprs[rn] & cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, ) cpu->gprs[rd] = cpu->gprs[rn] & ~cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \ DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, ) int32_t aluOut = cpu->gprs[rn] + cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \ DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, ) int32_t aluOut = cpu->gprs[rn] - cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, ) cpu->gprs[rd] = cpu->gprs[rn] ^ cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = cpu->shifterOperand;, ) cpu->gprs[rd] = cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = ~cpu->shifterOperand;, ) cpu->gprs[rd] = ~cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]), \ DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, cpu->gprs[rd]),
cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, ) cpu->gprs[rd] = cpu->gprs[rn] | cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d), \ DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, cpu->gprs[rn], d),
int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d) int32_t d = cpu->shifterOperand - cpu->gprs[rn];, cpu->gprs[rd] = d)
DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d), \ DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_S(cpu->shifterOperand, n, d),
int32_t n = cpu->gprs[rn] + !cpu->cpsr.c; \ int32_t n = cpu->gprs[rn] + !cpu->cpsr.c;
int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d) int32_t d = cpu->shifterOperand - n;, cpu->gprs[rd] = d)
DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d), \ DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_S(cpu->gprs[rn], shifterOperand, d),
int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c; \ int32_t shifterOperand = cpu->shifterOperand + !cpu->cpsr.c;
int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d) int32_t d = cpu->gprs[rn] - shifterOperand;, cpu->gprs[rd] = d)
DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d), \ DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(cpu->gprs[rn], cpu->shifterOperand, d),
int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d) int32_t d = cpu->gprs[rn] - cpu->shifterOperand;, cpu->gprs[rd] = d)
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \ DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, ) int32_t aluOut = cpu->gprs[rn] ^ cpu->shifterOperand;, )
DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut), \ DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifterOperand, aluOut),
int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, ) int32_t aluOut = cpu->gprs[rn] & cpu->shifterOperand;, )
// End ALU definitions // End ALU definitions
@ -461,28 +460,28 @@ DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address
DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd])) DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd])) DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, \ DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT,
enum PrivilegeMode priv = cpu->privilegeMode; \ enum PrivilegeMode priv = cpu->privilegeMode;
ARMSetPrivilegeMode(cpu, MODE_USER); \ ARMSetPrivilegeMode(cpu, MODE_USER);
cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); \ cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address);
ARMSetPrivilegeMode(cpu, priv);) ARMSetPrivilegeMode(cpu, priv);)
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, \ DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT,
enum PrivilegeMode priv = cpu->privilegeMode; \ enum PrivilegeMode priv = cpu->privilegeMode;
ARMSetPrivilegeMode(cpu, MODE_USER); \ ARMSetPrivilegeMode(cpu, MODE_USER);
cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); \ cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address);
ARMSetPrivilegeMode(cpu, priv);) ARMSetPrivilegeMode(cpu, priv);)
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, \ DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT,
enum PrivilegeMode priv = cpu->privilegeMode; \ enum PrivilegeMode priv = cpu->privilegeMode;
ARMSetPrivilegeMode(cpu, MODE_USER); \ ARMSetPrivilegeMode(cpu, MODE_USER);
cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]); \ cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]);
ARMSetPrivilegeMode(cpu, priv);) ARMSetPrivilegeMode(cpu, priv);)
DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT, \ DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRT,
enum PrivilegeMode priv = cpu->privilegeMode; \ enum PrivilegeMode priv = cpu->privilegeMode;
ARMSetPrivilegeMode(cpu, MODE_USER); \ ARMSetPrivilegeMode(cpu, MODE_USER);
cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]); \ cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]);
ARMSetPrivilegeMode(cpu, priv);) ARMSetPrivilegeMode(cpu, priv);)
DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM, ARM_STUB) DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM, ARM_STUB)
@ -495,21 +494,21 @@ DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB)
// Begin branch definitions // Begin branch definitions
DEFINE_INSTRUCTION_ARM(B, \ DEFINE_INSTRUCTION_ARM(B,
int32_t offset = opcode << 8; \ int32_t offset = opcode << 8;
offset >>= 6; \ offset >>= 6;
cpu->gprs[ARM_PC] += offset; \ cpu->gprs[ARM_PC] += offset;
ARM_WRITE_PC;) ARM_WRITE_PC;)
DEFINE_INSTRUCTION_ARM(BL, ARM_STUB) DEFINE_INSTRUCTION_ARM(BL, ARM_STUB)
DEFINE_INSTRUCTION_ARM(BX, \ DEFINE_INSTRUCTION_ARM(BX,
int rm = opcode & 0x0000000F; \ int rm = opcode & 0x0000000F;
_ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001); \ _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE; \ cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE;
if (cpu->executionMode == MODE_THUMB) { \ if (cpu->executionMode == MODE_THUMB) {
THUMB_WRITE_PC; THUMB_WRITE_PC;
} else { \ } else {
ARM_WRITE_PC; \ ARM_WRITE_PC;
}) })
// End branch definitions // End branch definitions
@ -519,28 +518,28 @@ DEFINE_INSTRUCTION_ARM(BX, \
DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience DEFINE_INSTRUCTION_ARM(BKPT, ARM_STUB) // Not strictly in ARMv4T, but here for convenience
DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode DEFINE_INSTRUCTION_ARM(ILL, ARM_STUB) // Illegal opcode
DEFINE_INSTRUCTION_ARM(MSR, \ DEFINE_INSTRUCTION_ARM(MSR,
int c = opcode & 0x00010000; \ int c = opcode & 0x00010000;
int f = opcode & 0x00080000; \ int f = opcode & 0x00080000;
int32_t operand; \ int32_t operand;
if (opcode & 0x02000000) { \ if (opcode & 0x02000000) {
int rotate = (opcode & 0x00000F00) >> 8; \ int rotate = (opcode & 0x00000F00) >> 8;
operand = ARM_ROR(opcode & 0x000000FF, rotate); \ operand = ARM_ROR(opcode & 0x000000FF, rotate);
} else { \ } else {
operand = cpu->gprs[opcode & 0x0000000F]; \ operand = cpu->gprs[opcode & 0x0000000F];
} \ }
int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0); \ int32_t mask = (c ? 0x000000FF : 0) | (f ? 0xFF000000 : 0);
if (opcode & 0x00400000) { \ if (opcode & 0x00400000) {
mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK; \ mask &= PSR_USER_MASK | PSR_PRIV_MASK | PSR_STATE_MASK;
cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask); \ cpu->spsr.packed = (cpu->spsr.packed & ~mask) | (operand & mask);
} else { \ } else {
if (mask & PSR_USER_MASK) { \ if (mask & PSR_USER_MASK) {
cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK); \ cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_USER_MASK) | (operand & PSR_USER_MASK);
} \ }
if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) { \ if (cpu->privilegeMode != MODE_USER && (mask & PSR_PRIV_MASK)) {
ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010)); \ ARMSetPrivilegeMode(cpu, (enum PrivilegeMode) ((operand & 0x0000000F) | 0x00000010));
cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK); \ cpu->cpsr.packed = (cpu->cpsr.packed & ~PSR_PRIV_MASK) | (operand & PSR_PRIV_MASK);
} \ }
}) })
DEFINE_INSTRUCTION_ARM(MRS, ARM_STUB) DEFINE_INSTRUCTION_ARM(MRS, ARM_STUB)

200
src/arm/isa-thumb.c
View File

@ -108,23 +108,23 @@ void ThumbStep(struct ARMCore* cpu) {
#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \ #define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY) COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, \ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
if (!immediate) { \ if (!immediate) {
cpu->gprs[rd] = cpu->gprs[rm]; \ cpu->gprs[rd] = cpu->gprs[rm];
} else { \ } else {
cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); \ cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate));
cpu->gprs[rd] = cpu->gprs[rm] << immediate; \ cpu->gprs[rd] = cpu->gprs[rm] << immediate;
} \ }
THUMB_NEUTRAL_S( , , cpu->gprs[rd]);) THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
if (!immediate) { \ if (!immediate) {
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); \ cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
cpu->gprs[rd] = 0; \ cpu->gprs[rd] = 0;
} else { \ } else {
cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); \ cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1));
cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; \ cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
} \ }
THUMB_NEUTRAL_S( , , cpu->gprs[rd]);) THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB) DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
@ -185,38 +185,38 @@ DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, THUMB_SUBTRACTION(cpu->gprs[rd], cpu-
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd])) DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, cpu->gprs[rd] = cpu->gprs[rd] & cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd])) DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, cpu->gprs[rd] = cpu->gprs[rd] ^ cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB) DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, \ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
int rs = cpu->gprs[rn] & 0xFF; \ int rs = cpu->gprs[rn] & 0xFF;
if (rs) { \ if (rs) {
if (rs < 32) { \ if (rs < 32) {
cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \ cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1));
cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs; \ cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
} else { \ } else {
if (rs > 32) { \ if (rs > 32) {
cpu->cpsr.c = 0; \ cpu->cpsr.c = 0;
} else { \ } else {
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \ cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
} \ }
cpu->gprs[rd] = 0; \ cpu->gprs[rd] = 0;
} \ }
} \ }
THUMB_NEUTRAL_S( , , cpu->gprs[rd])) THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, \ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
int rs = cpu->gprs[rn] & 0xFF; \ int rs = cpu->gprs[rn] & 0xFF;
if (rs) { \ if (rs) {
if (rs < 32) { \ if (rs < 32) {
cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); \ cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1));
cpu->gprs[rd] >>= rs; \ cpu->gprs[rd] >>= rs;
} else { \ } else {
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); \ cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
if (cpu->cpsr.c) { \ if (cpu->cpsr.c) {
cpu->gprs[rd] = 0xFFFFFFFF; \ cpu->gprs[rd] = 0xFFFFFFFF;
} else { \ } else {
cpu->gprs[rd] = 0; \ cpu->gprs[rd] = 0;
} \ }
} \ }
} \ }
THUMB_NEUTRAL_S( , , cpu->gprs[rd])) THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB) DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
@ -302,14 +302,14 @@ DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \ #define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK) COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\ DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \ cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
if (!((1 << rn) & rs)) { \ if (!((1 << rn) & rs)) {
cpu->gprs[rn] = address; \ cpu->gprs[rn] = address;
}) })
DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \ DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA,
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \ cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
cpu->gprs[rn] = address) cpu->gprs[rn] = address)
#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \ #define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
@ -338,77 +338,77 @@ DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2) DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2) DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP,
opcode & 0x00FF, \ opcode & 0x00FF,
cpu->gprs[ARM_SP], \ cpu->gprs[ARM_SP],
(m = 0x01, i = 0; i < 8; m <<= 1, ++i), \ (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \ cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
+=, \ +=,
, , \ , ,
cpu->gprs[ARM_SP] = address) cpu->gprs[ARM_SP] = address)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR,
opcode & 0x00FF, \ opcode & 0x00FF,
cpu->gprs[ARM_SP], \ cpu->gprs[ARM_SP],
(m = 0x01, i = 0; i < 8; m <<= 1, ++i), \ (m = 0x01, i = 0; i < 8; m <<= 1, ++i),
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \ cpu->gprs[i] = cpu->memory->load32(cpu->memory, address),
+=, \ +=,
, \ ,
cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \ cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE;
address += 4;, \ address += 4;,
cpu->gprs[ARM_SP] = address; \ cpu->gprs[ARM_SP] = address;
THUMB_WRITE_PC;) THUMB_WRITE_PC;)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH,
opcode & 0x00FF, \ opcode & 0x00FF,
cpu->gprs[ARM_SP] - 4, \ cpu->gprs[ARM_SP] - 4,
(m = 0x80, i = 7; m; m >>= 1, --i), \ (m = 0x80, i = 7; m; m >>= 1, --i),
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \ cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
-=, \ -=,
, , \ , ,
cpu->gprs[ARM_SP] = address + 4) cpu->gprs[ARM_SP] = address + 4)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR,
opcode & 0x00FF, \ opcode & 0x00FF,
cpu->gprs[ARM_SP] - 4, \ cpu->gprs[ARM_SP] - 4,
(m = 0x80, i = 7; m; m >>= 1, --i), \ (m = 0x80, i = 7; m; m >>= 1, --i),
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \ cpu->memory->store32(cpu->memory, address, cpu->gprs[i]),
-=, \ -=,
cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \ cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]);
address -= 4;, \ address -= 4;,
, \ ,
cpu->gprs[ARM_SP] = address + 4) cpu->gprs[ARM_SP] = address + 4)
DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB) DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB) DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
DEFINE_INSTRUCTION_THUMB(B, \ DEFINE_INSTRUCTION_THUMB(B,
int16_t immediate = (opcode & 0x07FF) << 5; \ int16_t immediate = (opcode & 0x07FF) << 5;
cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4); \ cpu->gprs[ARM_PC] += (((int32_t) immediate) >> 4);
THUMB_WRITE_PC;) THUMB_WRITE_PC;)
DEFINE_INSTRUCTION_THUMB(BL1, \ DEFINE_INSTRUCTION_THUMB(BL1,
int16_t immediate = (opcode & 0x07FF) << 5; \ int16_t immediate = (opcode & 0x07FF) << 5;
cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);) cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 7);)
DEFINE_INSTRUCTION_THUMB(BL2, \ DEFINE_INSTRUCTION_THUMB(BL2,
uint16_t immediate = (opcode & 0x07FF) << 1; \ uint16_t immediate = (opcode & 0x07FF) << 1;
uint32_t pc = cpu->gprs[ARM_PC]; \ uint32_t pc = cpu->gprs[ARM_PC];
cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \ cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate;
cpu->gprs[ARM_LR] = pc - 1; \ cpu->gprs[ARM_LR] = pc - 1;
THUMB_WRITE_PC;) THUMB_WRITE_PC;)
DEFINE_INSTRUCTION_THUMB(BX, \ DEFINE_INSTRUCTION_THUMB(BX,
int rm = (opcode >> 3) & 0xF; \ int rm = (opcode >> 3) & 0xF;
_ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001); _ARMSetMode(cpu, cpu->gprs[rm] & 0x00000001);
int misalign = 0; int misalign = 0;
if (rm == ARM_PC) { if (rm == ARM_PC) {
misalign = cpu->gprs[rm] & 0x00000002; misalign = cpu->gprs[rm] & 0x00000002;
} }
cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign; \ cpu->gprs[ARM_PC] = cpu->gprs[rm] & 0xFFFFFFFE - misalign;
if (cpu->executionMode == MODE_THUMB) { \ if (cpu->executionMode == MODE_THUMB) {
THUMB_WRITE_PC; \ THUMB_WRITE_PC;
} else { \ } else {
ARM_WRITE_PC; \ ARM_WRITE_PC;
}) })
DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF)) DEFINE_INSTRUCTION_THUMB(SWI, cpu->board->swi16(cpu->board, opcode & 0xFF))