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Decode MSR and MRS

This commit is contained in:
Jeffrey Pfau 2014-07-12 00:29:00 -07:00
parent a2eec31632
commit b41e11d4c1
3 changed files with 68 additions and 13 deletions
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70
src/arm/decoder-arm.c
View File

@ -362,23 +362,67 @@ DEFINE_DECODER_ARM(BX, BX,
// Begin coprocessor definitions // Begin coprocessor definitions
DEFINE_DECODER_ARM(CDP, ILL,) DEFINE_DECODER_ARM(CDP, ILL, info->operandFormat = ARM_OPERAND_NONE;)
DEFINE_DECODER_ARM(LDC, ILL,) DEFINE_DECODER_ARM(LDC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
DEFINE_DECODER_ARM(STC, ILL,) DEFINE_DECODER_ARM(STC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
DEFINE_DECODER_ARM(MCR, ILL,) DEFINE_DECODER_ARM(MCR, ILL, info->operandFormat = ARM_OPERAND_NONE;)
DEFINE_DECODER_ARM(MRC, ILL,) DEFINE_DECODER_ARM(MRC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
// Begin miscellaneous definitions // Begin miscellaneous definitions
DEFINE_DECODER_ARM(BKPT, BKPT,) // Not strictly in ARMv4T, but here for convenience DEFINE_DECODER_ARM(BKPT, BKPT, info->operandFormat = ARM_OPERAND_NONE;) // Not strictly in ARMv4T, but here for convenience
DEFINE_DECODER_ARM(ILL, ILL,) // Illegal opcode DEFINE_DECODER_ARM(ILL, ILL, info->operandFormat = ARM_OPERAND_NONE;) // Illegal opcode
DEFINE_DECODER_ARM(MSR, MSR, info->affectsCPSR = 1;) DEFINE_DECODER_ARM(MSR, MSR,
DEFINE_DECODER_ARM(MSRR, MSR, info->affectsCPSR = 1;) info->affectsCPSR = 1;
DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;) info->op1.reg = ARM_CPSR;
DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;) info->op2.reg = opcode & 0x0000000F;
DEFINE_DECODER_ARM(MSRI, MSR, info->affectsCPSR = 1;) info->operandFormat = ARM_OPERAND_REGISTER_1 |
DEFINE_DECODER_ARM(MSRRI, MSR, info->affectsCPSR = 1;) ARM_OPERAND_AFFECTED_1 |
ARM_OPERAND_REGISTER_2;)
DEFINE_DECODER_ARM(MSRR, MSR,
info->op1.reg = ARM_SPSR;
info->op2.reg = opcode & 0x0000000F;
info->operandFormat = ARM_OPERAND_REGISTER_1 |
ARM_OPERAND_AFFECTED_1 |
ARM_OPERAND_REGISTER_2;)
DEFINE_DECODER_ARM(MRS, MRS, info->affectsCPSR = 1;
info->affectsCPSR = 1;
info->op1.reg = (opcode >> 12) & 0xF;
info->op2.reg = ARM_CPSR;
info->operandFormat = ARM_OPERAND_REGISTER_1 |
ARM_OPERAND_AFFECTED_1 |
ARM_OPERAND_REGISTER_2;)
DEFINE_DECODER_ARM(MRSR, MRS, info->affectsCPSR = 1;
info->affectsCPSR = 1;
info->op1.reg = (opcode >> 12) & 0xF;
info->op2.reg = ARM_SPSR;
info->operandFormat = ARM_OPERAND_REGISTER_1 |
ARM_OPERAND_AFFECTED_1 |
ARM_OPERAND_REGISTER_2;)
DEFINE_DECODER_ARM(MSRI, MSR, info->affectsCPSR = 1;
int rotate = (opcode & 0x00000F00) >> 7;
int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
info->affectsCPSR = 1;
info->op1.reg = ARM_CPSR;
info->op2.immediate = operand;
info->operandFormat = ARM_OPERAND_REGISTER_1 |
ARM_OPERAND_AFFECTED_1 |
ARM_OPERAND_IMMEDIATE_2;)
DEFINE_DECODER_ARM(MSRRI, MSR, info->affectsCPSR = 1;
int rotate = (opcode & 0x00000F00) >> 7;
int32_t operand = ARM_ROR(opcode & 0x000000FF, rotate);
info->affectsCPSR = 1;
info->op1.reg = ARM_SPSR;
info->op2.immediate = operand;
info->operandFormat = ARM_OPERAND_REGISTER_1 |
ARM_OPERAND_AFFECTED_1 |
ARM_OPERAND_IMMEDIATE_2;)
DEFINE_DECODER_ARM(SWI, SWI, DEFINE_DECODER_ARM(SWI, SWI,
info->op1.immediate = opcode & 0xFFFFFF; info->op1.immediate = opcode & 0xFFFFFF;

6
src/arm/decoder.c
View File

@ -46,6 +46,12 @@ static int _decodeRegister(int reg, char* buffer, int blen) {
case ARM_PC: case ARM_PC:
strncpy(buffer, "pc", blen - 1); strncpy(buffer, "pc", blen - 1);
return 2; return 2;
case ARM_CPSR:
strncpy(buffer, "cpsr", blen - 1);
return 4;
case ARM_SPSR:
strncpy(buffer, "spsr", blen - 1);
return 4;
default: default:
return snprintf(buffer, blen - 1, "r%i", reg); return snprintf(buffer, blen - 1, "r%i", reg);
} }

5
src/arm/decoder.h
View File

@ -166,6 +166,11 @@ enum ARMMnemonic {
ARM_MN_MAX ARM_MN_MAX
}; };
enum {
ARM_CPSR = 16,
ARM_SPSR = 17
};
struct ARMInstructionInfo { struct ARMInstructionInfo {
enum ExecutionMode execMode; enum ExecutionMode execMode;
uint32_t opcode; uint32_t opcode;