mirror of https://github.com/mgba-emu/mgba.git
GB: Revamp IRQ handling based on new information
This commit is contained in:
Vicki Pfau
parent
148e7cd0b5
commit
a949fdfced
1
CHANGES
1
CHANGES
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@ -44,6 +44,7 @@ Bugfixes:
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- GBA Video: Fix broken sprite blending hack (fixes mgba.io/i/532)
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- GBA I/O: Fix reading from a few invalid I/O registers (fixes mgba.io/i/876)
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- GBA Savedata: Fix size of SRAM saves (fixes mgba.io/i/883)
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- GB: Revamp IRQ handling based on new information
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Misc:
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- GBA Timer: Use global cycles for timers
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- GBA: Extend oddly-sized ROMs to full address space (fixes mgba.io/i/722)
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@ -42,7 +42,7 @@ mLOG_DECLARE_CATEGORY(GB_STATE);
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* | 0x00036 - 0x00037: Index address
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* | 0x00038: Bus value
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* | 0x00039: Execution state
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* | 0x0003A - 0x0003B: IRQ vector
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* | 0x0003A - 0x0003B: Reserved
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* | 0x0003C - 0x0003F: EI pending cycles
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* | 0x00040 - 0x00043: Reserved (DI pending cycles)
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* | 0x00044 - 0x00047: Flags
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@ -287,7 +287,7 @@ struct GBSerializedState {
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uint8_t bus;
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uint8_t executionState;
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uint16_t irqVector;
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uint16_t reserved;
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uint32_t eiPending;
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int32_t reservedDiPending;
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@ -66,6 +66,7 @@ struct LR35902InterruptHandler {
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void (*reset)(struct LR35902Core* cpu);
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void (*processEvents)(struct LR35902Core* cpu);
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void (*setInterrupts)(struct LR35902Core* cpu, bool enable);
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uint16_t (*irqVector)(struct LR35902Core* cpu);
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void (*halt)(struct LR35902Core* cpu);
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void (*stop)(struct LR35902Core* cpu);
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@ -118,7 +119,6 @@ struct LR35902Core {
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LR35902Instruction instruction;
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bool irqPending;
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uint16_t irqVector;
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struct LR35902Memory memory;
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struct LR35902InterruptHandler irqh;
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@ -136,7 +136,7 @@ void LR35902HotplugAttach(struct LR35902Core* cpu, size_t slot);
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void LR35902HotplugDetach(struct LR35902Core* cpu, size_t slot);
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void LR35902Reset(struct LR35902Core* cpu);
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void LR35902RaiseIRQ(struct LR35902Core* cpu, uint8_t vector);
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void LR35902RaiseIRQ(struct LR35902Core* cpu);
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void LR35902Tick(struct LR35902Core* cpu);
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void LR35902Run(struct LR35902Core* cpu);
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55
src/gb/gb.c
55
src/gb/gb.c
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@ -39,6 +39,7 @@ static void GBDeinit(struct mCPUComponent* component);
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static void GBInterruptHandlerInit(struct LR35902InterruptHandler* irqh);
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static void GBProcessEvents(struct LR35902Core* cpu);
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static void GBSetInterrupts(struct LR35902Core* cpu, bool enable);
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static uint16_t GBIRQVector(struct LR35902Core* cpu);
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static void GBIllegal(struct LR35902Core* cpu);
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static void GBStop(struct LR35902Core* cpu);
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@ -371,6 +372,7 @@ void GBInterruptHandlerInit(struct LR35902InterruptHandler* irqh) {
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irqh->reset = GBReset;
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irqh->processEvents = GBProcessEvents;
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irqh->setInterrupts = GBSetInterrupts;
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irqh->irqVector = GBIRQVector;
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irqh->hitIllegal = GBIllegal;
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irqh->stop = GBStop;
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irqh->halt = GBHalt;
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@ -596,31 +598,7 @@ void GBUpdateIRQs(struct GB* gb) {
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if (!gb->memory.ime || gb->cpu->irqPending) {
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return;
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}
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if (irqs & (1 << GB_IRQ_VBLANK)) {
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LR35902RaiseIRQ(gb->cpu, GB_VECTOR_VBLANK);
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_VBLANK);
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return;
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}
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if (irqs & (1 << GB_IRQ_LCDSTAT)) {
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LR35902RaiseIRQ(gb->cpu, GB_VECTOR_LCDSTAT);
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_LCDSTAT);
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return;
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}
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if (irqs & (1 << GB_IRQ_TIMER)) {
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LR35902RaiseIRQ(gb->cpu, GB_VECTOR_TIMER);
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_TIMER);
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return;
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}
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if (irqs & (1 << GB_IRQ_SIO)) {
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LR35902RaiseIRQ(gb->cpu, GB_VECTOR_SIO);
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_SIO);
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return;
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}
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if (irqs & (1 << GB_IRQ_KEYPAD)) {
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LR35902RaiseIRQ(gb->cpu, GB_VECTOR_KEYPAD);
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_KEYPAD);
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}
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LR35902RaiseIRQ(gb->cpu);
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}
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void GBProcessEvents(struct LR35902Core* cpu) {
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@ -663,6 +641,33 @@ void GBSetInterrupts(struct LR35902Core* cpu, bool enable) {
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}
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}
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uint16_t GBIRQVector(struct LR35902Core* cpu) {
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struct GB* gb = (struct GB*) cpu->master;
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int irqs = gb->memory.ie & gb->memory.io[REG_IF];
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if (irqs & (1 << GB_IRQ_VBLANK)) {
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_VBLANK);
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return GB_VECTOR_VBLANK;
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}
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if (irqs & (1 << GB_IRQ_LCDSTAT)) {
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_LCDSTAT);
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return GB_VECTOR_LCDSTAT;
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}
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if (irqs & (1 << GB_IRQ_TIMER)) {
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_TIMER);
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return GB_VECTOR_TIMER;
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}
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if (irqs & (1 << GB_IRQ_SIO)) {
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_SIO);
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return GB_VECTOR_SIO;
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}
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if (irqs & (1 << GB_IRQ_KEYPAD)) {
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gb->memory.io[REG_IF] &= ~(1 << GB_IRQ_KEYPAD);
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return GB_VECTOR_KEYPAD;
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}
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return 0;
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}
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static void _enableInterrupts(struct mTiming* timing, void* user, uint32_t cyclesLate) {
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UNUSED(timing);
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UNUSED(cyclesLate);
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@ -47,7 +47,6 @@ void GBSerialize(struct GB* gb, struct GBSerializedState* state) {
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STORE_16LE(gb->cpu->index, 0, &state->cpu.index);
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state->cpu.bus = gb->cpu->bus;
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state->cpu.executionState = gb->cpu->executionState;
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STORE_16LE(gb->cpu->irqVector, 0, &state->cpu.irqVector);
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GBSerializedCpuFlags flags = 0;
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flags = GBSerializedCpuFlagsSetCondition(flags, gb->cpu->condition);
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@ -154,7 +153,6 @@ bool GBDeserialize(struct GB* gb, const struct GBSerializedState* state) {
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LOAD_16LE(gb->cpu->index, 0, &state->cpu.index);
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gb->cpu->bus = state->cpu.bus;
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gb->cpu->executionState = state->cpu.executionState;
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LOAD_16LE(gb->cpu->irqVector, 0, &state->cpu.irqVector);
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GBSerializedCpuFlags flags;
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LOAD_32LE(flags, 0, &state->cpu.flags);
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@ -70,9 +70,8 @@ void LR35902Reset(struct LR35902Core* cpu) {
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cpu->irqh.reset(cpu);
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}
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void LR35902RaiseIRQ(struct LR35902Core* cpu, uint8_t vector) {
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void LR35902RaiseIRQ(struct LR35902Core* cpu) {
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cpu->irqPending = true;
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cpu->irqVector = vector;
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}
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static void _LR35902InstructionIRQStall(struct LR35902Core* cpu) {
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@ -85,18 +84,19 @@ static void _LR35902InstructionIRQFinish(struct LR35902Core* cpu) {
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}
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static void _LR35902InstructionIRQDelay(struct LR35902Core* cpu) {
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cpu->index = cpu->sp + 1;
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cpu->bus = cpu->pc >> 8;
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--cpu->sp;
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cpu->index = cpu->sp;
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cpu->bus = cpu->pc;
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cpu->executionState = LR35902_CORE_MEMORY_STORE;
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cpu->instruction = _LR35902InstructionIRQFinish;
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cpu->pc = cpu->irqVector;
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cpu->pc = cpu->irqh.irqVector(cpu);
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cpu->memory.setActiveRegion(cpu, cpu->pc);
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}
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static void _LR35902InstructionIRQ(struct LR35902Core* cpu) {
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cpu->sp -= 2; /* TODO: Atomic incrementing? */
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--cpu->sp;
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cpu->index = cpu->sp;
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cpu->bus = cpu->pc;
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cpu->bus = cpu->pc >> 8;
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cpu->executionState = LR35902_CORE_MEMORY_STORE;
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cpu->instruction = _LR35902InstructionIRQDelay;
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}
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Binary file not shown.
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After Width: | Height: | Size: 518 B |
Binary file not shown.
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@ -0,0 +1,282 @@
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; this file was created with wlalink by ville helin <vhelin@iki.fi>.
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; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/interrupts/ie_push.gb".
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[labels]
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01:4bff print_load_font
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01:4c0c print_string
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01:4c16 print_a
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01:4c20 print_newline
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01:4c2b print_digit
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01:4c38 print_regs
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01:4c41 _print_sl_data0
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01:4c47 _print_sl_out0
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01:4c54 _print_sl_data1
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01:4c5a _print_sl_out1
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01:4c6c _print_sl_data2
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01:4c72 _print_sl_out2
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01:4c7f _print_sl_data3
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01:4c85 _print_sl_out3
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01:4c97 _print_sl_data4
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01:4c9d _print_sl_out4
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01:4caa _print_sl_data5
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01:4cb0 _print_sl_out5
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01:4cc2 _print_sl_data6
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01:4cc8 _print_sl_out6
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01:4cd5 _print_sl_data7
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01:4cdb _print_sl_out7
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01:4000 font
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00:c000 regs_save
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00:c000 regs_save.f
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00:c001 regs_save.a
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00:c002 regs_save.c
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00:c003 regs_save.b
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00:c004 regs_save.e
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00:c005 regs_save.d
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00:c006 regs_save.l
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00:c007 regs_save.h
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00:c008 regs_flags
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00:c009 regs_assert
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00:c009 regs_assert.f
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00:c00a regs_assert.a
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00:c00b regs_assert.c
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00:c00c regs_assert.b
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00:c00d regs_assert.e
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00:c00e regs_assert.d
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00:c00f regs_assert.l
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00:c010 regs_assert.h
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00:c011 memdump_len
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00:c012 memdump_addr
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01:47f0 memcpy
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01:47f9 memset
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01:4802 memcmp
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01:4810 clear_vram
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01:481a clear_oam
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01:4824 disable_lcd_safe
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01:482a _wait_ly_0
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01:4830 _wait_ly_1
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01:4839 reset_screen
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01:484d process_results
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01:4861 _wait_ly_2
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01:4867 _wait_ly_3
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01:487d _print_results_halt_0
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01:4880 _process_results_cb
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01:488b _print_sl_data8
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01:4895 _print_sl_out8
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01:48af _print_sl_data9
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01:48ba _print_sl_out9
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01:48d2 _print_sl_data10
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01:48de _print_sl_out10
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01:48df dump_mem
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01:48fe _dump_mem_line
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01:4928 _check_asserts
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01:4936 _print_sl_data11
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01:4939 _print_sl_out11
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01:4945 _print_sl_data12
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01:4947 _print_sl_out12
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01:494f _print_sl_data13
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01:4952 _print_sl_out13
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01:495c __check_assert_fail0
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01:4967 _print_sl_data14
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01:496a _print_sl_out14
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01:496d __check_assert_ok0
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01:4975 _print_sl_data15
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01:497a _print_sl_out15
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01:497c __check_assert_skip0
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01:4984 _print_sl_data16
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01:498c _print_sl_out16
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01:498c __check_assert_out0
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01:4998 _print_sl_data17
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01:499a _print_sl_out17
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01:49a2 _print_sl_data18
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01:49a5 _print_sl_out18
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01:49af __check_assert_fail1
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01:49ba _print_sl_data19
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01:49bd _print_sl_out19
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01:49c0 __check_assert_ok1
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01:49c8 _print_sl_data20
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01:49cd _print_sl_out20
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01:49cf __check_assert_skip1
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01:49d7 _print_sl_data21
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01:49df _print_sl_out21
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01:49df __check_assert_out1
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01:49ea _print_sl_data22
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01:49ed _print_sl_out22
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01:49f9 _print_sl_data23
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01:49fb _print_sl_out23
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01:4a03 _print_sl_data24
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01:4a06 _print_sl_out24
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01:4a10 __check_assert_fail2
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01:4a1b _print_sl_data25
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01:4a1e _print_sl_out25
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01:4a21 __check_assert_ok2
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01:4a29 _print_sl_data26
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01:4a2e _print_sl_out26
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01:4a30 __check_assert_skip2
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01:4a38 _print_sl_data27
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01:4a40 _print_sl_out27
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01:4a40 __check_assert_out2
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01:4a4c _print_sl_data28
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01:4a4e _print_sl_out28
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01:4a56 _print_sl_data29
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01:4a59 _print_sl_out29
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01:4a63 __check_assert_fail3
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01:4a6e _print_sl_data30
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01:4a71 _print_sl_out30
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01:4a74 __check_assert_ok3
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01:4a7c _print_sl_data31
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01:4a81 _print_sl_out31
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01:4a83 __check_assert_skip3
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01:4a8b _print_sl_data32
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01:4a93 _print_sl_out32
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01:4a93 __check_assert_out3
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01:4a9e _print_sl_data33
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01:4aa1 _print_sl_out33
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01:4aad _print_sl_data34
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01:4aaf _print_sl_out34
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01:4ab7 _print_sl_data35
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01:4aba _print_sl_out35
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01:4ac4 __check_assert_fail4
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01:4acf _print_sl_data36
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01:4ad2 _print_sl_out36
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01:4ad5 __check_assert_ok4
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01:4add _print_sl_data37
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01:4ae2 _print_sl_out37
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01:4ae4 __check_assert_skip4
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01:4aec _print_sl_data38
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01:4af4 _print_sl_out38
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01:4af4 __check_assert_out4
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01:4b00 _print_sl_data39
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01:4b02 _print_sl_out39
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01:4b0a _print_sl_data40
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01:4b0d _print_sl_out40
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01:4b17 __check_assert_fail5
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01:4b22 _print_sl_data41
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01:4b25 _print_sl_out41
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01:4b28 __check_assert_ok5
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01:4b30 _print_sl_data42
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01:4b35 _print_sl_out42
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01:4b37 __check_assert_skip5
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01:4b3f _print_sl_data43
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01:4b47 _print_sl_out43
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01:4b47 __check_assert_out5
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01:4b52 _print_sl_data44
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01:4b55 _print_sl_out44
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01:4b61 _print_sl_data45
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01:4b63 _print_sl_out45
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01:4b6b _print_sl_data46
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01:4b6e _print_sl_out46
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01:4b78 __check_assert_fail6
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01:4b83 _print_sl_data47
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01:4b86 _print_sl_out47
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01:4b89 __check_assert_ok6
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01:4b91 _print_sl_data48
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01:4b96 _print_sl_out48
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01:4b98 __check_assert_skip6
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01:4ba0 _print_sl_data49
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01:4ba8 _print_sl_out49
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01:4ba8 __check_assert_out6
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01:4bb4 _print_sl_data50
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01:4bb6 _print_sl_out50
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01:4bbe _print_sl_data51
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01:4bc1 _print_sl_out51
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01:4bcb __check_assert_fail7
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01:4bd6 _print_sl_data52
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01:4bd9 _print_sl_out52
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01:4bdc __check_assert_ok7
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01:4be4 _print_sl_data53
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01:4be9 _print_sl_out53
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01:4beb __check_assert_skip7
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01:4bf3 _print_sl_data54
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01:4bfb _print_sl_out54
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01:4bfb __check_assert_out7
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00:0200 round1
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00:0214 finish_round1
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00:021d round2
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00:0224 round3
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00:0235 target
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00:0238 finish_round3
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00:023f round4
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00:0253 finish_round4
|
||||
00:0270 _wait_ly_4
|
||||
00:0276 _wait_ly_5
|
||||
00:028c _print_results_halt_1
|
||||
00:028f _test_ok_cb_0
|
||||
00:0297 _print_sl_data55
|
||||
00:029f _print_sl_out55
|
||||
00:1000 fail_round1_nointr
|
||||
00:1017 _wait_ly_6
|
||||
00:101d _wait_ly_7
|
||||
00:1033 _print_results_halt_2
|
||||
00:1036 _test_failure_cb_0
|
||||
00:103e _print_sl_data56
|
||||
00:104f _print_sl_out56
|
||||
00:1052 fail_round1_nocancel
|
||||
00:1069 _wait_ly_8
|
||||
00:106f _wait_ly_9
|
||||
00:1085 _print_results_halt_3
|
||||
00:1088 _test_failure_cb_1
|
||||
00:1090 _print_sl_data57
|
||||
00:10a2 _print_sl_out57
|
||||
00:10a5 fail_round1_if
|
||||
00:10bc _wait_ly_10
|
||||
00:10c2 _wait_ly_11
|
||||
00:10d8 _print_results_halt_4
|
||||
00:10db _test_failure_cb_2
|
||||
00:10e3 _print_sl_data58
|
||||
00:10f3 _print_sl_out58
|
||||
00:10f6 fail_round2_intr
|
||||
00:110d _wait_ly_12
|
||||
00:1113 _wait_ly_13
|
||||
00:1129 _print_results_halt_5
|
||||
00:112c _test_failure_cb_3
|
||||
00:1134 _print_sl_data59
|
||||
00:1146 _print_sl_out59
|
||||
00:1149 fail_round3_nointr
|
||||
00:1160 _wait_ly_14
|
||||
00:1166 _wait_ly_15
|
||||
00:117c _print_results_halt_6
|
||||
00:117f _test_failure_cb_4
|
||||
00:1187 _print_sl_data60
|
||||
00:1198 _print_sl_out60
|
||||
00:119b fail_round3_cancel
|
||||
00:11b2 _wait_ly_16
|
||||
00:11b8 _wait_ly_17
|
||||
00:11ce _print_results_halt_7
|
||||
00:11d1 _test_failure_cb_5
|
||||
00:11d9 _print_sl_data61
|
||||
00:11ed _print_sl_out61
|
||||
00:11f0 fail_round3_if
|
||||
00:1207 _wait_ly_18
|
||||
00:120d _wait_ly_19
|
||||
00:1223 _print_results_halt_8
|
||||
00:1226 _test_failure_cb_6
|
||||
00:122e _print_sl_data62
|
||||
00:123e _print_sl_out62
|
||||
00:1241 fail_round4_nointr
|
||||
00:1258 _wait_ly_20
|
||||
00:125e _wait_ly_21
|
||||
00:1274 _print_results_halt_9
|
||||
00:1277 _test_failure_cb_7
|
||||
00:127f _print_sl_data63
|
||||
00:1290 _print_sl_out63
|
||||
00:1293 fail_round4_cancel
|
||||
00:12aa _wait_ly_22
|
||||
00:12b0 _wait_ly_23
|
||||
00:12c6 _print_results_halt_10
|
||||
00:12c9 _test_failure_cb_8
|
||||
00:12d1 _print_sl_data64
|
||||
00:12e5 _print_sl_out64
|
||||
00:12e8 fail_round4_if
|
||||
00:12ff _wait_ly_24
|
||||
00:1305 _wait_ly_25
|
||||
00:131b _print_results_halt_11
|
||||
00:131e _test_failure_cb_9
|
||||
00:1326 _print_sl_data65
|
||||
00:1333 _print_sl_out65
|
||||
00:1336 fail_round4_vblank
|
||||
00:134d _wait_ly_26
|
||||
00:1353 _wait_ly_27
|
||||
00:1369 _print_results_halt_12
|
||||
00:136c _test_failure_cb_10
|
||||
00:1374 _print_sl_data66
|
||||
00:1383 _print_sl_out66
|
||||
Loading…
Reference in New Issue