mirror of https://github.com/mgba-emu/mgba.git
DS GX: Stub out GX
This commit is contained in:
Vicki Pfau
parent
d41b904485
commit
a7f1567286
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@ -14,6 +14,7 @@ CXX_GUARD_START
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#include <mgba/core/timing.h>
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#include <mgba-util/circle-buffer.h>
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#include <mgba/internal/ds/gx.h>
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#include <mgba/internal/ds/memory.h>
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#include <mgba/internal/ds/timer.h>
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#include <mgba/internal/ds/video.h>
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@ -78,6 +79,7 @@ struct DS {
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struct DSCommon ds9;
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struct DSMemory memory;
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struct DSVideo video;
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struct DSGX gx;
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struct mCoreSync* sync;
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struct mTimingEvent slice;
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@ -0,0 +1,87 @@
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/* Copyright (c) 2013-2017 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef DS_GX_H
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#define DS_GX_H
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#include <mgba-util/common.h>
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CXX_GUARD_START
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#include <mgba/core/log.h>
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#include <mgba/core/timing.h>
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#include <mgba-util/circle-buffer.h>
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mLOG_DECLARE_CATEGORY(DS_GX);
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enum DSGXCommand {
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DS_GX_CMD_NOP = 0,
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DS_GX_CMD_MTX_MODE = 0x10,
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DS_GX_CMD_MTX_PUSH = 0x11,
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DS_GX_CMD_MTX_POP = 0x12,
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DS_GX_CMD_MTX_STORE = 0x13,
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DS_GX_CMD_MTX_RESTORE = 0x14,
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DS_GX_CMD_MTX_IDENTITY = 0x15,
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DS_GX_CMD_MTX_LOAD_4x4 = 0x16,
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DS_GX_CMD_MTX_LOAD_4x3 = 0x17,
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DS_GX_CMD_MTX_MULT_4x4 = 0x18,
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DS_GX_CMD_MTX_MULT_4x3 = 0x19,
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DS_GX_CMD_MTX_MULT_3x3 = 0x1A,
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DS_GX_CMD_MTX_SCALE = 0x1B,
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DS_GX_CMD_MTX_TRANS = 0x1C,
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DS_GX_CMD_COLOR = 0x20,
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DS_GX_CMD_NORMAL = 0x21,
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DS_GX_CMD_TEXCOORD = 0x22,
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DS_GX_CMD_VTX_16 = 0x23,
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DS_GX_CMD_VTX_10 = 0x24,
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DS_GX_CMD_VTX_XY = 0x25,
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DS_GX_CMD_VTX_XZ = 0x26,
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DS_GX_CMD_VTX_YZ = 0x27,
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DS_GX_CMD_VTX_DIFF = 0x28,
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DS_GX_CMD_POLYGON_ATTR = 0x29,
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DS_GX_CMD_TEXIMAGE_PARAM = 0x2A,
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DS_GX_CMD_PLTT_BASE = 0x2B,
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DS_GX_CMD_DIF_AMB = 0x30,
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DS_GX_CMD_SPE_EMI = 0x31,
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DS_GX_CMD_LIGHT_VECTOR = 0x32,
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DS_GX_CMD_LIGHT_COLOR = 0x33,
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DS_GX_CMD_SHININESS = 0x34,
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DS_GX_CMD_BEGIN_VTXS = 0x40,
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DS_GX_CMD_END_VTXS = 0x41,
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DS_GX_CMD_SWAP_BUFFERS = 0x50,
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DS_GX_CMD_VIEWPORT = 0x60,
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DS_GX_CMD_BOX_TEST = 0x70,
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DS_GX_CMD_POS_TEST = 0x71,
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DS_GX_CMD_VEC_TEST = 0x72,
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DS_GX_CMD_MAX
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};
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#pragma pack(push, 1)
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struct DSGXEntry {
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uint8_t command;
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uint8_t params[4];
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};
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#pragma pack(pop)
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struct DS;
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struct DSGX {
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struct DS* p;
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struct DSGXEntry pipe[4];
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struct CircleBuffer fifo;
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struct mTimingEvent fifoEvent;
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};
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void DSGXInit(struct DSGX*);
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void DSGXDeinit(struct DSGX*);
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void DSGXReset(struct DSGX*);
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uint16_t DSGXWriteRegister(struct DSGX*, uint32_t address, uint16_t value);
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uint32_t DSGXWriteRegister32(struct DSGX*, uint32_t address, uint32_t value);
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CXX_GUARD_END
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#endif
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@ -166,7 +166,6 @@ enum DS9IORegisters {
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DS9_REG_A_BLDCNT = 0x050,
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DS9_REG_A_BLDALPHA = 0x052,
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DS9_REG_A_BLDY = 0x054,
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DS9_REG_DISP3DCNT = 0x060,
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DS9_REG_DISPCAPCNT_LO = 0x064,
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DS9_REG_DISPCAPCNT_HI = 0x066,
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DS9_REG_DISP_MMEM_FIFO_LO = 0x068,
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@ -256,6 +255,173 @@ enum DS9IORegisters {
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DS9_REG_SQRT_PARAM_2 = 0x2BC,
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DS9_REG_SQRT_PARAM_3 = 0x2BE,
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// GX
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DS9_REG_DISP3DCNT = 0x060,
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DS9_REG_RDLINES_COUNT = 0x320,
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DS9_REG_EDGE_COLOR_0 = 0x330,
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DS9_REG_EDGE_COLOR_1 = 0x332,
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DS9_REG_EDGE_COLOR_2 = 0x334,
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DS9_REG_EDGE_COLOR_3 = 0x336,
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DS9_REG_EDGE_COLOR_4 = 0x338,
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DS9_REG_EDGE_COLOR_5 = 0x33A,
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DS9_REG_EDGE_COLOR_6 = 0x33C,
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DS9_REG_EDGE_COLOR_7 = 0x33E,
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DS9_REG_ALPHA_TEST_REF = 0x340,
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DS9_REG_CLEAR_COLOR_LO = 0x350,
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DS9_REG_CLEAR_COLOR_HI = 0x352,
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DS9_REG_CLEAR_DEPTH = 0x354,
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DS9_REG_CLRIMAGE_OFFSET = 0x356,
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DS9_REG_FOG_COLOR_LO = 0x358,
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DS9_REG_FOG_COLOR_HI = 0x35A,
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DS9_REG_FOG_OFFSET = 0x35C,
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DS9_REG_FOG_TABLE_0 = 0x360,
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DS9_REG_FOG_TABLE_1 = 0x362,
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DS9_REG_FOG_TABLE_2 = 0x364,
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DS9_REG_FOG_TABLE_3 = 0x366,
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DS9_REG_FOG_TABLE_4 = 0x368,
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DS9_REG_FOG_TABLE_5 = 0x36A,
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DS9_REG_FOG_TABLE_6 = 0x36C,
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DS9_REG_FOG_TABLE_7 = 0x36E,
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DS9_REG_FOG_TABLE_8 = 0x370,
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DS9_REG_FOG_TABLE_9 = 0x372,
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DS9_REG_FOG_TABLE_A = 0x374,
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DS9_REG_FOG_TABLE_B = 0x376,
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DS9_REG_FOG_TABLE_C = 0x378,
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DS9_REG_FOG_TABLE_D = 0x37A,
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DS9_REG_FOG_TABLE_E = 0x37C,
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DS9_REG_FOG_TABLE_F = 0x37E,
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DS9_REG_TOON_TABLE_00 = 0x380,
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DS9_REG_TOON_TABLE_01 = 0x382,
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DS9_REG_TOON_TABLE_02 = 0x384,
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DS9_REG_TOON_TABLE_03 = 0x386,
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DS9_REG_TOON_TABLE_04 = 0x388,
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DS9_REG_TOON_TABLE_05 = 0x38A,
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DS9_REG_TOON_TABLE_06 = 0x38C,
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DS9_REG_TOON_TABLE_07 = 0x38E,
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DS9_REG_TOON_TABLE_08 = 0x390,
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DS9_REG_TOON_TABLE_09 = 0x392,
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DS9_REG_TOON_TABLE_0A = 0x394,
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DS9_REG_TOON_TABLE_0B = 0x396,
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DS9_REG_TOON_TABLE_0C = 0x398,
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DS9_REG_TOON_TABLE_0D = 0x39A,
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DS9_REG_TOON_TABLE_0E = 0x39C,
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DS9_REG_TOON_TABLE_0F = 0x39E,
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DS9_REG_TOON_TABLE_10 = 0x3A0,
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DS9_REG_TOON_TABLE_11 = 0x3A2,
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DS9_REG_TOON_TABLE_12 = 0x3A4,
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DS9_REG_TOON_TABLE_13 = 0x3A6,
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DS9_REG_TOON_TABLE_14 = 0x3A8,
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DS9_REG_TOON_TABLE_15 = 0x3AA,
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DS9_REG_TOON_TABLE_16 = 0x3AC,
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DS9_REG_TOON_TABLE_17 = 0x3AE,
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DS9_REG_TOON_TABLE_18 = 0x3B0,
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DS9_REG_TOON_TABLE_19 = 0x3B2,
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DS9_REG_TOON_TABLE_1A = 0x3B4,
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DS9_REG_TOON_TABLE_1B = 0x3B6,
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DS9_REG_TOON_TABLE_1C = 0x3B8,
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DS9_REG_TOON_TABLE_1D = 0x3BA,
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DS9_REG_TOON_TABLE_1E = 0x3BC,
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DS9_REG_TOON_TABLE_1F = 0x3BE,
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DS9_REG_GXFIFO_00 = 0x400,
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DS9_REG_GXFIFO_01 = 0x402,
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DS9_REG_GXFIFO_02 = 0x404,
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DS9_REG_GXFIFO_03 = 0x406,
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DS9_REG_GXFIFO_04 = 0x408,
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DS9_REG_GXFIFO_05 = 0x40A,
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DS9_REG_GXFIFO_06 = 0x40C,
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DS9_REG_GXFIFO_07 = 0x40E,
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DS9_REG_GXFIFO_08 = 0x410,
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DS9_REG_GXFIFO_09 = 0x412,
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DS9_REG_GXFIFO_0A = 0x414,
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DS9_REG_GXFIFO_0B = 0x416,
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DS9_REG_GXFIFO_0C = 0x418,
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DS9_REG_GXFIFO_0D = 0x41A,
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DS9_REG_GXFIFO_0E = 0x41C,
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DS9_REG_GXFIFO_0F = 0x41E,
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DS9_REG_GXFIFO_10 = 0x420,
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DS9_REG_GXFIFO_11 = 0x422,
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DS9_REG_GXFIFO_12 = 0x424,
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DS9_REG_GXFIFO_13 = 0x426,
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DS9_REG_GXFIFO_14 = 0x428,
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DS9_REG_GXFIFO_15 = 0x42A,
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DS9_REG_GXFIFO_16 = 0x42C,
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DS9_REG_GXFIFO_17 = 0x42E,
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DS9_REG_GXFIFO_18 = 0x430,
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DS9_REG_GXFIFO_19 = 0x432,
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DS9_REG_GXFIFO_1A = 0x434,
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DS9_REG_GXFIFO_1B = 0x436,
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DS9_REG_GXFIFO_1C = 0x438,
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DS9_REG_GXFIFO_1D = 0x43A,
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DS9_REG_GXFIFO_1E = 0x43C,
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DS9_REG_GXFIFO_1F = 0x43E,
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DS9_REG_GXSTAT_LO = 0x600,
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DS9_REG_GXSTAT_HI = 0x602,
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DS9_REG_RAM_COUNT_LO = 0x604,
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DS9_REG_RAM_COUNT_HI = 0x606,
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DS9_REG_DISP_1DOT_DEPTH = 0x610,
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DS9_REG_POS_RESULT_0 = 0x620,
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DS9_REG_POS_RESULT_1 = 0x622,
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DS9_REG_POS_RESULT_2 = 0x624,
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DS9_REG_POS_RESULT_3 = 0x626,
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DS9_REG_POS_RESULT_4 = 0x628,
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DS9_REG_POS_RESULT_5 = 0x62A,
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DS9_REG_POS_RESULT_6 = 0x62C,
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DS9_REG_POS_RESULT_7 = 0x62E,
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DS9_REG_VEC_RESULT_0 = 0x630,
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DS9_REG_VEC_RESULT_1 = 0x632,
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DS9_REG_VEC_RESULT_2 = 0x634,
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DS9_REG_CLIPMTX_RESULT_00 = 0x640,
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DS9_REG_CLIPMTX_RESULT_01 = 0x642,
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DS9_REG_CLIPMTX_RESULT_02 = 0x644,
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DS9_REG_CLIPMTX_RESULT_03 = 0x646,
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DS9_REG_CLIPMTX_RESULT_04 = 0x648,
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DS9_REG_CLIPMTX_RESULT_05 = 0x64A,
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DS9_REG_CLIPMTX_RESULT_06 = 0x64C,
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DS9_REG_CLIPMTX_RESULT_07 = 0x64E,
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DS9_REG_CLIPMTX_RESULT_08 = 0x650,
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DS9_REG_CLIPMTX_RESULT_09 = 0x652,
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DS9_REG_CLIPMTX_RESULT_0A = 0x654,
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DS9_REG_CLIPMTX_RESULT_0B = 0x656,
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DS9_REG_CLIPMTX_RESULT_0C = 0x658,
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DS9_REG_CLIPMTX_RESULT_0D = 0x65A,
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DS9_REG_CLIPMTX_RESULT_0E = 0x65C,
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DS9_REG_CLIPMTX_RESULT_0F = 0x65E,
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DS9_REG_CLIPMTX_RESULT_10 = 0x660,
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DS9_REG_CLIPMTX_RESULT_11 = 0x662,
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DS9_REG_CLIPMTX_RESULT_12 = 0x664,
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DS9_REG_CLIPMTX_RESULT_13 = 0x666,
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DS9_REG_CLIPMTX_RESULT_14 = 0x668,
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DS9_REG_CLIPMTX_RESULT_15 = 0x66A,
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DS9_REG_CLIPMTX_RESULT_16 = 0x66C,
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DS9_REG_CLIPMTX_RESULT_17 = 0x66E,
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DS9_REG_CLIPMTX_RESULT_18 = 0x670,
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DS9_REG_CLIPMTX_RESULT_19 = 0x672,
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DS9_REG_CLIPMTX_RESULT_1A = 0x674,
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DS9_REG_CLIPMTX_RESULT_1B = 0x676,
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DS9_REG_CLIPMTX_RESULT_1C = 0x678,
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DS9_REG_CLIPMTX_RESULT_1D = 0x67A,
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DS9_REG_CLIPMTX_RESULT_1E = 0x67C,
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DS9_REG_CLIPMTX_RESULT_1F = 0x67E,
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DS9_REG_VECMTX_RESULT_00 = 0x680,
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DS9_REG_VECMTX_RESULT_01 = 0x682,
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DS9_REG_VECMTX_RESULT_02 = 0x684,
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DS9_REG_VECMTX_RESULT_03 = 0x686,
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DS9_REG_VECMTX_RESULT_04 = 0x688,
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DS9_REG_VECMTX_RESULT_05 = 0x68A,
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DS9_REG_VECMTX_RESULT_06 = 0x68C,
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DS9_REG_VECMTX_RESULT_07 = 0x68E,
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DS9_REG_VECMTX_RESULT_08 = 0x690,
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DS9_REG_VECMTX_RESULT_09 = 0x692,
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DS9_REG_VECMTX_RESULT_0A = 0x694,
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DS9_REG_VECMTX_RESULT_0B = 0x696,
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DS9_REG_VECMTX_RESULT_0C = 0x698,
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DS9_REG_VECMTX_RESULT_0D = 0x69A,
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DS9_REG_VECMTX_RESULT_0E = 0x69C,
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DS9_REG_VECMTX_RESULT_0F = 0x69E,
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DS9_REG_VECMTX_RESULT_10 = 0x6A0,
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DS9_REG_VECMTX_RESULT_11 = 0x6A2,
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DS9_REG_VECMTX_RESULT_12 = 0x6A4,
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DS9_REG_MAX = 0x106E,
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DS9_REG_POWCNT1 = 0x304,
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@ -196,6 +196,9 @@ static void DSInit(void* cpu, struct mCPUComponent* component) {
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DSVideoInit(&ds->video);
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ds->video.p = ds;
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DSGXInit(&ds->gx);
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ds->gx.p = ds;
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ds->ds7.springIRQ = 0;
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ds->ds9.springIRQ = 0;
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DSTimerInit(ds);
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@ -234,6 +237,7 @@ void DSDestroy(struct DS* ds) {
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CircleBufferDeinit(&ds->ds9.fifo);
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DSUnloadROM(ds);
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DSMemoryDeinit(ds);
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DSGXDeinit(&ds->gx);
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mTimingDeinit(&ds->ds7.timing);
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mTimingDeinit(&ds->ds9.timing);
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}
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@ -318,6 +322,7 @@ void DS9Reset(struct ARMCore* cpu) {
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mTimingClear(&ds->ds9.timing);
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CircleBufferInit(&ds->ds9.fifo, 64);
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DSVideoReset(&ds->video);
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DSGXReset(&ds->gx);
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DSDMAReset(&ds->ds9);
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DS9IOInit(ds);
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@ -0,0 +1,104 @@
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/* Copyright (c) 2013-2017 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include <mgba/internal/ds/gx.h>
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#include <mgba/internal/ds/io.h>
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mLOG_DEFINE_CATEGORY(DS_GX, "DS GX");
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#define DS_GX_FIFO_SIZE 256
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static const int32_t _gxCommandCycleBase[DS_GX_CMD_MAX] = {
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[DS_GX_CMD_NOP] = 0,
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[DS_GX_CMD_MTX_MODE] = 2,
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[DS_GX_CMD_MTX_PUSH] = 34,
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[DS_GX_CMD_MTX_POP] = 72,
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[DS_GX_CMD_MTX_STORE] = 34,
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[DS_GX_CMD_MTX_RESTORE] = 72,
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[DS_GX_CMD_MTX_IDENTITY] = 38,
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[DS_GX_CMD_MTX_LOAD_4x4] = 68,
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[DS_GX_CMD_MTX_LOAD_4x3] = 60,
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[DS_GX_CMD_MTX_MULT_4x4] = 70,
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[DS_GX_CMD_MTX_MULT_4x3] = 62,
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[DS_GX_CMD_MTX_MULT_3x3] = 56,
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[DS_GX_CMD_MTX_SCALE] = 44,
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[DS_GX_CMD_MTX_TRANS] = 44,
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[DS_GX_CMD_COLOR] = 2,
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[DS_GX_CMD_NORMAL] = 18,
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[DS_GX_CMD_TEXCOORD] = 2,
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[DS_GX_CMD_VTX_16] = 18,
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[DS_GX_CMD_VTX_10] = 16,
|
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[DS_GX_CMD_VTX_XY] = 16,
|
||||
[DS_GX_CMD_VTX_XZ] = 16,
|
||||
[DS_GX_CMD_VTX_YZ] = 16,
|
||||
[DS_GX_CMD_VTX_DIFF] = 16,
|
||||
[DS_GX_CMD_POLYGON_ATTR] = 2,
|
||||
[DS_GX_CMD_TEXIMAGE_PARAM] = 2,
|
||||
[DS_GX_CMD_PLTT_BASE] = 2,
|
||||
[DS_GX_CMD_DIF_AMB] = 8,
|
||||
[DS_GX_CMD_SPE_EMI] = 8,
|
||||
[DS_GX_CMD_LIGHT_VECTOR] = 12,
|
||||
[DS_GX_CMD_LIGHT_COLOR] = 2,
|
||||
[DS_GX_CMD_SHININESS] = 64,
|
||||
[DS_GX_CMD_BEGIN_VTXS] = 2,
|
||||
[DS_GX_CMD_END_VTXS] = 2,
|
||||
[DS_GX_CMD_SWAP_BUFFERS] = 784,
|
||||
[DS_GX_CMD_VIEWPORT] = 2,
|
||||
[DS_GX_CMD_BOX_TEST] = 206,
|
||||
[DS_GX_CMD_POS_TEST] = 18,
|
||||
[DS_GX_CMD_VEC_TEST] = 10,
|
||||
};
|
||||
|
||||
void DSGXInit(struct DSGX* gx) {
|
||||
CircleBufferInit(&gx->fifo, sizeof(struct DSGXEntry) * DS_GX_FIFO_SIZE);
|
||||
}
|
||||
|
||||
void DSGXDeinit(struct DSGX* gx) {
|
||||
CircleBufferDeinit(&gx->fifo);
|
||||
}
|
||||
|
||||
void DSGXReset(struct DSGX* gx) {
|
||||
CircleBufferClear(&gx->fifo);
|
||||
}
|
||||
|
||||
uint16_t DSGXWriteRegister(struct DSGX* gx, uint32_t address, uint16_t value) {
|
||||
switch (address) {
|
||||
case DS9_REG_DISP3DCNT:
|
||||
case DS9_REG_GXSTAT_LO:
|
||||
case DS9_REG_GXSTAT_HI:
|
||||
mLOG(DS_GX, STUB, "Unimplemented GX write %03X:%04X", address, value);
|
||||
break;
|
||||
default:
|
||||
if (address < DS9_REG_GXFIFO_00) {
|
||||
mLOG(DS_GX, STUB, "Unimplemented GX write %03X:%04X", address, value);
|
||||
} else if (address < DS9_REG_GXSTAT_LO) {
|
||||
mLOG(DS_GX, STUB, "Unimplemented FIFO write %03X:%04X", address, value);
|
||||
} else {
|
||||
mLOG(DS_GX, STUB, "Unimplemented GX write %03X:%04X", address, value);
|
||||
}
|
||||
break;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
uint32_t DSGXWriteRegister32(struct DSGX* gx, uint32_t address, uint32_t value) {
|
||||
switch (address) {
|
||||
case DS9_REG_DISP3DCNT:
|
||||
case DS9_REG_GXSTAT_LO:
|
||||
mLOG(DS_GX, STUB, "Unimplemented GX write %03X:%04X", address, value);
|
||||
break;
|
||||
default:
|
||||
if (address < DS9_REG_GXFIFO_00) {
|
||||
mLOG(DS_GX, STUB, "Unimplemented GX write %03X:%04X", address, value);
|
||||
} else if (address < DS9_REG_GXSTAT_LO) {
|
||||
mLOG(DS_GX, STUB, "Unimplemented FIFO write %03X:%04X", address, value);
|
||||
} else {
|
||||
mLOG(DS_GX, STUB, "Unimplemented GX write %03X:%04X", address, value);
|
||||
}
|
||||
break;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
68
src/ds/io.c
68
src/ds/io.c
|
|
@ -7,6 +7,7 @@
|
|||
|
||||
#include <mgba/core/interface.h>
|
||||
#include <mgba/internal/ds/ds.h>
|
||||
#include <mgba/internal/ds/gx.h>
|
||||
#include <mgba/internal/ds/ipc.h>
|
||||
#include <mgba/internal/ds/slot1.h>
|
||||
#include <mgba/internal/ds/spi.h>
|
||||
|
|
@ -415,6 +416,7 @@ void DS9IOInit(struct DS* ds) {
|
|||
memset(ds->memory.io9, 0, sizeof(ds->memory.io9));
|
||||
ds->memory.io9[DS_REG_IPCFIFOCNT >> 1] = 0x0101;
|
||||
ds->memory.io9[DS_REG_POSTFLG >> 1] = 0x0001;
|
||||
ds->memory.io9[DS9_REG_GXSTAT_HI >> 1] = 0x0600;
|
||||
DS9IOWrite(ds, DS9_REG_VRAMCNT_G, 0x0300);
|
||||
}
|
||||
|
||||
|
|
@ -423,6 +425,8 @@ void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value) {
|
|||
value = ds->video.renderer->writeVideoRegister(ds->video.renderer, address, value);
|
||||
} else if (address >= DS9_REG_B_DISPCNT_LO && address <= DS9_REG_B_BLDY) {
|
||||
value = ds->video.renderer->writeVideoRegister(ds->video.renderer, address, value);
|
||||
} else if ((address >= DS9_REG_RDLINES_COUNT && address <= DS9_REG_VECMTX_RESULT_12) || address == DS9_REG_DISP3DCNT) {
|
||||
value = DSGXWriteRegister(&ds->gx, address, value);
|
||||
} else {
|
||||
uint16_t oldValue;
|
||||
switch (address) {
|
||||
|
|
@ -514,37 +518,41 @@ void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value) {
|
|||
}
|
||||
|
||||
void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value) {
|
||||
switch (address) {
|
||||
case DS_REG_DMA0SAD_LO:
|
||||
case DS_REG_DMA1SAD_LO:
|
||||
case DS_REG_DMA2SAD_LO:
|
||||
case DS_REG_DMA3SAD_LO:
|
||||
case DS_REG_DMA0DAD_LO:
|
||||
case DS_REG_DMA1DAD_LO:
|
||||
case DS_REG_DMA2DAD_LO:
|
||||
case DS_REG_DMA3DAD_LO:
|
||||
case DS_REG_IPCFIFOSEND_LO:
|
||||
case DS_REG_IE_LO:
|
||||
value = DSIOWrite32(&ds->ds9, address, value);
|
||||
break;
|
||||
if ((address >= DS9_REG_RDLINES_COUNT && address <= DS9_REG_VECMTX_RESULT_12) || address == DS9_REG_DISP3DCNT) {
|
||||
value = DSGXWriteRegister32(&ds->gx, address, value);
|
||||
} else {
|
||||
switch (address) {
|
||||
case DS_REG_DMA0SAD_LO:
|
||||
case DS_REG_DMA1SAD_LO:
|
||||
case DS_REG_DMA2SAD_LO:
|
||||
case DS_REG_DMA3SAD_LO:
|
||||
case DS_REG_DMA0DAD_LO:
|
||||
case DS_REG_DMA1DAD_LO:
|
||||
case DS_REG_DMA2DAD_LO:
|
||||
case DS_REG_DMA3DAD_LO:
|
||||
case DS_REG_IPCFIFOSEND_LO:
|
||||
case DS_REG_IE_LO:
|
||||
value = DSIOWrite32(&ds->ds9, address, value);
|
||||
break;
|
||||
|
||||
case DS_REG_DMA0CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 3, value);
|
||||
break;
|
||||
case DS_REG_DMA0CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 0, value);
|
||||
break;
|
||||
case DS_REG_DMA1CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 1, value);
|
||||
break;
|
||||
case DS_REG_DMA2CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 2, value);
|
||||
break;
|
||||
case DS_REG_DMA3CNT_LO:
|
||||
DS9DMAWriteCNT(&ds->ds9, 3, value);
|
||||
break;
|
||||
|
||||
default:
|
||||
DS9IOWrite(ds, address, value & 0xFFFF);
|
||||
DS9IOWrite(ds, address | 2, value >> 16);
|
||||
return;
|
||||
default:
|
||||
DS9IOWrite(ds, address, value & 0xFFFF);
|
||||
DS9IOWrite(ds, address | 2, value >> 16);
|
||||
return;
|
||||
}
|
||||
}
|
||||
ds->ds9.memory.io[address >> 1] = value;
|
||||
ds->ds9.memory.io[(address >> 1) + 1] = value >> 16;
|
||||
|
|
@ -608,6 +616,8 @@ uint16_t DS9IORead(struct DS* ds, uint32_t address) {
|
|||
case DS9_REG_SQRT_RESULT_LO:
|
||||
case DS9_REG_SQRT_RESULT_HI:
|
||||
case DS_REG_POSTFLG:
|
||||
case DS9_REG_GXSTAT_LO:
|
||||
case DS9_REG_GXSTAT_HI:
|
||||
// Handled transparently by the registers
|
||||
break;
|
||||
case DS_REG_AUXSPICNT:
|
||||
|
|
|
|||
Loading…
Reference in New Issue