From 7b82cc0040a524acbeb11ab49684f56f5b414021 Mon Sep 17 00:00:00 2001
From: Jeffrey Pfau <jeffrey@endrift.com>
Date: Sat, 6 Apr 2013 13:05:53 -0700
Subject: [PATCH] Fill in LDR/STR block

---
 src/arm.c | 126 +++++++++++++++++++++++++++++++++---------------------
 1 file changed, 77 insertions(+), 49 deletions(-)

diff --git a/src/arm.c b/src/arm.c
index 3e981f0f3..04cf34419 100644
--- a/src/arm.c
+++ b/src/arm.c
@@ -222,14 +222,20 @@ inline void ARMCycle(struct ARMCore* cpu) {
 		BODY; \
 		WRITEBACK;)
 
-// TODO: shifters
+#define DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME, SHIFTER, BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, SHIFTER(ADDR_MODE_2_RN), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), , BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, SHIFTER(ADDR_MODE_2_RM)), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY)
+
+
 #define DEFINE_LOAD_STORE_INSTRUCTION_ARM(NAME, BODY) \
-	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM)), BODY) \
-	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## U, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM)), BODY) \
-	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## P, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM), , BODY) \
-	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PW, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_RM), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
-	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PU, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM), , BODY) \
-	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## PUW, ADDR_MODE_2_INDEX(+, ADDR_MODE_2_RM), ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_ADDRESS), BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSL_, ADDR_MODE_2_LSL, BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _LSR_, ADDR_MODE_2_LSR, BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ASR_, ADDR_MODE_2_ASR, BODY) \
+	DEFINE_LOAD_STORE_INSTRUCTION_SHIFTER_ARM(NAME ## _ROR_, ADDR_MODE_2_ROR, BODY) \
 	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## I, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE)), BODY) \
 	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IU, ADDR_MODE_2_RN, ADDR_MODE_2_WRITEBACK(ADDR_MODE_2_INDEX(+, ADDR_MODE_2_IMMEDIATE)), BODY) \
 	DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME ## IP, ADDR_MODE_2_INDEX(-, ADDR_MODE_2_IMMEDIATE), , BODY) \
@@ -327,12 +333,16 @@ DEFINE_INSTRUCTION_ARM(UMULLS,)
 
 DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address))
 DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address))
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRBT,)
 DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address))
 DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address))
 DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address))
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRT,)
 DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd]))
 DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd]))
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRBT,)
 DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd]))
+DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRT,)
 
 DEFINE_INSTRUCTION_ARM(SWP,)
 DEFINE_INSTRUCTION_ARM(SWPB,)
@@ -375,9 +385,27 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
 	DECLARE_INSTRUCTION_ARM(COND, EX4)
 
 #define DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, NAME, P, U, W) \
-	DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)) \
+	DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W)), \
 	DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME ## I ## P ## U ## W))
 
+#define DECLARE_ARM_LOAD_STORE_BLOCK(COND, NAME, P, U, W) \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSL_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSR_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _ASR_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSL_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _LSR_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _ASR_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL), \
+	DECLARE_INSTRUCTION_ARM(COND, NAME ## _ROR_ ## P ## U ## W), \
+	DECLARE_INSTRUCTION_ARM(COND, ILL)
+
 #define LDRHW ILL
 #define LDRSBW ILL
 #define LDRSHW ILL
@@ -459,23 +487,23 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
 	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BIC), \
 	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, BICS), \
 	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVN), \
-	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS)//, \
+	DECLARE_ARM_ALU_IMMEDIATE_BLOCK(COND, MVNS), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , ), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , , W), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , , W), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRT, , , ), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRT, , , ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , ), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , , W), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , , W), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRBT, , , ), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRBT, , , ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, ), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, , U, W), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, , U, W), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRT, , U, ), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRT, , U, ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, ), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, , U, W), \
-	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, , U, W), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRBT, , U, ), \
+	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRBT, , U, ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDR, P, , ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STR, P, , W), \
@@ -492,38 +520,38 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, ), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, STRB, P, U, W), \
 	DECLARE_ARM_LOAD_STORE_IMMEDIATE_BLOCK(COND, LDRB, P, U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
-	// DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRT, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRT, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRBT, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRBT, , , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRT, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRT, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRBT, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRBT, , U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, , W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, , W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, , W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, , W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STR, P, U, W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDR, P, U, W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, ), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, STRB, P, U, W), \
+	DECLARE_ARM_LOAD_STORE_BLOCK(COND, LDRB, P, U, W)//, \
 	// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , ), \
 	// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, LDM, , , ), \
 	// DECLARE_ARM_LOAD_STORE_MULTIPLE_BLOCK(COND, STM, , , W), \