mirror of https://github.com/mgba-emu/mgba.git
Merge branch 'master' into port/wii
This commit is contained in:
commit
72b34f7941
1
CHANGES
1
CHANGES
|
@ -10,6 +10,7 @@ Misc:
|
||||||
- Qt: Increase usability of key mapper
|
- Qt: Increase usability of key mapper
|
||||||
- GBA Memory: Use a dynamically sized mask for ROM memory
|
- GBA Memory: Use a dynamically sized mask for ROM memory
|
||||||
- Qt: Remove useless help icons in dialogs
|
- Qt: Remove useless help icons in dialogs
|
||||||
|
- ARM7: Combine shifter-immediate and shifter-register functions to reduce binary size
|
||||||
|
|
||||||
0.3.0: (2015-08-16)
|
0.3.0: (2015-08-16)
|
||||||
Features:
|
Features:
|
||||||
|
|
|
@ -11,18 +11,16 @@
|
||||||
|
|
||||||
#define ADDR_MODE_1_SHIFT(OP) \
|
#define ADDR_MODE_1_SHIFT(OP) \
|
||||||
info->op3.reg = opcode & 0x0000000F; \
|
info->op3.reg = opcode & 0x0000000F; \
|
||||||
info->op3.shifterOp = ARM_SHIFT_ ## OP; \
|
info->operandFormat |= ARM_OPERAND_REGISTER_3; \
|
||||||
info->op3.shifterImm = (opcode >> 7) & 0x1F; \
|
if (opcode & 0x00000010) { \
|
||||||
info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
|
info->op3.shifterOp = ARM_SHIFT_ ## OP; \
|
||||||
ARM_OPERAND_SHIFT_IMMEDIATE_3;
|
info->op3.shifterReg = (opcode >> 8) & 0xF; \
|
||||||
|
++info->iCycles; \
|
||||||
#define ADDR_MODE_1_SHIFTR(OP) \
|
info->operandFormat |= ARM_OPERAND_SHIFT_REGISTER_3; \
|
||||||
info->op3.reg = opcode & 0x0000000F; \
|
} else { \
|
||||||
info->op3.shifterOp = ARM_SHIFT_ ## OP; \
|
info->op3.shifterImm = (opcode >> 7) & 0x1F; \
|
||||||
info->op3.shifterReg = (opcode >> 8) & 0xF; \
|
info->operandFormat |= ARM_OPERAND_SHIFT_IMMEDIATE_3; \
|
||||||
++info->iCycles; \
|
}
|
||||||
info->operandFormat |= ARM_OPERAND_REGISTER_3 | \
|
|
||||||
ARM_OPERAND_SHIFT_REGISTER_3;
|
|
||||||
|
|
||||||
#define ADDR_MODE_1_LSL \
|
#define ADDR_MODE_1_LSL \
|
||||||
ADDR_MODE_1_SHIFT(LSL) \
|
ADDR_MODE_1_SHIFT(LSL) \
|
||||||
|
@ -39,11 +37,6 @@
|
||||||
info->op3.shifterOp = ARM_SHIFT_RRX; \
|
info->op3.shifterOp = ARM_SHIFT_RRX; \
|
||||||
}
|
}
|
||||||
|
|
||||||
#define ADDR_MODE_1_LSLR ADDR_MODE_1_SHIFTR(LSL)
|
|
||||||
#define ADDR_MODE_1_LSRR ADDR_MODE_1_SHIFTR(LSR)
|
|
||||||
#define ADDR_MODE_1_ASRR ADDR_MODE_1_SHIFTR(ASR)
|
|
||||||
#define ADDR_MODE_1_RORR ADDR_MODE_1_SHIFTR(ROR)
|
|
||||||
|
|
||||||
#define ADDR_MODE_1_IMM \
|
#define ADDR_MODE_1_IMM \
|
||||||
int rotate = (opcode & 0x00000F00) >> 7; \
|
int rotate = (opcode & 0x00000F00) >> 7; \
|
||||||
int immediate = opcode & 0x000000FF; \
|
int immediate = opcode & 0x000000FF; \
|
||||||
|
@ -121,32 +114,20 @@
|
||||||
#define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
|
#define DEFINE_ALU_DECODER_ARM(NAME, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 0, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 0, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 0, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 0, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 0, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 0, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 0, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 0, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## S_RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 0, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## SI, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_AFFECTED_1, SKIPPED)
|
||||||
|
|
||||||
#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
|
#define DEFINE_ALU_DECODER_S_ONLY_ARM(NAME) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSL, NAME, 1, ADDR_MODE_1_LSL, ARM_OPERAND_NONE, 1) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSLR, NAME, 1, ADDR_MODE_1_LSLR, ARM_OPERAND_NONE, 1) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSR, NAME, 1, ADDR_MODE_1_LSR, ARM_OPERAND_NONE, 1) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _LSRR, NAME, 1, ADDR_MODE_1_LSRR, ARM_OPERAND_NONE, 1) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASR, NAME, 1, ADDR_MODE_1_ASR, ARM_OPERAND_NONE, 1) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ASRR, NAME, 1, ADDR_MODE_1_ASRR, ARM_OPERAND_NONE, 1) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## _ROR, NAME, 1, ADDR_MODE_1_ROR, ARM_OPERAND_NONE, 1) \
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## _RORR, NAME, 1, ADDR_MODE_1_RORR, ARM_OPERAND_NONE, 1) \
|
|
||||||
DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
|
DEFINE_ALU_DECODER_EX_ARM(NAME ## I, NAME, 1, ADDR_MODE_1_IMM, ARM_OPERAND_NONE, 1)
|
||||||
|
|
||||||
#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
|
#define DEFINE_MULTIPLY_DECODER_EX_ARM(NAME, MNEMONIC, S, OTHER_AFFECTED) \
|
||||||
|
|
|
@ -17,13 +17,13 @@
|
||||||
|
|
||||||
#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
|
#define DECLARE_ARM_ALU_BLOCK(EMITTER, ALU, EX1, EX2, EX3, EX4) \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSLR), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
|
||||||
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSRR), \
|
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASRR), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ASR), \
|
||||||
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _ROR), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _RORR), \
|
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSL), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, EX1), \
|
||||||
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
|
DECLARE_INSTRUCTION_ARM(EMITTER, ALU ## _LSR), \
|
||||||
|
|
|
@ -16,160 +16,156 @@
|
||||||
// Addressing mode 1
|
// Addressing mode 1
|
||||||
static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
|
static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
|
||||||
int rm = opcode & 0x0000000F;
|
int rm = opcode & 0x0000000F;
|
||||||
int immediate = (opcode & 0x00000F80) >> 7;
|
if (opcode & 0x00000010) {
|
||||||
if (!immediate) {
|
int rs = (opcode >> 8) & 0x0000000F;
|
||||||
cpu->shifterOperand = cpu->gprs[rm];
|
++cpu->cycles;
|
||||||
cpu->shifterCarryOut = cpu->cpsr.c;
|
int shift = cpu->gprs[rs];
|
||||||
|
if (rs == ARM_PC) {
|
||||||
|
shift += 4;
|
||||||
|
}
|
||||||
|
shift &= 0xFF;
|
||||||
|
int32_t shiftVal = cpu->gprs[rm];
|
||||||
|
if (rm == ARM_PC) {
|
||||||
|
shiftVal += 4;
|
||||||
|
}
|
||||||
|
if (!shift) {
|
||||||
|
cpu->shifterOperand = shiftVal;
|
||||||
|
cpu->shifterCarryOut = cpu->cpsr.c;
|
||||||
|
} else if (shift < 32) {
|
||||||
|
cpu->shifterOperand = shiftVal << shift;
|
||||||
|
cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
|
||||||
|
} else if (shift == 32) {
|
||||||
|
cpu->shifterOperand = 0;
|
||||||
|
cpu->shifterCarryOut = shiftVal & 1;
|
||||||
|
} else {
|
||||||
|
cpu->shifterOperand = 0;
|
||||||
|
cpu->shifterCarryOut = 0;
|
||||||
|
}
|
||||||
} else {
|
} else {
|
||||||
cpu->shifterOperand = cpu->gprs[rm] << immediate;
|
int immediate = (opcode & 0x00000F80) >> 7;
|
||||||
cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
|
if (!immediate) {
|
||||||
}
|
cpu->shifterOperand = cpu->gprs[rm];
|
||||||
}
|
cpu->shifterCarryOut = cpu->cpsr.c;
|
||||||
|
} else {
|
||||||
static inline void _shiftLSLR(struct ARMCore* cpu, uint32_t opcode) {
|
cpu->shifterOperand = cpu->gprs[rm] << immediate;
|
||||||
int rm = opcode & 0x0000000F;
|
cpu->shifterCarryOut = (cpu->gprs[rm] >> (32 - immediate)) & 1;
|
||||||
int rs = (opcode >> 8) & 0x0000000F;
|
}
|
||||||
++cpu->cycles;
|
|
||||||
int shift = cpu->gprs[rs];
|
|
||||||
if (rs == ARM_PC) {
|
|
||||||
shift += 4;
|
|
||||||
}
|
|
||||||
shift &= 0xFF;
|
|
||||||
int32_t shiftVal = cpu->gprs[rm];
|
|
||||||
if (rm == ARM_PC) {
|
|
||||||
shiftVal += 4;
|
|
||||||
}
|
|
||||||
if (!shift) {
|
|
||||||
cpu->shifterOperand = shiftVal;
|
|
||||||
cpu->shifterCarryOut = cpu->cpsr.c;
|
|
||||||
} else if (shift < 32) {
|
|
||||||
cpu->shifterOperand = shiftVal << shift;
|
|
||||||
cpu->shifterCarryOut = (shiftVal >> (32 - shift)) & 1;
|
|
||||||
} else if (shift == 32) {
|
|
||||||
cpu->shifterOperand = 0;
|
|
||||||
cpu->shifterCarryOut = shiftVal & 1;
|
|
||||||
} else {
|
|
||||||
cpu->shifterOperand = 0;
|
|
||||||
cpu->shifterCarryOut = 0;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
|
static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
|
||||||
int rm = opcode & 0x0000000F;
|
int rm = opcode & 0x0000000F;
|
||||||
int immediate = (opcode & 0x00000F80) >> 7;
|
if (opcode & 0x00000010) {
|
||||||
if (immediate) {
|
int rs = (opcode >> 8) & 0x0000000F;
|
||||||
cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
|
++cpu->cycles;
|
||||||
cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
|
int shift = cpu->gprs[rs];
|
||||||
|
if (rs == ARM_PC) {
|
||||||
|
shift += 4;
|
||||||
|
}
|
||||||
|
shift &= 0xFF;
|
||||||
|
uint32_t shiftVal = cpu->gprs[rm];
|
||||||
|
if (rm == ARM_PC) {
|
||||||
|
shiftVal += 4;
|
||||||
|
}
|
||||||
|
if (!shift) {
|
||||||
|
cpu->shifterOperand = shiftVal;
|
||||||
|
cpu->shifterCarryOut = cpu->cpsr.c;
|
||||||
|
} else if (shift < 32) {
|
||||||
|
cpu->shifterOperand = shiftVal >> shift;
|
||||||
|
cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
|
||||||
|
} else if (shift == 32) {
|
||||||
|
cpu->shifterOperand = 0;
|
||||||
|
cpu->shifterCarryOut = shiftVal >> 31;
|
||||||
|
} else {
|
||||||
|
cpu->shifterOperand = 0;
|
||||||
|
cpu->shifterCarryOut = 0;
|
||||||
|
}
|
||||||
} else {
|
} else {
|
||||||
cpu->shifterOperand = 0;
|
int immediate = (opcode & 0x00000F80) >> 7;
|
||||||
cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
|
if (immediate) {
|
||||||
}
|
cpu->shifterOperand = ((uint32_t) cpu->gprs[rm]) >> immediate;
|
||||||
}
|
cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
|
||||||
|
} else {
|
||||||
static inline void _shiftLSRR(struct ARMCore* cpu, uint32_t opcode) {
|
cpu->shifterOperand = 0;
|
||||||
int rm = opcode & 0x0000000F;
|
cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
|
||||||
int rs = (opcode >> 8) & 0x0000000F;
|
}
|
||||||
++cpu->cycles;
|
|
||||||
int shift = cpu->gprs[rs];
|
|
||||||
if (rs == ARM_PC) {
|
|
||||||
shift += 4;
|
|
||||||
}
|
|
||||||
shift &= 0xFF;
|
|
||||||
uint32_t shiftVal = cpu->gprs[rm];
|
|
||||||
if (rm == ARM_PC) {
|
|
||||||
shiftVal += 4;
|
|
||||||
}
|
|
||||||
if (!shift) {
|
|
||||||
cpu->shifterOperand = shiftVal;
|
|
||||||
cpu->shifterCarryOut = cpu->cpsr.c;
|
|
||||||
} else if (shift < 32) {
|
|
||||||
cpu->shifterOperand = shiftVal >> shift;
|
|
||||||
cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
|
|
||||||
} else if (shift == 32) {
|
|
||||||
cpu->shifterOperand = 0;
|
|
||||||
cpu->shifterCarryOut = shiftVal >> 31;
|
|
||||||
} else {
|
|
||||||
cpu->shifterOperand = 0;
|
|
||||||
cpu->shifterCarryOut = 0;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
|
static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
|
||||||
int rm = opcode & 0x0000000F;
|
int rm = opcode & 0x0000000F;
|
||||||
int immediate = (opcode & 0x00000F80) >> 7;
|
if (opcode & 0x00000010) {
|
||||||
if (immediate) {
|
int rs = (opcode >> 8) & 0x0000000F;
|
||||||
cpu->shifterOperand = cpu->gprs[rm] >> immediate;
|
++cpu->cycles;
|
||||||
cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
|
int shift = cpu->gprs[rs];
|
||||||
|
if (rs == ARM_PC) {
|
||||||
|
shift += 4;
|
||||||
|
}
|
||||||
|
shift &= 0xFF;
|
||||||
|
int shiftVal = cpu->gprs[rm];
|
||||||
|
if (rm == ARM_PC) {
|
||||||
|
shiftVal += 4;
|
||||||
|
}
|
||||||
|
if (!shift) {
|
||||||
|
cpu->shifterOperand = shiftVal;
|
||||||
|
cpu->shifterCarryOut = cpu->cpsr.c;
|
||||||
|
} else if (shift < 32) {
|
||||||
|
cpu->shifterOperand = shiftVal >> shift;
|
||||||
|
cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
|
||||||
|
} else if (cpu->gprs[rm] >> 31) {
|
||||||
|
cpu->shifterOperand = 0xFFFFFFFF;
|
||||||
|
cpu->shifterCarryOut = 1;
|
||||||
|
} else {
|
||||||
|
cpu->shifterOperand = 0;
|
||||||
|
cpu->shifterCarryOut = 0;
|
||||||
|
}
|
||||||
} else {
|
} else {
|
||||||
cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
|
int immediate = (opcode & 0x00000F80) >> 7;
|
||||||
cpu->shifterOperand = cpu->shifterCarryOut;
|
if (immediate) {
|
||||||
}
|
cpu->shifterOperand = cpu->gprs[rm] >> immediate;
|
||||||
}
|
cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
|
||||||
|
} else {
|
||||||
static inline void _shiftASRR(struct ARMCore* cpu, uint32_t opcode) {
|
cpu->shifterCarryOut = ARM_SIGN(cpu->gprs[rm]);
|
||||||
int rm = opcode & 0x0000000F;
|
cpu->shifterOperand = cpu->shifterCarryOut;
|
||||||
int rs = (opcode >> 8) & 0x0000000F;
|
}
|
||||||
++cpu->cycles;
|
|
||||||
int shift = cpu->gprs[rs];
|
|
||||||
if (rs == ARM_PC) {
|
|
||||||
shift += 4;
|
|
||||||
}
|
|
||||||
shift &= 0xFF;
|
|
||||||
int shiftVal = cpu->gprs[rm];
|
|
||||||
if (rm == ARM_PC) {
|
|
||||||
shiftVal += 4;
|
|
||||||
}
|
|
||||||
if (!shift) {
|
|
||||||
cpu->shifterOperand = shiftVal;
|
|
||||||
cpu->shifterCarryOut = cpu->cpsr.c;
|
|
||||||
} else if (shift < 32) {
|
|
||||||
cpu->shifterOperand = shiftVal >> shift;
|
|
||||||
cpu->shifterCarryOut = (shiftVal >> (shift - 1)) & 1;
|
|
||||||
} else if (cpu->gprs[rm] >> 31) {
|
|
||||||
cpu->shifterOperand = 0xFFFFFFFF;
|
|
||||||
cpu->shifterCarryOut = 1;
|
|
||||||
} else {
|
|
||||||
cpu->shifterOperand = 0;
|
|
||||||
cpu->shifterCarryOut = 0;
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
|
static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
|
||||||
int rm = opcode & 0x0000000F;
|
int rm = opcode & 0x0000000F;
|
||||||
int immediate = (opcode & 0x00000F80) >> 7;
|
if (opcode & 0x00000010) {
|
||||||
if (immediate) {
|
int rs = (opcode >> 8) & 0x0000000F;
|
||||||
cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
|
++cpu->cycles;
|
||||||
cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
|
int shift = cpu->gprs[rs];
|
||||||
|
if (rs == ARM_PC) {
|
||||||
|
shift += 4;
|
||||||
|
}
|
||||||
|
shift &= 0xFF;
|
||||||
|
int shiftVal = cpu->gprs[rm];
|
||||||
|
if (rm == ARM_PC) {
|
||||||
|
shiftVal += 4;
|
||||||
|
}
|
||||||
|
int rotate = shift & 0x1F;
|
||||||
|
if (!shift) {
|
||||||
|
cpu->shifterOperand = shiftVal;
|
||||||
|
cpu->shifterCarryOut = cpu->cpsr.c;
|
||||||
|
} else if (rotate) {
|
||||||
|
cpu->shifterOperand = ROR(shiftVal, rotate);
|
||||||
|
cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
|
||||||
|
} else {
|
||||||
|
cpu->shifterOperand = shiftVal;
|
||||||
|
cpu->shifterCarryOut = ARM_SIGN(shiftVal);
|
||||||
|
}
|
||||||
} else {
|
} else {
|
||||||
// RRX
|
int immediate = (opcode & 0x00000F80) >> 7;
|
||||||
cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
|
if (immediate) {
|
||||||
cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
|
cpu->shifterOperand = ROR(cpu->gprs[rm], immediate);
|
||||||
}
|
cpu->shifterCarryOut = (cpu->gprs[rm] >> (immediate - 1)) & 1;
|
||||||
}
|
} else {
|
||||||
|
// RRX
|
||||||
static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
|
cpu->shifterOperand = (cpu->cpsr.c << 31) | (((uint32_t) cpu->gprs[rm]) >> 1);
|
||||||
int rm = opcode & 0x0000000F;
|
cpu->shifterCarryOut = cpu->gprs[rm] & 0x00000001;
|
||||||
int rs = (opcode >> 8) & 0x0000000F;
|
}
|
||||||
++cpu->cycles;
|
|
||||||
int shift = cpu->gprs[rs];
|
|
||||||
if (rs == ARM_PC) {
|
|
||||||
shift += 4;
|
|
||||||
}
|
|
||||||
shift &= 0xFF;
|
|
||||||
int shiftVal = cpu->gprs[rm];
|
|
||||||
if (rm == ARM_PC) {
|
|
||||||
shiftVal += 4;
|
|
||||||
}
|
|
||||||
int rotate = shift & 0x1F;
|
|
||||||
if (!shift) {
|
|
||||||
cpu->shifterOperand = shiftVal;
|
|
||||||
cpu->shifterCarryOut = cpu->cpsr.c;
|
|
||||||
} else if (rotate) {
|
|
||||||
cpu->shifterOperand = ROR(shiftVal, rotate);
|
|
||||||
cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
|
|
||||||
} else {
|
|
||||||
cpu->shifterOperand = shiftVal;
|
|
||||||
cpu->shifterCarryOut = ARM_SIGN(shiftVal);
|
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -293,32 +289,20 @@ static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
|
||||||
#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
|
#define DEFINE_ALU_INSTRUCTION_ARM(NAME, S_BODY, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, , _shiftLSL, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSL, S_BODY, _shiftLSL, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, , _shiftLSLR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSLR, S_BODY, _shiftLSLR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, , _shiftLSR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSR, S_BODY, _shiftLSR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, , _shiftLSRR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_LSRR, S_BODY, _shiftLSRR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, , _shiftASR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASR, S_BODY, _shiftASR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, , _shiftASRR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ASRR, S_BODY, _shiftASRR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, , _shiftROR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_ROR, S_BODY, _shiftROR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, , _shiftRORR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## S_RORR, S_BODY, _shiftRORR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, , _immediate, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## SI, S_BODY, _immediate, BODY)
|
||||||
|
|
||||||
#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
|
#define DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(NAME, S_BODY, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSL, S_BODY, _shiftLSL, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSLR, S_BODY, _shiftLSLR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSR, S_BODY, _shiftLSR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _LSRR, S_BODY, _shiftLSRR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASR, S_BODY, _shiftASR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ASRR, S_BODY, _shiftASRR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _ROR, S_BODY, _shiftROR, BODY) \
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## _RORR, S_BODY, _shiftRORR, BODY) \
|
|
||||||
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
|
DEFINE_ALU_INSTRUCTION_EX_ARM(NAME ## I, S_BODY, _immediate, BODY)
|
||||||
|
|
||||||
#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
|
#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
|
||||||
|
|
|
@ -388,7 +388,7 @@ void GBADetachDebugger(struct GBA* gba) {
|
||||||
gba->cpu->components[GBA_COMPONENT_DEBUGGER] = 0;
|
gba->cpu->components[GBA_COMPONENT_DEBUGGER] = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
void GBALoadROM(struct GBA* gba, struct VFile* vf, struct VFile* sav, const char* fname) {
|
bool GBALoadROM(struct GBA* gba, struct VFile* vf, struct VFile* sav, const char* fname) {
|
||||||
GBAUnloadROM(gba);
|
GBAUnloadROM(gba);
|
||||||
gba->romVf = vf;
|
gba->romVf = vf;
|
||||||
gba->pristineRomSize = vf->size(vf);
|
gba->pristineRomSize = vf->size(vf);
|
||||||
|
@ -399,7 +399,7 @@ void GBALoadROM(struct GBA* gba, struct VFile* vf, struct VFile* sav, const char
|
||||||
gba->pristineRom = vf->map(vf, gba->pristineRomSize, MAP_READ);
|
gba->pristineRom = vf->map(vf, gba->pristineRomSize, MAP_READ);
|
||||||
if (!gba->pristineRom) {
|
if (!gba->pristineRom) {
|
||||||
GBALog(gba, GBA_LOG_WARN, "Couldn't map ROM");
|
GBALog(gba, GBA_LOG_WARN, "Couldn't map ROM");
|
||||||
return;
|
return false;
|
||||||
}
|
}
|
||||||
gba->yankedRomSize = 0;
|
gba->yankedRomSize = 0;
|
||||||
gba->memory.rom = gba->pristineRom;
|
gba->memory.rom = gba->pristineRom;
|
||||||
|
@ -409,6 +409,7 @@ void GBALoadROM(struct GBA* gba, struct VFile* vf, struct VFile* sav, const char
|
||||||
gba->romCrc32 = doCrc32(gba->memory.rom, gba->memory.romSize);
|
gba->romCrc32 = doCrc32(gba->memory.rom, gba->memory.romSize);
|
||||||
GBASavedataInit(&gba->memory.savedata, sav);
|
GBASavedataInit(&gba->memory.savedata, sav);
|
||||||
GBAHardwareInit(&gba->memory.hw, &((uint16_t*) gba->memory.rom)[GPIO_REG_DATA >> 1]);
|
GBAHardwareInit(&gba->memory.hw, &((uint16_t*) gba->memory.rom)[GPIO_REG_DATA >> 1]);
|
||||||
|
return true;
|
||||||
// TODO: error check
|
// TODO: error check
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
@ -166,7 +166,7 @@ void GBASetBreakpoint(struct GBA* gba, struct ARMComponent* component, uint32_t
|
||||||
uint32_t* opcode);
|
uint32_t* opcode);
|
||||||
void GBAClearBreakpoint(struct GBA* gba, uint32_t address, enum ExecutionMode mode, uint32_t opcode);
|
void GBAClearBreakpoint(struct GBA* gba, uint32_t address, enum ExecutionMode mode, uint32_t opcode);
|
||||||
|
|
||||||
void GBALoadROM(struct GBA* gba, struct VFile* vf, struct VFile* sav, const char* fname);
|
bool GBALoadROM(struct GBA* gba, struct VFile* vf, struct VFile* sav, const char* fname);
|
||||||
void GBAYankROM(struct GBA* gba);
|
void GBAYankROM(struct GBA* gba);
|
||||||
void GBAUnloadROM(struct GBA* gba);
|
void GBAUnloadROM(struct GBA* gba);
|
||||||
void GBALoadBIOS(struct GBA* gba, struct VFile* vf);
|
void GBALoadBIOS(struct GBA* gba, struct VFile* vf);
|
||||||
|
|
|
@ -16,6 +16,7 @@ bool GBAContextInit(struct GBAContext* context, const char* port) {
|
||||||
context->rom = 0;
|
context->rom = 0;
|
||||||
context->save = 0;
|
context->save = 0;
|
||||||
context->renderer = 0;
|
context->renderer = 0;
|
||||||
|
memset(context->components, 0, sizeof(context->components));
|
||||||
|
|
||||||
if (!context->gba || !context->cpu) {
|
if (!context->gba || !context->cpu) {
|
||||||
if (context->gba) {
|
if (context->gba) {
|
||||||
|
@ -33,7 +34,7 @@ bool GBAContextInit(struct GBAContext* context, const char* port) {
|
||||||
}
|
}
|
||||||
|
|
||||||
GBACreate(context->gba);
|
GBACreate(context->gba);
|
||||||
ARMSetComponents(context->cpu, &context->gba->d, 0, 0);
|
ARMSetComponents(context->cpu, &context->gba->d, 0, context->components);
|
||||||
ARMInit(context->cpu);
|
ARMInit(context->cpu);
|
||||||
|
|
||||||
context->gba->sync = 0;
|
context->gba->sync = 0;
|
||||||
|
@ -113,13 +114,16 @@ bool GBAContextLoadBIOSFromVFile(struct GBAContext* context, struct VFile* bios)
|
||||||
|
|
||||||
bool GBAContextStart(struct GBAContext* context) {
|
bool GBAContextStart(struct GBAContext* context) {
|
||||||
struct GBAOptions opts = {};
|
struct GBAOptions opts = {};
|
||||||
GBAConfigMap(&context->config, &opts);
|
|
||||||
|
|
||||||
if (context->renderer) {
|
if (context->renderer) {
|
||||||
GBAVideoAssociateRenderer(&context->gba->video, context->renderer);
|
GBAVideoAssociateRenderer(&context->gba->video, context->renderer);
|
||||||
}
|
}
|
||||||
|
|
||||||
GBALoadROM(context->gba, context->rom, context->save, 0);
|
if (!GBALoadROM(context->gba, context->rom, context->save, 0)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
GBAConfigMap(&context->config, &opts);
|
||||||
if (opts.useBios && context->bios) {
|
if (opts.useBios && context->bios) {
|
||||||
GBALoadBIOS(context->gba, context->bios);
|
GBALoadBIOS(context->gba, context->bios);
|
||||||
}
|
}
|
||||||
|
|
|
@ -18,6 +18,7 @@ struct GBAContext {
|
||||||
struct VFile* rom;
|
struct VFile* rom;
|
||||||
struct VFile* save;
|
struct VFile* save;
|
||||||
struct VFile* bios;
|
struct VFile* bios;
|
||||||
|
struct ARMComponent* components[GBA_COMPONENT_MAX];
|
||||||
struct GBAConfig config;
|
struct GBAConfig config;
|
||||||
struct GBAOptions opts;
|
struct GBAOptions opts;
|
||||||
struct GBAInputMap inputMap;
|
struct GBAInputMap inputMap;
|
||||||
|
|
|
@ -20,6 +20,8 @@ enum GUIInput {
|
||||||
GUI_INPUT_DOWN,
|
GUI_INPUT_DOWN,
|
||||||
GUI_INPUT_LEFT,
|
GUI_INPUT_LEFT,
|
||||||
GUI_INPUT_RIGHT,
|
GUI_INPUT_RIGHT,
|
||||||
|
|
||||||
|
GUI_INPUT_MAX
|
||||||
};
|
};
|
||||||
|
|
||||||
struct GUIParams {
|
struct GUIParams {
|
||||||
|
|
|
@ -26,6 +26,10 @@ void _upDirectory(char* currentPath) {
|
||||||
if (!end) {
|
if (!end) {
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
if (end == currentPath) {
|
||||||
|
end[1] = '\0';
|
||||||
|
return;
|
||||||
|
}
|
||||||
end[0] = '\0';
|
end[0] = '\0';
|
||||||
if (end[1]) {
|
if (end[1]) {
|
||||||
return;
|
return;
|
||||||
|
@ -54,7 +58,6 @@ bool _refreshDirectory(const char* currentPath, struct FileList* currentFiles) {
|
||||||
bool selectFile(const struct GUIParams* params, const char* basePath, char* outPath, size_t outLen, const char* suffix) {
|
bool selectFile(const struct GUIParams* params, const char* basePath, char* outPath, size_t outLen, const char* suffix) {
|
||||||
char currentPath[256];
|
char currentPath[256];
|
||||||
strncpy(currentPath, basePath, sizeof(currentPath));
|
strncpy(currentPath, basePath, sizeof(currentPath));
|
||||||
int oldInput = -1;
|
|
||||||
size_t fileIndex = 0;
|
size_t fileIndex = 0;
|
||||||
size_t start = 0;
|
size_t start = 0;
|
||||||
|
|
||||||
|
@ -62,10 +65,21 @@ bool selectFile(const struct GUIParams* params, const char* basePath, char* outP
|
||||||
FileListInit(¤tFiles, 0);
|
FileListInit(¤tFiles, 0);
|
||||||
_refreshDirectory(currentPath, ¤tFiles);
|
_refreshDirectory(currentPath, ¤tFiles);
|
||||||
|
|
||||||
|
int inputHistory[GUI_INPUT_MAX] = { 0 };
|
||||||
|
|
||||||
while (true) {
|
while (true) {
|
||||||
int input = params->pollInput();
|
int input = params->pollInput();
|
||||||
int newInput = input & (oldInput ^ input);
|
int newInput = 0;
|
||||||
oldInput = input;
|
for (int i = 0; i < GUI_INPUT_MAX; ++i) {
|
||||||
|
if (input & (1 << i)) {
|
||||||
|
++inputHistory[i];
|
||||||
|
} else {
|
||||||
|
inputHistory[i] = -1;
|
||||||
|
}
|
||||||
|
if (!inputHistory[i] || (inputHistory[i] >= 30 && !(inputHistory[i] % 6))) {
|
||||||
|
newInput |= (1 << i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
if (newInput & (1 << GUI_INPUT_UP) && fileIndex > 0) {
|
if (newInput & (1 << GUI_INPUT_UP) && fileIndex > 0) {
|
||||||
--fileIndex;
|
--fileIndex;
|
||||||
|
@ -85,7 +99,12 @@ bool selectFile(const struct GUIParams* params, const char* basePath, char* outP
|
||||||
return false;
|
return false;
|
||||||
}
|
}
|
||||||
if (newInput & (1 << GUI_INPUT_SELECT)) {
|
if (newInput & (1 << GUI_INPUT_SELECT)) {
|
||||||
snprintf(currentPath, sizeof(currentPath), "%s%c%s", currentPath, '/', *FileListGetPointer(¤tFiles, fileIndex));
|
size_t len = strlen(currentPath);
|
||||||
|
const char* sep = PATH_SEP;
|
||||||
|
if (currentPath[len - 1] == *sep) {
|
||||||
|
sep = "";
|
||||||
|
}
|
||||||
|
snprintf(currentPath, sizeof(currentPath), "%s%s%s", currentPath, sep, *FileListGetPointer(¤tFiles, fileIndex));
|
||||||
if (!_refreshDirectory(currentPath, ¤tFiles)) {
|
if (!_refreshDirectory(currentPath, ¤tFiles)) {
|
||||||
strncpy(outPath, currentPath, outLen);
|
strncpy(outPath, currentPath, outLen);
|
||||||
return true;
|
return true;
|
||||||
|
|
|
@ -49,7 +49,7 @@ struct GUIFontGlyphMetric defaultFontMetrics[128] = {
|
||||||
{ 6, 11, { 2, 5, 3, 5 }}, // 0x28 "("
|
{ 6, 11, { 2, 5, 3, 5 }}, // 0x28 "("
|
||||||
{ 6, 11, { 2, 5, 3, 5 }}, // 0x29 ")"
|
{ 6, 11, { 2, 5, 3, 5 }}, // 0x29 ")"
|
||||||
{ 8, 7, { 2, 4, 5, 4 }}, // 0x2A "*"
|
{ 8, 7, { 2, 4, 5, 4 }}, // 0x2A "*"
|
||||||
{ 10, 9, { 3, 0, 4, 0 }}, // 0x2B "+"
|
{ 10, 9, { 3, 3, 4, 3 }}, // 0x2B "+"
|
||||||
{ 4, 5, { 9, 6, 2, 6 }}, // 0x2C ","
|
{ 4, 5, { 9, 6, 2, 6 }}, // 0x2C ","
|
||||||
{ 6, 3, { 6, 4, 7, 4 }}, // 0x2D "-"
|
{ 6, 3, { 6, 4, 7, 4 }}, // 0x2D "-"
|
||||||
{ 4, 4, { 9, 6, 3, 6 }}, // 0x2E "."
|
{ 4, 4, { 9, 6, 3, 6 }}, // 0x2E "."
|
||||||
|
@ -115,7 +115,7 @@ struct GUIFontGlyphMetric defaultFontMetrics[128] = {
|
||||||
{ 7, 13, { 2, 5, 1, 4 }}, // 0x6A "j"
|
{ 7, 13, { 2, 5, 1, 4 }}, // 0x6A "j"
|
||||||
{ 8, 11, { 2, 4, 3, 4 }}, // 0x6B "k"
|
{ 8, 11, { 2, 4, 3, 4 }}, // 0x6B "k"
|
||||||
{ 5, 11, { 2, 5, 3, 6 }}, // 0x6C "l"
|
{ 5, 11, { 2, 5, 3, 6 }}, // 0x6C "l"
|
||||||
{ 10, 7, { 6, 2, 3, 2 }}, // 0x6D "m"
|
{ 10, 7, { 6, 3, 3, 3 }}, // 0x6D "m"
|
||||||
{ 8, 7, { 6, 4, 3, 4 }}, // 0x6E "n"
|
{ 8, 7, { 6, 4, 3, 4 }}, // 0x6E "n"
|
||||||
{ 8, 7, { 6, 4, 3, 4 }}, // 0x6F "o"
|
{ 8, 7, { 6, 4, 3, 4 }}, // 0x6F "o"
|
||||||
{ 8, 9, { 6, 4, 1, 4 }}, // 0x70 "p"
|
{ 8, 9, { 6, 4, 1, 4 }}, // 0x70 "p"
|
||||||
|
|
Loading…
Reference in New Issue