From 6608ae282c7830f3a8b13853405b753bc162ad7a Mon Sep 17 00:00:00 2001 From: Jeffrey Pfau Date: Wed, 17 Apr 2013 23:54:31 -0700 Subject: [PATCH] Ensure loads to PC work --- src/arm/isa-arm.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/arm/isa-arm.c b/src/arm/isa-arm.c index d0284b36e..b3815dd10 100644 --- a/src/arm/isa-arm.c +++ b/src/arm/isa-arm.c @@ -248,6 +248,11 @@ void ARMStep(struct ARMCore* cpu) { #define ADDR_MODE_3_INDEX(U_OP, M) ADDR_MODE_2_INDEX(U_OP, M) #define ADDR_MODE_3_WRITEBACK(ADDR) ADDR_MODE_2_WRITEBACK(ADDR) +#define ARM_LOAD_POST_BODY \ + if (rd == ARM_PC) { \ + ARM_WRITE_PC; \ + } + #define DEFINE_INSTRUCTION_ARM(NAME, BODY) \ static void _ARMInstruction ## NAME (struct ARMCore* cpu, uint32_t opcode) { \ BODY; \ @@ -492,11 +497,11 @@ DEFINE_INSTRUCTION_ARM(UMULLS, ARM_STUB) // Begin load/store definitions -DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address)) -DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address)) -DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address)) -DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address)) -DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address)) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDR, cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); ARM_LOAD_POST_BODY;) +DEFINE_LOAD_STORE_INSTRUCTION_ARM(LDRB, cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); ARM_LOAD_POST_BODY;) +DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRH, cpu->gprs[rd] = cpu->memory->loadU16(cpu->memory, address); ARM_LOAD_POST_BODY;) +DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSB, cpu->gprs[rd] = cpu->memory->load8(cpu->memory, address); ARM_LOAD_POST_BODY;) +DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(LDRSH, cpu->gprs[rd] = cpu->memory->load16(cpu->memory, address); ARM_LOAD_POST_BODY;) DEFINE_LOAD_STORE_INSTRUCTION_ARM(STR, cpu->memory->store32(cpu->memory, address, cpu->gprs[rd])) DEFINE_LOAD_STORE_INSTRUCTION_ARM(STRB, cpu->memory->store8(cpu->memory, address, cpu->gprs[rd])) DEFINE_LOAD_STORE_MODE_3_INSTRUCTION_ARM(STRH, cpu->memory->store16(cpu->memory, address, cpu->gprs[rd])) @@ -505,13 +510,15 @@ DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRBT, enum PrivilegeMode priv = cpu->privilegeMode; ARMSetPrivilegeMode(cpu, MODE_USER); cpu->gprs[rd] = cpu->memory->loadU8(cpu->memory, address); - ARMSetPrivilegeMode(cpu, priv);) + ARMSetPrivilegeMode(cpu, priv); + ARM_LOAD_POST_BODY;) DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(LDRT, enum PrivilegeMode priv = cpu->privilegeMode; ARMSetPrivilegeMode(cpu, MODE_USER); cpu->gprs[rd] = cpu->memory->load32(cpu->memory, address); - ARMSetPrivilegeMode(cpu, priv);) + ARMSetPrivilegeMode(cpu, priv); + ARM_LOAD_POST_BODY;) DEFINE_LOAD_STORE_T_INSTRUCTION_ARM(STRBT, enum PrivilegeMode priv = cpu->privilegeMode;