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GBA Memory: Optimize Load-/StoreMultiple

This commit is contained in:
Jeffrey Pfau 2016-08-19 18:51:25 -07:00
parent 9efb41ecd5
commit 5e50a635cf
2 changed files with 11 additions and 16 deletions
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1
CHANGES
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@ -64,6 +64,7 @@ Misc:
- PSP2: Allow UTF-8 filenames
- Util: Add Vector GetConstPointer
- Util: Add rtrim
- GBA Memory: Optimize Load-/StoreMultiple
0.4.1: (2016-07-11)
Bugfixes:

26
src/gba/memory.c
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@ -1220,28 +1220,24 @@ void GBAPatch8(struct ARMCore* cpu, uint32_t address, int8_t value, int8_t* old)
for (i = 0; i < 16; i += 4) { \
if (UNLIKELY(mask & (1 << i))) { \
LDM; \
waitstatesRegion = memory->waitstatesSeq32; \
cpu->gprs[i] = value; \
++wait; \
address += 4; \
} \
if (UNLIKELY(mask & (2 << i))) { \
LDM; \
waitstatesRegion = memory->waitstatesSeq32; \
cpu->gprs[i + 1] = value; \
++wait; \
address += 4; \
} \
if (UNLIKELY(mask & (4 << i))) { \
LDM; \
waitstatesRegion = memory->waitstatesSeq32; \
cpu->gprs[i + 2] = value; \
++wait; \
address += 4; \
} \
if (UNLIKELY(mask & (8 << i))) { \
LDM; \
waitstatesRegion = memory->waitstatesSeq32; \
cpu->gprs[i + 3] = value; \
++wait; \
address += 4; \
@ -1252,8 +1248,7 @@ uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
struct GBA* gba = (struct GBA*) cpu->master;
struct GBAMemory* memory = &gba->memory;
uint32_t value;
int wait = 0;
char* waitstatesRegion = memory->waitstatesNonseq32;
char* waitstatesRegion = memory->waitstatesSeq32;
int i;
int offset = 4;
@ -1269,11 +1264,13 @@ uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
}
uint32_t addressMisalign = address & 0x3;
if (address >> BASE_OFFSET < REGION_CART_SRAM) {
int region = address >> BASE_OFFSET;
if (region < REGION_CART_SRAM) {
address &= 0xFFFFFFFC;
}
int wait = memory->waitstatesSeq32[region] - memory->waitstatesNonseq32[region];
switch (address >> BASE_OFFSET) {
switch (region) {
case REGION_BIOS:
LDM_LOOP(LOAD_BIOS);
break;
@ -1336,28 +1333,24 @@ uint32_t GBALoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum L
if (UNLIKELY(mask & (1 << i))) { \
value = cpu->gprs[i]; \
STM; \
waitstatesRegion = memory->waitstatesSeq32; \
++wait; \
address += 4; \
} \
if (UNLIKELY(mask & (2 << i))) { \
value = cpu->gprs[i + 1]; \
STM; \
waitstatesRegion = memory->waitstatesSeq32; \
++wait; \
address += 4; \
} \
if (UNLIKELY(mask & (4 << i))) { \
value = cpu->gprs[i + 2]; \
STM; \
waitstatesRegion = memory->waitstatesSeq32; \
++wait; \
address += 4; \
} \
if (UNLIKELY(mask & (8 << i))) { \
value = cpu->gprs[i + 3]; \
STM; \
waitstatesRegion = memory->waitstatesSeq32; \
++wait; \
address += 4; \
} \
@ -1367,8 +1360,7 @@ uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum
struct GBA* gba = (struct GBA*) cpu->master;
struct GBAMemory* memory = &gba->memory;
uint32_t value;
int wait = 0;
char* waitstatesRegion = memory->waitstatesNonseq32;
char* waitstatesRegion = memory->waitstatesSeq32;
int i;
int offset = 4;
@ -1384,11 +1376,13 @@ uint32_t GBAStoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum
}
uint32_t addressMisalign = address & 0x3;
if (address >> BASE_OFFSET < REGION_CART_SRAM) {
int region = address >> BASE_OFFSET;
if (region < REGION_CART_SRAM) {
address &= 0xFFFFFFFC;
}
int wait = memory->waitstatesSeq32[region] - memory->waitstatesNonseq32[region];
switch (address >> BASE_OFFSET) {
switch (region) {
case REGION_WORKING_RAM:
STM_LOOP(STORE_WORKING_RAM);
break;