mirror of https://github.com/mgba-emu/mgba.git
Cleanup
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f2a1257fbb
commit
5dd2379dd5
33
src/arm.c
33
src/arm.c
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@ -450,40 +450,23 @@ DEFINE_INSTRUCTION_ARM(MRSI,)
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DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \
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DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME))), \
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DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME)))
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DO_8(DO_8(DECLARE_INSTRUCTION_ARM(COND, NAME)))
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#define LDRHW ILL
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#define LDRSBW ILL
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#define LDRSHW ILL
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#define LDRHIW ILL
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#define LDRSBIW ILL
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#define LDRSHIW ILL
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#define LDRHUW ILL
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#define LDRSBUW ILL
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#define LDRSHUW ILL
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#define LDRHIUW ILL
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#define LDRSBIUW ILL
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#define LDRSHIUW ILL
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#define STRHIW ILL
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#define STRHIUW ILL
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#define STRHUW ILL
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#define STRHW ILL
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#define DECLARE_COND_BLOCK(COND) \
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#define DECLARE_COND_BLOCK(COND) \
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DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, AND, MUL, STRH, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, ANDS, MULS, LDRH, LDRSB, LDRSH), \
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DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, STRHW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, EOR, MLA, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, LDRHW, LDRSBW, LDRSHW), \
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DECLARE_ARM_ALU_BLOCK(COND, EORS, MLAS, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SUB, ILL, STRHI, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
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DECLARE_ARM_ALU_BLOCK(COND, SUBS, ILL, LDRHI, LDRSBI, LDRSHI), \
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DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, STRHIW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSB, ILL, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, LDRHIW, LDRSBIW, LDRSHIW), \
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DECLARE_ARM_ALU_BLOCK(COND, RSBS, ILL, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADD, UMULL, STRHU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
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DECLARE_ARM_ALU_BLOCK(COND, ADDS, UMULLS, LDRHU, LDRSBU, LDRSHU), \
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DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, STRHUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADC, UMLAL, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, LDRHUW, LDRSBUW, LDRSHUW), \
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DECLARE_ARM_ALU_BLOCK(COND, ADCS, UMLALS, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SBC, SMULL, STRHIU, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
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DECLARE_ARM_ALU_BLOCK(COND, SBCS, SMULLS, LDRHIU, LDRSBIU, LDRSHIU), \
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DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, STRHIUW, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSC, SMLAL, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, LDRHIUW, LDRSBIUW, LDRSHIUW), \
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DECLARE_ARM_ALU_BLOCK(COND, RSCS, SMLALS, ILL, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, MRS, SWP, STRHP, ILL, ILL), \
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DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
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DECLARE_ARM_ALU_BLOCK(COND, TST, ILL, LDRHP, LDRSBP, LDRSHP), \
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DECLARE_INSTRUCTION_ARM(COND, MSR), \
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DECLARE_INSTRUCTION_ARM(COND, MSR), \
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