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LR35902: Improve stalling behavior

This commit is contained in:
Jeffrey Pfau 2016-01-15 02:49:06 -08:00
parent b104a5cd1c
commit 5bce4480db
3 changed files with 14 additions and 18 deletions
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25
src/lr35902/isa-lr35902.c
View File

@ -27,8 +27,7 @@ DEFINE_INSTRUCTION_LR35902(JPFinish,
if (cpu->condition) {
cpu->pc = (cpu->bus << 8) | cpu->index;
cpu->memory.setActiveRegion(cpu, cpu->pc);
// TODO: Stall properly
cpu->cycles += 4;
cpu->executionState = LR35902_CORE_STALL;
})
DEFINE_INSTRUCTION_LR35902(JPDelay,
@ -48,8 +47,7 @@ DEFINE_INSTRUCTION_LR35902(JRFinish,
if (cpu->condition) {
cpu->pc += (int8_t) cpu->bus;
cpu->memory.setActiveRegion(cpu, cpu->pc);
// TODO: Stall properly
cpu->cycles += 4;
cpu->executionState = LR35902_CORE_STALL;
})
#define DEFINE_JR_INSTRUCTION_LR35902(CONDITION_NAME, CONDITION) \
@ -64,8 +62,7 @@ DEFINE_INSTRUCTION_LR35902(CALLFinish,
if (cpu->condition) {
cpu->pc = (cpu->bus << 8) | cpu->index;
cpu->memory.setActiveRegion(cpu, cpu->pc);
// TODO: Stall properly
cpu->cycles += 4;
cpu->executionState = LR35902_CORE_STALL;
})
DEFINE_INSTRUCTION_LR35902(CALLUpdatePC,
@ -103,8 +100,7 @@ DEFINE_INSTRUCTION_LR35902(RETUpdateSPL,
cpu->pc |= cpu->bus << 8;
cpu->sp += 2;
cpu->memory.setActiveRegion(cpu, cpu->pc);
// TODO: Stall properly
cpu->cycles += 4;)
cpu->executionState = LR35902_CORE_STALL;)
DEFINE_INSTRUCTION_LR35902(RETUpdateSPH,
if (cpu->condition) {
@ -368,14 +364,11 @@ DEFINE_INSTRUCTION_LR35902(LDIOA, \
DEFINE_INSTRUCTION_LR35902(INC ## REG, \
uint16_t reg = LR35902Read ## REG (cpu); \
LR35902Write ## REG (cpu, reg + 1); \
/* TODO: Stall properly */ \
cpu->cycles += 4;) \
cpu->executionState = LR35902_CORE_STALL;) \
DEFINE_INSTRUCTION_LR35902(DEC ## REG, \
uint16_t reg = LR35902Read ## REG (cpu); \
LR35902Write ## REG (cpu, reg - 1); \
/* TODO: Stall properly */ \
cpu->cycles += 4;) \
cpu->executionState = LR35902_CORE_STALL;)
DEFINE_INCDEC_INSTRUCTION_LR35902(BC);
DEFINE_INCDEC_INSTRUCTION_LR35902(DE);
@ -383,13 +376,11 @@ DEFINE_INCDEC_INSTRUCTION_LR35902(HL);
DEFINE_INSTRUCTION_LR35902(INCSP,
++cpu->sp;
// TODO: Stall properly
cpu->cycles += 4;)
cpu->executionState = LR35902_CORE_STALL;)
DEFINE_INSTRUCTION_LR35902(DECSP,
--cpu->sp;
// TODO: Stall properly
cpu->cycles += 4;)
cpu->executionState = LR35902_CORE_STALL;)
DEFINE_INSTRUCTION_LR35902(DI, cpu->irqh.setInterrupts(cpu, false));
DEFINE_INSTRUCTION_LR35902(EI, cpu->irqh.setInterrupts(cpu, true));

6
src/lr35902/lr35902.c
View File

@ -85,7 +85,8 @@ void LR35902Tick(struct LR35902Core* cpu) {
cpu->pc = cpu->irqVector;
cpu->irqPending = false;
cpu->irqh.setInterrupts(cpu, false);
// TODO: stall
cpu->instruction = _lr35902InstructionTable[0]; // NOP
break;
}
cpu->bus = cpu->memory.load8(cpu, cpu->pc);
cpu->instruction = _lr35902InstructionTable[cpu->bus];
@ -104,6 +105,9 @@ void LR35902Tick(struct LR35902Core* cpu) {
cpu->bus = cpu->memory.load8(cpu, cpu->pc);
++cpu->pc;
break;
case LR35902_CORE_STALL:
cpu->instruction = _lr35902InstructionTable[0]; // NOP
break;
default:
break;
}

1
src/lr35902/lr35902.h
View File

@ -43,6 +43,7 @@ enum LR35902ExecutionState {
LR35902_CORE_MEMORY_LOAD = 4,
LR35902_CORE_MEMORY_STORE = 8,
LR35902_CORE_READ_PC = 12,
LR35902_CORE_STALL = 16
};
struct LR35902Memory {