mirror of https://github.com/mgba-emu/mgba.git
Debugger: Fix ARM LDM/STM disassembling
This commit is contained in:
parent
264f6f1df2
commit
5ace8e5023
|
@ -260,7 +260,7 @@
|
||||||
} \
|
} \
|
||||||
info->operandFormat = ARM_OPERAND_MEMORY_1; \
|
info->operandFormat = ARM_OPERAND_MEMORY_1; \
|
||||||
info->memory.format = ARM_MEMORY_REGISTER_BASE | \
|
info->memory.format = ARM_MEMORY_REGISTER_BASE | \
|
||||||
ARM_MEMORY_WRITEBACK | \
|
WRITEBACK | \
|
||||||
ARM_MEMORY_ ## DIRECTION;)
|
ARM_MEMORY_ ## DIRECTION;)
|
||||||
|
|
||||||
|
|
||||||
|
@ -273,14 +273,14 @@
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IB, NAME, INCREMENT_BEFORE, 0) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IB, NAME, INCREMENT_BEFORE, 0) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## IBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDA, NAME, DECREMENT_AFTER, 0) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDA, NAME, DECREMENT_AFTER, ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDAW, NAME, DECREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDB, NAME, DECREMENT_BEFORE, 0) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDB, NAME, DECREMENT_BEFORE, ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SDBW, NAME, DECREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIA, NAME, INCREMENT_AFTER, 0) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIA, NAME, INCREMENT_AFTER, ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIAW, NAME, INCREMENT_AFTER, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIB, NAME, INCREMENT_BEFORE, 0) \
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIB, NAME, INCREMENT_BEFORE, ARM_MEMORY_SPSR_SWAP) \
|
||||||
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK)
|
DEFINE_LOAD_STORE_MULTIPLE_DECODER_EX_ARM(NAME ## SIBW, NAME, INCREMENT_BEFORE, ARM_MEMORY_WRITEBACK | ARM_MEMORY_SPSR_SWAP)
|
||||||
|
|
||||||
#define DEFINE_SWP_DECODER_ARM(NAME, TYPE) \
|
#define DEFINE_SWP_DECODER_ARM(NAME, TYPE) \
|
||||||
DEFINE_DECODER_ARM(NAME, SWP, \
|
DEFINE_DECODER_ARM(NAME, SWP, \
|
||||||
|
|
|
@ -255,7 +255,7 @@ static const char* _armDirectionStrings[] = {
|
||||||
"da",
|
"da",
|
||||||
"ia",
|
"ia",
|
||||||
"db",
|
"db",
|
||||||
"da"
|
"ib"
|
||||||
};
|
};
|
||||||
|
|
||||||
static const char* _armAccessTypeStrings[] = {
|
static const char* _armAccessTypeStrings[] = {
|
||||||
|
@ -341,6 +341,10 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
|
||||||
ADVANCE(2);
|
ADVANCE(2);
|
||||||
written = _decodeRegisterList(info->op1.immediate, buffer, blen);
|
written = _decodeRegisterList(info->op1.immediate, buffer, blen);
|
||||||
ADVANCE(written);
|
ADVANCE(written);
|
||||||
|
if (info->memory.format & ARM_MEMORY_SPSR_SWAP) {
|
||||||
|
strncpy(buffer, "^", blen - 1);
|
||||||
|
ADVANCE(1);
|
||||||
|
}
|
||||||
break;
|
break;
|
||||||
case ARM_MN_B:
|
case ARM_MN_B:
|
||||||
written = _decodePCRelative(info->op1.immediate, pc, buffer, blen);
|
written = _decodePCRelative(info->op1.immediate, pc, buffer, blen);
|
||||||
|
|
|
@ -55,8 +55,9 @@
|
||||||
#define ARM_MEMORY_INCREMENT_AFTER 0x0100
|
#define ARM_MEMORY_INCREMENT_AFTER 0x0100
|
||||||
#define ARM_MEMORY_DECREMENT_BEFORE 0x0200
|
#define ARM_MEMORY_DECREMENT_BEFORE 0x0200
|
||||||
#define ARM_MEMORY_INCREMENT_BEFORE 0x0300
|
#define ARM_MEMORY_INCREMENT_BEFORE 0x0300
|
||||||
|
#define ARM_MEMORY_SPSR_SWAP 0x0400
|
||||||
|
|
||||||
#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x7)
|
#define MEMORY_FORMAT_TO_DIRECTION(F) (((F) >> 8) & 0x3)
|
||||||
|
|
||||||
enum ARMCondition {
|
enum ARMCondition {
|
||||||
ARM_CONDITION_EQ = 0x0,
|
ARM_CONDITION_EQ = 0x0,
|
||||||
|
|
Loading…
Reference in New Issue