mirror of https://github.com/mgba-emu/mgba.git
ARM7: Decode MCR/MRC
This commit is contained in:
Jeffrey Pfau
parent
2006f27d6d
commit
5939af0a2b
1
CHANGES
1
CHANGES
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@ -45,6 +45,7 @@ Bugfixes:
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- GB Video: Hblank IRQs should mask LYC=LY IRQs
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- GB Audio: Reset envelope timer when reseting sound channel
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- SDL: Prevent crash on cores with no audio
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- ARM7: Decode MCR/MRC
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Misc:
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- SDL: Remove scancode key input
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- GBA Video: Clean up unused timers
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@ -355,11 +355,24 @@ DEFINE_DECODER_ARM(BX, BX,
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// Begin coprocessor definitions
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DEFINE_DECODER_ARM(CDP, ILL, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_ARM(LDC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_ARM(STC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_ARM(MCR, ILL, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_ARM(MRC, ILL, info->operandFormat = ARM_OPERAND_NONE;)
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#define DEFINE_DECODER_COPROCESSOR(NAME, FORMAT) \
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DEFINE_DECODER_ARM(NAME, NAME, \
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info->cp.op1 = (opcode >> 21) & 7; \
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info->cp.op2 = (opcode >> 5) & 7; \
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info->op1.reg = (opcode >> 12) & 0xF; \
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info->cp.cp = (opcode >> 8) & 0xF; \
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info->op2.reg = (opcode >> 16) & 0xF; \
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info->op3.reg = opcode & 0xF; \
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info->operandFormat = ARM_OPERAND_REGISTER_1 |\
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ARM_OPERAND_COPROCESSOR_REG_2 | \
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ARM_OPERAND_COPROCESSOR_REG_3 | \
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(FORMAT);)
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DEFINE_DECODER_ARM(CDP, CDP, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_ARM(LDC, LDC, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_ARM(STC, STC, info->operandFormat = ARM_OPERAND_NONE;)
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DEFINE_DECODER_COPROCESSOR(MCR, ARM_OPERAND_AFFECTED_2 | ARM_OPERAND_AFFECTED_3)
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DEFINE_DECODER_COPROCESSOR(MRC, ARM_OPERAND_AFFECTED_1)
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// Begin miscellaneous definitions
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@ -251,15 +251,19 @@ static const char* _armMnemonicStrings[] = {
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"bkpt",
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"bl",
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"bx",
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"cdp",
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"cmn",
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"cmp",
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"eor",
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"ldc",
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"ldm",
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"ldr",
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"lsl",
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"lsr",
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"mcr",
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"mla",
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"mov",
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"mrc",
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"mrs",
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"msr",
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"mul",
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@ -272,6 +276,7 @@ static const char* _armMnemonicStrings[] = {
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"sbc",
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"smlal",
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"smull",
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"stc",
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"stm",
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"str",
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"sub",
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@ -388,6 +393,10 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
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}
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break;
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default:
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if (info->operandFormat & ARM_OPERAND_COPROCESSOR) {
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written = snprintf(buffer, blen - 1, "p%i, %i, ", info->cp.cp, info->cp.op1);
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ADVANCE(written);
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}
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if (info->operandFormat & ARM_OPERAND_IMMEDIATE_1) {
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written = snprintf(buffer, blen - 1, "#%i", info->op1.immediate);
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ADVANCE(written);
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@ -401,6 +410,8 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
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written = _decodePSR(info->op1.psrBits, buffer, blen);
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ADVANCE(written);
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}
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} else if (info->operandFormat & ARM_OPERAND_COPROCESSOR_REG_1) {
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written = snprintf(buffer, blen - 1, "c%i", info->op1.reg);
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}
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if (info->operandFormat & ARM_OPERAND_SHIFT_REGISTER_1) {
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written = _decodeShift(info->op1, true, buffer, blen);
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@ -422,6 +433,9 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
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} else if (info->operandFormat & ARM_OPERAND_REGISTER_2) {
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written = _decodeRegister(info->op2.reg, buffer, blen);
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ADVANCE(written);
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} else if (info->operandFormat & ARM_OPERAND_COPROCESSOR_REG_2) {
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written = snprintf(buffer, blen - 1, "c%i", info->op2.reg);
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ADVANCE(written);
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}
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if (info->operandFormat & ARM_OPERAND_SHIFT_REGISTER_2) {
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written = _decodeShift(info->op2, true, buffer, blen);
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@ -443,6 +457,9 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
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} else if (info->operandFormat & ARM_OPERAND_REGISTER_3) {
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written = _decodeRegister(info->op3.reg, buffer, blen);
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ADVANCE(written);
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} else if (info->operandFormat & ARM_OPERAND_COPROCESSOR_REG_3) {
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written = snprintf(buffer, blen - 1, "c%i", info->op3.reg);
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ADVANCE(written);
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}
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if (info->operandFormat & ARM_OPERAND_SHIFT_REGISTER_3) {
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written = _decodeShift(info->op3, true, buffer, blen);
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@ -464,6 +481,9 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
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} else if (info->operandFormat & ARM_OPERAND_REGISTER_4) {
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written = _decodeRegister(info->op4.reg, buffer, blen);
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ADVANCE(written);
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} else if (info->operandFormat & ARM_OPERAND_COPROCESSOR_REG_4) {
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written = snprintf(buffer, blen - 1, "c%i", info->op4.reg);
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ADVANCE(written);
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}
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if (info->operandFormat & ARM_OPERAND_SHIFT_REGISTER_4) {
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written = _decodeShift(info->op4, true, buffer, blen);
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@ -472,6 +492,10 @@ int ARMDisassemble(struct ARMInstructionInfo* info, uint32_t pc, char* buffer, i
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written = _decodeShift(info->op4, false, buffer, blen);
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ADVANCE(written);
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}
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if (info->cp.op2) {
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written = snprintf(buffer, blen - 1, ", %i", info->cp.op2);
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ADVANCE(written);
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}
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break;
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}
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buffer[blen - 1] = '\0';
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@ -14,6 +14,7 @@
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// Bit 3: the destination of this operand is affected by this opcode
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// Bit 4: this operand is shifted by a register
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// Bit 5: this operand is shifted by an immediate
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// Bit 6: a coprocessor register is involved with this command
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#define ARM_OPERAND_NONE 0x00000000
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#define ARM_OPERAND_REGISTER_1 0x00000001
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#define ARM_OPERAND_IMMEDIATE_1 0x00000002
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@ -21,6 +22,7 @@
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#define ARM_OPERAND_AFFECTED_1 0x00000008
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#define ARM_OPERAND_SHIFT_REGISTER_1 0x00000010
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#define ARM_OPERAND_SHIFT_IMMEDIATE_1 0x00000020
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#define ARM_OPERAND_COPROCESSOR_REG_1 0x00000040
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#define ARM_OPERAND_1 0x000000FF
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#define ARM_OPERAND_REGISTER_2 0x00000100
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@ -29,6 +31,7 @@
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#define ARM_OPERAND_AFFECTED_2 0x00000800
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#define ARM_OPERAND_SHIFT_REGISTER_2 0x00001000
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#define ARM_OPERAND_SHIFT_IMMEDIATE_2 0x00002000
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#define ARM_OPERAND_COPROCESSOR_REG_2 0x00004000
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#define ARM_OPERAND_2 0x0000FF00
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#define ARM_OPERAND_REGISTER_3 0x00010000
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@ -37,6 +40,7 @@
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#define ARM_OPERAND_AFFECTED_3 0x00080000
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#define ARM_OPERAND_SHIFT_REGISTER_3 0x00100000
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#define ARM_OPERAND_SHIFT_IMMEDIATE_3 0x00200000
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#define ARM_OPERAND_COPROCESSOR_REG_3 0x00400000
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#define ARM_OPERAND_3 0x00FF0000
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#define ARM_OPERAND_REGISTER_4 0x01000000
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@ -45,9 +49,11 @@
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#define ARM_OPERAND_AFFECTED_4 0x08000000
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#define ARM_OPERAND_SHIFT_REGISTER_4 0x10000000
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#define ARM_OPERAND_SHIFT_IMMEDIATE_4 0x20000000
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#define ARM_OPERAND_COPROCESSOR_REG_4 0x40000000
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#define ARM_OPERAND_4 0xFF000000
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#define ARM_OPERAND_MEMORY (ARM_OPERAND_MEMORY_1 | ARM_OPERAND_MEMORY_2 | ARM_OPERAND_MEMORY_3 | ARM_OPERAND_MEMORY_4)
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#define ARM_OPERAND_COPROCESSOR (ARM_OPERAND_COPROCESSOR_REG_1 | ARM_OPERAND_COPROCESSOR_REG_2 | ARM_OPERAND_COPROCESSOR_REG_3 | ARM_OPERAND_COPROCESSOR_REG_4)
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#define ARM_MEMORY_REGISTER_BASE 0x0001
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#define ARM_MEMORY_IMMEDIATE_OFFSET 0x0002
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@ -112,6 +118,12 @@ union ARMOperand {
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int32_t immediate;
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};
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struct ARMCoprocessor {
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uint8_t cp : 4;
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uint8_t op1 : 4;
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uint8_t op2 : 3;
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};
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enum ARMMemoryAccessType {
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ARM_ACCESS_WORD = 4,
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ARM_ACCESS_HALFWORD = 2,
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@ -147,15 +159,19 @@ enum ARMMnemonic {
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ARM_MN_BKPT,
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ARM_MN_BL,
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ARM_MN_BX,
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ARM_MN_CDP,
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ARM_MN_CMN,
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ARM_MN_CMP,
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ARM_MN_EOR,
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ARM_MN_LDC,
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ARM_MN_LDM,
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ARM_MN_LDR,
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ARM_MN_LSL,
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ARM_MN_LSR,
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ARM_MN_MCR,
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ARM_MN_MLA,
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ARM_MN_MOV,
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ARM_MN_MRC,
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ARM_MN_MRS,
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ARM_MN_MSR,
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ARM_MN_MUL,
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@ -168,6 +184,7 @@ enum ARMMnemonic {
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ARM_MN_SBC,
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ARM_MN_SMLAL,
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ARM_MN_SMULL,
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ARM_MN_STC,
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ARM_MN_STM,
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ARM_MN_STR,
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ARM_MN_SUB,
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@ -206,6 +223,7 @@ struct ARMInstructionInfo {
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unsigned nInstructionCycles : 4;
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unsigned sDataCycles : 10;
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unsigned nDataCycles : 10;
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struct ARMCoprocessor cp;
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};
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void ARMDecodeARM(uint32_t opcode, struct ARMInstructionInfo* info);
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@ -67,8 +67,10 @@
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME)), \
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DO_8(DECLARE_INSTRUCTION_ARM(EMITTER, NAME))
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#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2) \
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DO_8(DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))))
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#define DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, NAME1, NAME2, NAME3) \
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DO_8(DO_INTERLACE( \
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DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME2))), \
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DO_8(DO_INTERLACE(DECLARE_INSTRUCTION_ARM(EMITTER, NAME1), DECLARE_INSTRUCTION_ARM(EMITTER, NAME3)))))
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#define DECLARE_ARM_SWI_BLOCK(EMITTER) \
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DO_256(DECLARE_INSTRUCTION_ARM(EMITTER, SWI))
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@ -328,8 +330,7 @@
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DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, ), \
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DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, STC, P, U, N, W), \
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DECLARE_ARM_LOAD_STORE_COPROCESSOR_BLOCK(EMITTER, LDC, P, U, N, W), \
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DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR), \
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DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MRC), \
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DECLARE_ARM_COPROCESSOR_BLOCK(EMITTER, CDP, MCR, MRC), \
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DECLARE_ARM_SWI_BLOCK(EMITTER)
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#endif
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