mirror of https://github.com/mgba-emu/mgba.git
ARM: Fix long and accumulate multiply timing
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232aab5a08
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@ -24,6 +24,7 @@ Emulation fixes:
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- ARM: Fix STR storing PC after address calculation
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- ARM: Fix STR storing PC after address calculation
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- ARM: Fix Addressing mode 1 shifter on rs == pc (fixes mgba.io/i/1926)
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- ARM: Fix Addressing mode 1 shifter on rs == pc (fixes mgba.io/i/1926)
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- ARM: Fix long multiply-and-accumulate register write order (fixes mgba.io/1/1956)
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- ARM: Fix long multiply-and-accumulate register write order (fixes mgba.io/1/1956)
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- ARM: Fix long and accumulate multiply timing
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- GB: Partially fix timing for skipped BIOS
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- GB: Partially fix timing for skipped BIOS
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- GB: Downgrade DMG-only ROMs from CGB mode even without boot ROM
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- GB: Downgrade DMG-only ROMs from CGB mode even without boot ROM
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- GB Audio: Fix serializing sweep time
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- GB Audio: Fix serializing sweep time
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@ -37,17 +37,17 @@
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#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_V_ADDITION(M, N, D) (!(ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_V_SUBTRACTION(M, N, D) ((ARM_SIGN((M) ^ (N))) && (ARM_SIGN((M) ^ (D))))
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#define ARM_WAIT_MUL(R) \
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#define ARM_WAIT_MUL(R, WAIT) \
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{ \
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{ \
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int32_t wait; \
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int32_t wait = WAIT; \
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if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
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if ((R & 0xFFFFFF00) == 0xFFFFFF00 || !(R & 0xFFFFFF00)) { \
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wait = 1; \
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wait += 1; \
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} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
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} else if ((R & 0xFFFF0000) == 0xFFFF0000 || !(R & 0xFFFF0000)) { \
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wait = 2; \
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wait += 2; \
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} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
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} else if ((R & 0xFF000000) == 0xFF000000 || !(R & 0xFF000000)) { \
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wait = 3; \
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wait += 3; \
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} else { \
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} else { \
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wait = 4; \
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wait += 4; \
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} \
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} \
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currentCycles += cpu->memory.stall(cpu, wait); \
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currentCycles += cpu->memory.stall(cpu, wait); \
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}
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}
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@ -325,12 +325,11 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
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int rd = (opcode >> 16) & 0xF; \
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int rd = (opcode >> 16) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rm = opcode & 0xF; \
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int rm = opcode & 0xF; \
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if (rd == ARM_PC) { \
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if (rd != ARM_PC) { \
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return; \
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ARM_WAIT_MUL(cpu->gprs[rs], 0); \
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BODY; \
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S_BODY; \
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} \
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} \
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ARM_WAIT_MUL(cpu->gprs[rs]); \
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BODY; \
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S_BODY; \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
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#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
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@ -339,12 +338,11 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
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int rdHi = (opcode >> 16) & 0xF; \
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int rdHi = (opcode >> 16) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rm = opcode & 0xF; \
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int rm = opcode & 0xF; \
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if (rdHi == ARM_PC || rd == ARM_PC) { \
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if (rdHi != ARM_PC && rd != ARM_PC) { \
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return; \
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ARM_WAIT_MUL(cpu->gprs[rs], WAIT); \
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BODY; \
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S_BODY; \
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} \
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} \
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currentCycles += cpu->memory.stall(cpu, WAIT); \
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BODY; \
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S_BODY; \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
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#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
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@ -522,7 +520,7 @@ DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(n, cpu->shifterOperand, alu
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// Begin multiply definitions
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// Begin multiply definitions
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 1)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
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@ -530,26 +528,26 @@ DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
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int32_t dHi = cpu->gprs[rdHi] + (d >> 32);
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int32_t dHi = cpu->gprs[rdHi] + (d >> 32);
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cpu->gprs[rd] = d;
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cpu->gprs[rd] = d;
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cpu->gprs[rdHi] = dHi;,
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cpu->gprs[rdHi] = dHi;,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], dHi), 3)
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], dHi), 2)
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
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int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
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int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
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cpu->gprs[rd] = d;
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cpu->gprs[rd] = d;
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cpu->gprs[rdHi] = d >> 32;,
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cpu->gprs[rdHi] = d >> 32;,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 1)
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
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uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]) + ((uint32_t) cpu->gprs[rd]);
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uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]) + ((uint32_t) cpu->gprs[rd]);
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uint32_t dHi = ((uint32_t) cpu->gprs[rdHi]) + (d >> 32);
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uint32_t dHi = ((uint32_t) cpu->gprs[rdHi]) + (d >> 32);
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cpu->gprs[rd] = d;
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cpu->gprs[rd] = d;
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cpu->gprs[rdHi] = dHi;,
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cpu->gprs[rdHi] = dHi;,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], dHi), 3)
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], dHi), 2)
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
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uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
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uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
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cpu->gprs[rd] = d;
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cpu->gprs[rd] = d;
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cpu->gprs[rdHi] = d >> 32;,
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cpu->gprs[rdHi] = d >> 32;,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 1)
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// End multiply definitions
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// End multiply definitions
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@ -232,7 +232,7 @@ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, THUMB_SUBTRACTION(cpu->gprs[rd], 0, cp
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, int32_t aluOut = cpu->gprs[rd] - cpu->gprs[rn]; THUMB_SUBTRACTION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, int32_t aluOut = cpu->gprs[rd] + cpu->gprs[rn]; THUMB_ADDITION_S(cpu->gprs[rd], cpu->gprs[rn], aluOut))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, cpu->gprs[rd] = cpu->gprs[rd] | cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd]); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_WAIT_MUL(cpu->gprs[rd], 0); cpu->gprs[rd] *= cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]); currentCycles += cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16)
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, cpu->gprs[rd] = cpu->gprs[rd] & ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, cpu->gprs[rd] = ~cpu->gprs[rn]; THUMB_NEUTRAL_S( , , cpu->gprs[rd]))
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