DS Memory: Totally fake RAM timings

This commit is contained in:
Vicki Pfau 2017-03-01 20:12:34 -08:00
parent abf57aa602
commit 4920ab3690
1 changed files with 4 additions and 4 deletions

View File

@ -40,10 +40,10 @@ static const char DS7_BASE_WAITSTATES_32[16] = { 0, 0, 9, 0, 0, 1, 1, 0 };
static const char DS7_BASE_WAITSTATES_SEQ[16] = { 0, 0, 1, 0, 0, 0, 0, 0 };
static const char DS7_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 2, 0, 0, 1, 1, 0 };
static const char DS9_BASE_WAITSTATES[16] = { 0, 0, 17, 6, 6, 7, 7, 6 };
static const char DS9_BASE_WAITSTATES_32[16] = { 0, 0, 19, 6, 6, 9, 9, 6 };
static const char DS9_BASE_WAITSTATES_SEQ[16] = { 0, 0, 1, 1, 1, 2, 2, 1 };
static const char DS9_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 3, 1, 1, 4, 4, 1 };
static const char DS9_BASE_WAITSTATES[16] = { 0, 0, 2, 6, 6, 7, 7, 6 };
static const char DS9_BASE_WAITSTATES_32[16] = { 0, 0, 4, 6, 6, 9, 9, 6 };
static const char DS9_BASE_WAITSTATES_SEQ[16] = { 0, 0, 1, 1, 1, 2, 2, 1 };
static const char DS9_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 2, 1, 1, 4, 4, 1 };
void DSMemoryInit(struct DS* ds) {
struct ARMCore* arm7 = ds->ds7.cpu;