From 3e3bb58ae5860673c7c25ed92833f6392063ddb1 Mon Sep 17 00:00:00 2001 From: Jeffrey Pfau Date: Tue, 8 Oct 2013 02:10:40 -0700 Subject: [PATCH] Minor timing fixes --- src/arm/isa-arm.c | 2 +- src/arm/isa-inlines.h | 4 ++-- src/arm/isa-thumb.c | 11 ++++++----- src/gba/gba-memory.c | 5 ++--- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/arm/isa-arm.c b/src/arm/isa-arm.c index 5b8f0c787..e9f7d440c 100644 --- a/src/arm/isa-arm.c +++ b/src/arm/isa-arm.c @@ -710,7 +710,7 @@ DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(LDM, DEFINE_LOAD_STORE_MULTIPLE_INSTRUCTION_ARM(STM, cpu->memory->store32(cpu->memory, addr, cpu->gprs[i], 0);, - currentCycles -= ARM_PREFETCH_CYCLES) + currentCycles += cpu->memory->activeNonseqCycles32 - cpu->memory->activePrefetchCycles32) DEFINE_INSTRUCTION_ARM(SWP, ARM_STUB) DEFINE_INSTRUCTION_ARM(SWPB, ARM_STUB) diff --git a/src/arm/isa-inlines.h b/src/arm/isa-inlines.h index 091994a52..9b48513a9 100644 --- a/src/arm/isa-inlines.h +++ b/src/arm/isa-inlines.h @@ -68,12 +68,12 @@ #define ARM_WRITE_PC \ cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_ARM) + WORD_SIZE_ARM; \ cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC]); \ - cpu->cycles += 1 + cpu->memory->activePrefetchCycles32; + currentCycles += 2 + cpu->memory->activeNonseqCycles32 + cpu->memory->activePrefetchCycles32; #define THUMB_WRITE_PC \ cpu->gprs[ARM_PC] = (cpu->gprs[ARM_PC] & -WORD_SIZE_THUMB) + WORD_SIZE_THUMB; \ cpu->memory->setActiveRegion(cpu->memory, cpu->gprs[ARM_PC]); \ - cpu->cycles += 1 + cpu->memory->activePrefetchCycles16; + currentCycles += 2 + cpu->memory->activeNonseqCycles16 + cpu->memory->activePrefetchCycles16; static inline int _ARMModeHasSPSR(enum PrivilegeMode mode) { return mode != MODE_SYSTEM && mode != MODE_USER; diff --git a/src/arm/isa-thumb.c b/src/arm/isa-thumb.c index d0334647c..18e3cfaaf 100644 --- a/src/arm/isa-thumb.c +++ b/src/arm/isa-thumb.c @@ -46,8 +46,7 @@ void ThumbStep(struct ARMCore* cpu) { #define THUMB_PREFETCH_CYCLES (1 + cpu->memory->activePrefetchCycles16) #define THUMB_STORE_POST_BODY \ - currentCycles -= THUMB_PREFETCH_CYCLES; \ - currentCycles += 1 + cpu->memory->activeNonseqCycles16; + currentCycles += cpu->memory->activeNonseqCycles16 - cpu->memory->activePrefetchCycles16; #define APPLY(F, ...) F(__VA_ARGS__) @@ -377,7 +376,8 @@ DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA, DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0), - cpu->gprs[rn] = address) + THUMB_STORE_POST_BODY; + cpu->gprs[rn] = address;) #define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \ DEFINE_INSTRUCTION_THUMB(B ## COND, \ @@ -432,7 +432,8 @@ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, (m = 0x80, i = 7; m; m >>= 1, --i), cpu->memory->store32(cpu->memory, address, cpu->gprs[i], 0), -=, - , , + , + THUMB_STORE_POST_BODY, cpu->gprs[ARM_SP] = address + 4) DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, @@ -443,7 +444,7 @@ DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, -=, cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR], 0); address -= 4;, - , + THUMB_STORE_POST_BODY, cpu->gprs[ARM_SP] = address + 4) DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB) diff --git a/src/gba/gba-memory.c b/src/gba/gba-memory.c index ee2047228..43ab9f775 100644 --- a/src/gba/gba-memory.c +++ b/src/gba/gba-memory.c @@ -13,9 +13,9 @@ static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t region); static int GBAWaitMultiple(struct ARMMemory* memory, uint32_t startAddress, int count); static const char GBA_BASE_WAITSTATES[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 4, 4, 4, 4, 4, 4, 4 }; -static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 }; +static const char GBA_BASE_WAITSTATES_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 7, 7, 9, 9, 13, 13, 9 }; static const char GBA_BASE_WAITSTATES_SEQ[16] = { 0, 0, 2, 0, 0, 0, 0, 0, 2, 2, 4, 4, 8, 8, 4 }; -static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 4, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 }; +static const char GBA_BASE_WAITSTATES_SEQ_32[16] = { 0, 0, 5, 0, 0, 0, 0, 0, 5, 5, 9, 9, 17, 17, 9 }; static const char GBA_ROM_WAITSTATES[] = { 4, 3, 2, 8 }; static const char GBA_ROM_WAITSTATES_SEQ[] = { 2, 1, 4, 1, 8, 1 }; static const int DMA_OFFSET[] = { 1, -1, 0, 1 }; @@ -115,7 +115,6 @@ static void GBASetActiveRegion(struct ARMMemory* memory, uint32_t address) { memory->activeMask = 0; break; } - gbaMemory->p->cpu.cycles += 1 + (gbaMemory->p->cpu.executionMode == MODE_ARM ? gbaMemory->waitstates32[address >> BASE_OFFSET] : gbaMemory->waitstates16[address >> BASE_OFFSET]); } int32_t GBALoad32(struct ARMMemory* memory, uint32_t address, int* cycleCounter) {