mirror of https://github.com/mgba-emu/mgba.git
DS: A little more skeleton
This commit is contained in:
Jeffrey Pfau
parent
290d5b77dd
commit
3cf9446ba1
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@ -842,6 +842,7 @@ if(NOT QUIET)
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message(STATUS "Platforms:")
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message(STATUS " Game Boy Advance: ${M_CORE_GBA}")
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message(STATUS " Game Boy: ${M_CORE_GB}")
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message(STATUS " DS: ${M_CORE_DS}")
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message(STATUS "Features:")
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message(STATUS " Debuggers: ${USE_DEBUGGERS}")
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message(STATUS " CLI debugger: ${USE_EDITLINE}")
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@ -0,0 +1,11 @@
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/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "bios.h"
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mLOG_DEFINE_CATEGORY(DS_BIOS, "DS BIOS");
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const uint32_t DS7_BIOS_CHECKSUM = 0x1280F0D5;
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const uint32_t DS9_BIOS_CHECKSUM = 0x2AB23573;
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@ -0,0 +1,24 @@
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/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#ifndef DS_BIOS_H
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#define DS_BIOS_H
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#include "util/common.h"
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#include "core/log.h"
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mLOG_DECLARE_CATEGORY(DS_BIOS);
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struct ARMCore;
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void DS7Swi16(struct ARMCore* cpu, int immediate);
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void DS7Swi32(struct ARMCore* cpu, int immediate);
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void DS9Swi16(struct ARMCore* cpu, int immediate);
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void DS9Swi32(struct ARMCore* cpu, int immediate);
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extern const uint32_t DS7_BIOS_CHECKSUM;
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extern const uint32_t DS9_BIOS_CHECKSUM;
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#endif
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@ -91,6 +91,14 @@ static void _DSCoreSetSync(struct mCore* core, struct mCoreSync* sync) {
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}
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static void _DSCoreLoadConfig(struct mCore* core, const struct mCoreConfig* config) {
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struct DS* ds = core->board;
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struct VFile* bios = NULL;
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if (core->opts.useBios && core->opts.bios) {
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bios = VFileOpen(core->opts.bios, O_RDONLY);
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}
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if (bios) {
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DSLoadBIOS(ds, bios);
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}
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}
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static void _DSCoreDesiredVideoDimensions(struct mCore* core, unsigned* width, unsigned* height) {
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@ -124,7 +132,8 @@ static bool _DSCoreLoadROM(struct mCore* core, struct VFile* vf) {
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}
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static bool _DSCoreLoadBIOS(struct mCore* core, struct VFile* vf, int type) {
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return false;
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UNUSED(type);
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return DSLoadBIOS(core->board, vf);
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}
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static bool _DSCoreLoadSave(struct mCore* core, struct VFile* vf) {
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38
src/ds/ds.c
38
src/ds/ds.c
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@ -8,11 +8,11 @@
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#include "arm/decoder.h"
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#include "arm/debugger/debugger.h"
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#include "arm/isa-inlines.h"
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#include "ds/bios.h"
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#include "util/crc32.h"
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#include "util/memory.h"
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#include "util/math.h"
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#include "util/patch.h"
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#include "util/vfs.h"
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mLOG_DEFINE_CATEGORY(DS, "DS");
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@ -67,8 +67,11 @@ static void DSInit(void* cpu, struct mCPUComponent* component) {
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}
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ds->arm9 = cpu;
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ds->arm9->cp15.r1.c0 = ARMControlRegFillVE(0);
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DS7InterruptHandlerInit(&ds->arm7->irqh);
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DS9InterruptHandlerInit(&ds->arm9->irqh);
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DSMemoryInit(ds);
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ds->video.p = ds;
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@ -92,6 +95,7 @@ void DSUnloadROM(struct DS* ds) {
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void DSDestroy(struct DS* ds) {
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DSUnloadROM(ds);
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DSMemoryDeinit(ds);
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}
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void DS7InterruptHandlerInit(struct ARMInterruptHandler* irqh) {
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@ -134,6 +138,9 @@ void DS9Reset(struct ARMCore* cpu) {
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cpu->gprs[ARM_SP] = DS9_SP_BASE_SVC;
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ARMSetPrivilegeMode(cpu, MODE_SYSTEM);
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cpu->gprs[ARM_SP] = DS9_SP_BASE;
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struct DS* ds = (struct DS*) cpu->master;
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DSMemoryReset(ds);
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}
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static void DSProcessEvents(struct ARMCore* cpu) {
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@ -198,6 +205,35 @@ bool DSIsROM(struct VFile* vf) {
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return memcmp(signature, DS_ROM_MAGIC, sizeof(signature)) == 0;
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}
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bool DSLoadBIOS(struct DS* ds, struct VFile* vf) {
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size_t size = vf->size(vf);
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void* data = NULL;
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uint32_t crc;
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if (size == DS7_SIZE_BIOS) {
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data = vf->map(vf, size, MAP_READ);
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} else if (size == 0x1000) {
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data = vf->map(vf, size, MAP_READ);
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}
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if (!data) {
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return false;
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}
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crc = doCrc32(data, size);
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if (crc == DS7_BIOS_CHECKSUM) {
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ds->bios7Vf = vf;
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ds->memory.bios7 = data;
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mLOG(DS, INFO, "Official DS ARM7 BIOS detected");
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} else if (crc == DS9_BIOS_CHECKSUM) {
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ds->bios9Vf = vf;
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ds->memory.bios9 = data;
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mLOG(DS, INFO, "Official DS ARM9 BIOS detected");
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} else {
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mLOG(DS, WARN, "BIOS checksum incorrect");
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vf->unmap(vf, data, size);
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return false;
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}
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return true;
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}
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void DSGetGameCode(struct DS* ds, char* out) {
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memset(out, 0, 8);
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if (!ds->romVf) {
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10
src/ds/ds.h
10
src/ds/ds.h
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@ -11,6 +11,7 @@
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#include "arm/arm.h"
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#include "core/log.h"
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#include "ds/memory.h"
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#include "ds/video.h"
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extern const uint32_t DS_ARM946ES_FREQUENCY;
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@ -54,6 +55,7 @@ struct DS {
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struct ARMCore* arm7;
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struct ARMCore* arm9;
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struct DSMemory memory;
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struct DSVideo video;
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struct mCoreSync* sync;
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@ -63,13 +65,15 @@ struct DS {
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int springIRQ7;
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int springIRQ9;
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uint32_t biosChecksum;
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uint32_t bios7Checksum;
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uint32_t bios9Checksum;
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int* keySource;
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struct mRTCSource* rtcSource;
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struct mRumble* rumble;
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uint32_t romCrc32;
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struct VFile* romVf;
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struct VFile* bios7Vf;
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struct VFile* bios9Vf;
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struct mKeyCallback* keyCallback;
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};
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@ -121,6 +125,8 @@ bool DSLoadROM(struct DS* ds, struct VFile* vf);
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void DSUnloadROM(struct DS* ds);
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void DSApplyPatch(struct DS* ds, struct Patch* patch);
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bool DSLoadBIOS(struct DS* ds, struct VFile* vf);
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bool DSIsROM(struct VFile* vf);
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void DSGetGameCode(struct DS* ds, char* out);
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void DSGetGameTitle(struct DS* ds, char* out);
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@ -0,0 +1,583 @@
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/* Copyright (c) 2013-2016 Jeffrey Pfau
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*
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* This Source Code Form is subject to the terms of the Mozilla Public
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* License, v. 2.0. If a copy of the MPL was not distributed with this
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* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
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#include "memory.h"
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#include "ds/ds.h"
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#include "util/math.h"
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mLOG_DEFINE_CATEGORY(DS_MEM, "DS Memory");
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#define LDM_LOOP(LDM) \
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for (i = 0; i < 16; i += 4) { \
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if (UNLIKELY(mask & (1 << i))) { \
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LDM; \
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cpu->gprs[i] = value; \
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++wait; \
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address += 4; \
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} \
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if (UNLIKELY(mask & (2 << i))) { \
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LDM; \
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cpu->gprs[i + 1] = value; \
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++wait; \
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address += 4; \
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} \
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if (UNLIKELY(mask & (4 << i))) { \
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LDM; \
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cpu->gprs[i + 2] = value; \
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++wait; \
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address += 4; \
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} \
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if (UNLIKELY(mask & (8 << i))) { \
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LDM; \
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cpu->gprs[i + 3] = value; \
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++wait; \
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address += 4; \
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} \
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}
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#define STM_LOOP(STM) \
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for (i = 0; i < 16; i += 4) { \
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if (UNLIKELY(mask & (1 << i))) { \
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value = cpu->gprs[i]; \
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STM; \
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++wait; \
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address += 4; \
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} \
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if (UNLIKELY(mask & (2 << i))) { \
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value = cpu->gprs[i + 1]; \
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STM; \
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++wait; \
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address += 4; \
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} \
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if (UNLIKELY(mask & (4 << i))) { \
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value = cpu->gprs[i + 2]; \
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STM; \
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++wait; \
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address += 4; \
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} \
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if (UNLIKELY(mask & (8 << i))) { \
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value = cpu->gprs[i + 3]; \
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STM; \
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++wait; \
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address += 4; \
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} \
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}
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static uint32_t _deadbeef[1] = { 0xE710B710 }; // Illegal instruction on both ARM and Thumb
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static void DS7SetActiveRegion(struct ARMCore* cpu, uint32_t region);
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static void DS9SetActiveRegion(struct ARMCore* cpu, uint32_t region);
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static int32_t DSMemoryStall(struct ARMCore* cpu, int32_t wait);
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static const int DMA_OFFSET[] = { 1, -1, 0, 1 };
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void DSMemoryInit(struct DS* ds) {
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struct ARMCore* arm7 = ds->arm7;
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arm7->memory.load32 = DS7Load32;
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arm7->memory.load16 = DS7Load16;
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arm7->memory.load8 = DS7Load8;
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arm7->memory.loadMultiple = DS7LoadMultiple;
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arm7->memory.store32 = DS7Store32;
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arm7->memory.store16 = DS7Store16;
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arm7->memory.store8 = DS7Store8;
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arm7->memory.storeMultiple = DS7StoreMultiple;
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arm7->memory.stall = DSMemoryStall;
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struct ARMCore* arm9 = ds->arm9;
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arm9->memory.load32 = DS9Load32;
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arm9->memory.load16 = DS9Load16;
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arm9->memory.load8 = DS9Load8;
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arm9->memory.loadMultiple = DS9LoadMultiple;
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arm9->memory.store32 = DS9Store32;
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arm9->memory.store16 = DS9Store16;
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arm9->memory.store8 = DS9Store8;
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arm9->memory.storeMultiple = DS9StoreMultiple;
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arm9->memory.stall = DSMemoryStall;
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ds->memory.bios7 = NULL;
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ds->memory.bios9 = NULL;
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ds->memory.wram = NULL;
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ds->memory.ram = NULL;
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ds->memory.rom = NULL;
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ds->memory.activeRegion7 = -1;
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ds->memory.activeRegion9 = -1;
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arm7->memory.activeRegion = 0;
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arm7->memory.activeMask = 0;
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arm7->memory.setActiveRegion = DS7SetActiveRegion;
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arm7->memory.activeSeqCycles32 = 0;
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arm7->memory.activeSeqCycles16 = 0;
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arm7->memory.activeNonseqCycles32 = 0;
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arm7->memory.activeNonseqCycles16 = 0;
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arm9->memory.activeRegion = 0;
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arm9->memory.activeMask = 0;
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arm9->memory.setActiveRegion = DS9SetActiveRegion;
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arm9->memory.activeSeqCycles32 = 0;
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arm9->memory.activeSeqCycles16 = 0;
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arm9->memory.activeNonseqCycles32 = 0;
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arm9->memory.activeNonseqCycles16 = 0;
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}
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void DSMemoryDeinit(struct DS* ds) {
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mappedMemoryFree(ds->memory.wram, DS_SIZE_WORKING_RAM);
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mappedMemoryFree(ds->memory.ram, DS_SIZE_RAM);
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}
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void DSMemoryReset(struct DS* ds) {
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if (ds->memory.wram) {
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mappedMemoryFree(ds->memory.wram, DS_SIZE_WORKING_RAM);
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}
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ds->memory.wram = anonymousMemoryMap(DS_SIZE_WORKING_RAM);
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if (ds->memory.ram) {
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mappedMemoryFree(ds->memory.ram, DS_SIZE_RAM);
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}
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ds->memory.ram = anonymousMemoryMap(DS_SIZE_RAM);
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memset(ds->memory.dma7, 0, sizeof(ds->memory.dma7));
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memset(ds->memory.dma9, 0, sizeof(ds->memory.dma9));
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ds->memory.activeDMA7 = -1;
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ds->memory.activeDMA9 = -1;
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ds->memory.nextDMA = INT_MAX;
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ds->memory.eventDiff = 0;
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if (!ds->memory.wram || !ds->memory.ram) {
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DSMemoryDeinit(ds);
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mLOG(DS_MEM, FATAL, "Could not map memory");
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}
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}
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static void DS7SetActiveRegion(struct ARMCore* cpu, uint32_t address) {
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struct DS* ds = (struct DS*) cpu->master;
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struct DSMemory* memory = &ds->memory;
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int newRegion = address >> DS_BASE_OFFSET;
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memory->activeRegion7 = newRegion;
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switch (newRegion) {
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case DS7_REGION_BIOS:
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cpu->memory.activeRegion = memory->bios7;
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cpu->memory.activeMask = DS7_SIZE_BIOS - 1;
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break;
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default:
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mLOG(DS_MEM, FATAL, "Jumped to invalid address: %08X", address);
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return;
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}
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}
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uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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struct DS* ds = (struct DS*) cpu->master;
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struct DSMemory* memory = &ds->memory;
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uint32_t value = 0;
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int wait = 0;
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switch (address >> DS_BASE_OFFSET) {
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default:
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break;
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}
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if (cycleCounter) {
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wait += 2;
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*cycleCounter += wait;
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}
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// Unaligned 32-bit loads are "rotated" so they make some semblance of sense
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int rotate = (address & 3) << 3;
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return ROR(value, rotate);
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}
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uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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struct DS* ds = (struct DS*) cpu->master;
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struct DSMemory* memory = &ds->memory;
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uint32_t value = 0;
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int wait = 0;
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switch (address >> DS_BASE_OFFSET) {
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default:
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break;
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}
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if (cycleCounter) {
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wait += 2;
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*cycleCounter += wait;
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}
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// Unaligned 16-bit loads are "unpredictable", TODO: See what DS does
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int rotate = (address & 1) << 3;
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return ROR(value, rotate);
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}
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uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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struct DS* ds = (struct DS*) cpu->master;
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struct DSMemory* memory = &ds->memory;
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uint32_t value = 0;
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int wait = 0;
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switch (address >> DS_BASE_OFFSET) {
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default:
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break;
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}
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if (cycleCounter) {
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wait += 2;
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*cycleCounter += wait;
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}
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return value;
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}
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void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
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struct DS* ds = (struct DS*) cpu->master;
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struct DSMemory* memory = &ds->memory;
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int wait = 0;
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switch (address >> DS_BASE_OFFSET) {
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break;
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}
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if (cycleCounter) {
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++wait;
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*cycleCounter += wait;
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}
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}
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void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
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struct DS* ds = (struct DS*) cpu->master;
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struct DSMemory* memory = &ds->memory;
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int wait = 0;
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switch (address >> DS_BASE_OFFSET) {
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default:
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break;
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}
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if (cycleCounter) {
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++wait;
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*cycleCounter += wait;
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}
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}
|
||||
|
||||
void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
++wait;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t DS7LoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value;
|
||||
int wait = 0;
|
||||
|
||||
int i;
|
||||
int offset = 4;
|
||||
int popcount = 0;
|
||||
if (direction & LSM_D) {
|
||||
offset = -4;
|
||||
popcount = popcount32(mask);
|
||||
address -= (popcount << 2) - 4;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
uint32_t addressMisalign = address & 0x3;
|
||||
address &= 0xFFFFFFFC;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
++wait;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address -= offset;
|
||||
}
|
||||
|
||||
if (direction & LSM_D) {
|
||||
address -= (popcount << 2) + 4;
|
||||
}
|
||||
|
||||
return address | addressMisalign;
|
||||
}
|
||||
|
||||
|
||||
uint32_t DS7StoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
|
||||
struct DS* ds = (struct ds*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value;
|
||||
int wait = 0;
|
||||
|
||||
int i;
|
||||
int offset = 4;
|
||||
int popcount = 0;
|
||||
if (direction & LSM_D) {
|
||||
offset = -4;
|
||||
popcount = popcount32(mask);
|
||||
address -= (popcount << 2) - 4;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
uint32_t addressMisalign = address & 0x3;
|
||||
address &= 0xFFFFFFFC;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address -= offset;
|
||||
}
|
||||
|
||||
if (direction & LSM_D) {
|
||||
address -= (popcount << 2) + 4;
|
||||
}
|
||||
|
||||
return address | addressMisalign;
|
||||
}
|
||||
|
||||
static void DS9SetActiveRegion(struct ARMCore* cpu, uint32_t address) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
|
||||
int newRegion = address >> DS_BASE_OFFSET;
|
||||
|
||||
memory->activeRegion7 = newRegion;
|
||||
switch (newRegion) {
|
||||
case DS9_REGION_BIOS:
|
||||
// TODO: Mask properly
|
||||
if (memory->bios9) {
|
||||
cpu->memory.activeRegion = memory->bios9;
|
||||
cpu->memory.activeMask = DS9_SIZE_BIOS - 1;
|
||||
} else {
|
||||
cpu->memory.activeRegion = _deadbeef;
|
||||
cpu->memory.activeMask = 0;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
mLOG(DS_MEM, FATAL, "Jumped to invalid address: %08X", address);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value = 0;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
wait += 2;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
// Unaligned 32-bit loads are "rotated" so they make some semblance of sense
|
||||
int rotate = (address & 3) << 3;
|
||||
return ROR(value, rotate);
|
||||
}
|
||||
|
||||
uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value = 0;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
wait += 2;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
// Unaligned 16-bit loads are "unpredictable", TODO: See what DS does
|
||||
int rotate = (address & 1) << 3;
|
||||
return ROR(value, rotate);
|
||||
}
|
||||
|
||||
uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value = 0;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
wait += 2;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
return value;
|
||||
}
|
||||
|
||||
void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
++wait;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
}
|
||||
|
||||
void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
++wait;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
}
|
||||
|
||||
void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
int wait = 0;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
++wait;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t DS9LoadMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
|
||||
struct DS* ds = (struct DS*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value;
|
||||
int wait = 0;
|
||||
|
||||
int i;
|
||||
int offset = 4;
|
||||
int popcount = 0;
|
||||
if (direction & LSM_D) {
|
||||
offset = -4;
|
||||
popcount = popcount32(mask);
|
||||
address -= (popcount << 2) - 4;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
uint32_t addressMisalign = address & 0x3;
|
||||
address &= 0xFFFFFFFC;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
++wait;
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address -= offset;
|
||||
}
|
||||
|
||||
if (direction & LSM_D) {
|
||||
address -= (popcount << 2) + 4;
|
||||
}
|
||||
|
||||
return address | addressMisalign;
|
||||
}
|
||||
|
||||
|
||||
uint32_t DS9StoreMultiple(struct ARMCore* cpu, uint32_t address, int mask, enum LSMDirection direction, int* cycleCounter) {
|
||||
struct DS* ds = (struct ds*) cpu->master;
|
||||
struct DSMemory* memory = &ds->memory;
|
||||
uint32_t value;
|
||||
int wait = 0;
|
||||
|
||||
int i;
|
||||
int offset = 4;
|
||||
int popcount = 0;
|
||||
if (direction & LSM_D) {
|
||||
offset = -4;
|
||||
popcount = popcount32(mask);
|
||||
address -= (popcount << 2) - 4;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address += offset;
|
||||
}
|
||||
|
||||
uint32_t addressMisalign = address & 0x3;
|
||||
address &= 0xFFFFFFFC;
|
||||
|
||||
switch (address >> DS_BASE_OFFSET) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cycleCounter) {
|
||||
*cycleCounter += wait;
|
||||
}
|
||||
|
||||
if (direction & LSM_B) {
|
||||
address -= offset;
|
||||
}
|
||||
|
||||
if (direction & LSM_D) {
|
||||
address -= (popcount << 2) + 4;
|
||||
}
|
||||
|
||||
return address | addressMisalign;
|
||||
}
|
||||
|
||||
int32_t DSMemoryStall(struct ARMCore* cpu, int32_t wait) {
|
||||
return wait;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/* Copyright (c) 2013-2016 Jeffrey Pfau
|
||||
*
|
||||
* This Source Code Form is subject to the terms of the Mozilla Public
|
||||
* License, v. 2.0. If a copy of the MPL was not distributed with this
|
||||
* file, You can obtain one at http://mozilla.org/MPL/2.0/. */
|
||||
#ifndef DS_MEMORY_H
|
||||
#define DS_MEMORY_H
|
||||
|
||||
#include "util/common.h"
|
||||
|
||||
#include "arm/arm.h"
|
||||
#include "core/log.h"
|
||||
|
||||
enum DSMemoryRegion {
|
||||
DS7_REGION_BIOS = 0x0,
|
||||
DS9_REGION_ITCM = 0x0,
|
||||
DS_REGION_RAM = 0x2,
|
||||
DS_REGION_WORKING_RAM = 0x3,
|
||||
DS_REGION_IO = 0x4,
|
||||
DS9_REGION_PALETTE_RAM = 0x5,
|
||||
DS_REGION_VRAM = 0x6,
|
||||
DS9_REGION_OAM = 0x7,
|
||||
DS_REGION_SLOT2 = 0x8,
|
||||
DS_REGION_SLOT2_EX = 0x9,
|
||||
DS_REGION_SLOT2_SRAM = 0xA,
|
||||
DS9_REGION_BIOS = 0xFF,
|
||||
};
|
||||
|
||||
enum DSMemoryBase {
|
||||
DS7_BASE_BIOS = 0x00000000,
|
||||
DS9_BASE_ITCM = 0x00000000,
|
||||
DS_BASE_RAM = 0x02000000,
|
||||
DS_BASE_WORKING_RAM = 0x03000000,
|
||||
DS_BASE_IO = 0x04000000,
|
||||
DS9_BASE_PALETTE_RAM = 0x05000000,
|
||||
DS_BASE_VRAM = 0x06000000,
|
||||
DS9_BASE_OAM = 0x07000000,
|
||||
DS_BASE_SLOT2 = 0x08000000,
|
||||
DS_BASE_SLOT2_EX = 0x09000000,
|
||||
DS9_BASE_BIOS = 0xFFFF0000,
|
||||
};
|
||||
|
||||
enum {
|
||||
DS7_SIZE_BIOS = 0x00004000,
|
||||
DS9_SIZE_BIOS = 0x00008000,
|
||||
DS_SIZE_RAM = 0x00400000,
|
||||
DS_SIZE_WORKING_RAM = 0x00008000,
|
||||
DS9_SIZE_PALETTE_RAM = 0x00000800,
|
||||
DS9_SIZE_OAM = 0x00000800,
|
||||
DS_SIZE_SLOT2 = 0x02000000,
|
||||
DS_SIZE_SLOT2_SRAM = 0x00010000,
|
||||
};
|
||||
|
||||
enum {
|
||||
DS_OFFSET_MASK = 0x00FFFFFF,
|
||||
DS_BASE_OFFSET = 24
|
||||
};
|
||||
|
||||
enum DSDMAControl {
|
||||
DS_DMA_INCREMENT = 0,
|
||||
DS_DMA_DECREMENT = 1,
|
||||
DS_DMA_FIXED = 2,
|
||||
DS_DMA_INCREMENT_RELOAD = 3
|
||||
};
|
||||
|
||||
enum DSDMATiming {
|
||||
DS_DMA_TIMING_NOW = 0,
|
||||
DS_DMA_TIMING_VBLANK = 1,
|
||||
DS_DMA_TIMING_HBLANK = 2,
|
||||
DS7_DMA_TIMING_SLOT1 = 2,
|
||||
DS_DMA_TIMING_DISPLAY_START = 3,
|
||||
DS7_DMA_TIMING_CUSTOM = 3,
|
||||
DS_DMA_TIMING_MEMORY_DISPLAY = 4,
|
||||
DS9_DMA_TIMING_SLOT1 = 5,
|
||||
DS_DMA_TIMING_SLOT2 = 6,
|
||||
DS_DMA_TIMING_GEOM_FIFO = 7,
|
||||
};
|
||||
|
||||
mLOG_DECLARE_CATEGORY(DS_MEM);
|
||||
|
||||
DECL_BITFIELD(DSDMARegister, uint16_t);
|
||||
DECL_BITS(DSDMARegister, DestControl, 5, 2);
|
||||
DECL_BITS(DSDMARegister, SrcControl, 7, 2);
|
||||
DECL_BIT(DSDMARegister, Repeat, 9);
|
||||
DECL_BIT(DSDMARegister, Width, 10);
|
||||
DECL_BITS(DSDMARegister, Timing7, 12, 2);
|
||||
DECL_BITS(DSDMARegister, Timing9, 11, 3);
|
||||
DECL_BIT(DSDMARegister, DoIRQ, 14);
|
||||
DECL_BIT(DSDMARegister, Enable, 15);
|
||||
|
||||
struct DSDMA {
|
||||
DSDMARegister reg;
|
||||
|
||||
uint32_t source;
|
||||
uint32_t dest;
|
||||
int32_t count;
|
||||
uint32_t nextSource;
|
||||
uint32_t nextDest;
|
||||
int32_t nextCount;
|
||||
int32_t nextEvent;
|
||||
};
|
||||
|
||||
struct DSMemory {
|
||||
uint32_t* bios7;
|
||||
uint32_t* bios9;
|
||||
uint32_t* ram;
|
||||
uint32_t* wram;
|
||||
uint32_t* rom;
|
||||
|
||||
size_t romSize;
|
||||
|
||||
char waitstatesSeq32[256];
|
||||
char waitstatesSeq16[256];
|
||||
char waitstatesNonseq32[256];
|
||||
char waitstatesNonseq16[256];
|
||||
char waitstatesPrefetchSeq32[16];
|
||||
char waitstatesPrefetchSeq16[16];
|
||||
char waitstatesPrefetchNonseq32[16];
|
||||
char waitstatesPrefetchNonseq16[16];
|
||||
int activeRegion7;
|
||||
int activeRegion9;
|
||||
|
||||
struct DSDMA dma7[4];
|
||||
struct DSDMA dma9[4];
|
||||
int activeDMA7;
|
||||
int activeDMA9;
|
||||
int32_t nextDMA;
|
||||
int32_t eventDiff;
|
||||
};
|
||||
|
||||
struct DS;
|
||||
void DSMemoryInit(struct DS* ds);
|
||||
void DSMemoryDeinit(struct DS* ds);
|
||||
|
||||
void DSMemoryReset(struct DS* ds);
|
||||
|
||||
uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
|
||||
uint32_t DS7Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
|
||||
uint32_t DS7Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
|
||||
|
||||
void DS7Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
|
||||
void DS7Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
|
||||
void DS7Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
|
||||
|
||||
uint32_t DS7LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
|
||||
int* cycleCounter);
|
||||
uint32_t DS7StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
|
||||
int* cycleCounter);
|
||||
|
||||
uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
|
||||
uint32_t DS9Load16(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
|
||||
uint32_t DS9Load8(struct ARMCore* cpu, uint32_t address, int* cycleCounter);
|
||||
|
||||
void DS9Store32(struct ARMCore* cpu, uint32_t address, int32_t value, int* cycleCounter);
|
||||
void DS9Store16(struct ARMCore* cpu, uint32_t address, int16_t value, int* cycleCounter);
|
||||
void DS9Store8(struct ARMCore* cpu, uint32_t address, int8_t value, int* cycleCounter);
|
||||
|
||||
uint32_t DS9LoadMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
|
||||
int* cycleCounter);
|
||||
uint32_t DS9StoreMultiple(struct ARMCore*, uint32_t baseAddress, int mask, enum LSMDirection direction,
|
||||
int* cycleCounter);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue