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ARM: Reduce size of ARM condition prediction

This commit is contained in:
Jeffrey Pfau 2014-11-16 21:05:06 -08:00
parent 845d6e1d24
commit 3c41bd2427
1 changed files with 19 additions and 56 deletions
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75
src/arm/arm.c
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@ -177,94 +177,57 @@ static inline void ARMStep(struct ARMCore* cpu) {
unsigned condition = opcode >> 28; unsigned condition = opcode >> 28;
if (condition != 0xE) { if (condition != 0xE) {
bool conditionMet = false;
switch (condition) { switch (condition) {
case 0x0: case 0x0:
if (!ARM_COND_EQ) { conditionMet = ARM_COND_EQ;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x1: case 0x1:
if (!ARM_COND_NE) { conditionMet = ARM_COND_NE;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x2: case 0x2:
if (!ARM_COND_CS) { conditionMet = ARM_COND_CS;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x3: case 0x3:
if (!ARM_COND_CC) { conditionMet = ARM_COND_CC;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x4: case 0x4:
if (!ARM_COND_MI) { conditionMet = ARM_COND_MI;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x5: case 0x5:
if (!ARM_COND_PL) { conditionMet = ARM_COND_PL;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x6: case 0x6:
if (!ARM_COND_VS) { conditionMet = ARM_COND_VS;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x7: case 0x7:
if (!ARM_COND_VC) { conditionMet = ARM_COND_VC;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x8: case 0x8:
if (!ARM_COND_HI) { conditionMet = ARM_COND_HI;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0x9: case 0x9:
if (!ARM_COND_LS) { conditionMet = ARM_COND_LS;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0xA: case 0xA:
if (!ARM_COND_GE) { conditionMet = ARM_COND_GE;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0xB: case 0xB:
if (!ARM_COND_LT) { conditionMet = ARM_COND_LT;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0xC: case 0xC:
if (!ARM_COND_GT) { conditionMet = ARM_COND_GT;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
case 0xD: case 0xD:
if (!ARM_COND_LE) { conditionMet = ARM_COND_LE;
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
break; break;
default: default:
break; break;
} }
if (!conditionMet) {
cpu->cycles += ARM_PREFETCH_CYCLES;
return;
}
} }
ARMInstruction instruction = _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)]; ARMInstruction instruction = _armTable[((opcode >> 16) & 0xFF0) | ((opcode >> 4) & 0x00F)];
instruction(cpu, opcode); instruction(cpu, opcode);