mirror of https://github.com/mgba-emu/mgba.git
DS IPC: Implement IPC read
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@ -282,12 +282,14 @@ void DS7IOWrite(struct DS* ds, uint32_t address, uint16_t value);
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void DS7IOWrite8(struct DS* ds, uint32_t address, uint8_t value);
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void DS7IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
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uint16_t DS7IORead(struct DS* ds, uint32_t address);
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uint32_t DS7IORead32(struct DS* ds, uint32_t address);
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void DS9IOInit(struct DS* ds);
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void DS9IOWrite(struct DS* ds, uint32_t address, uint16_t value);
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void DS9IOWrite8(struct DS* ds, uint32_t address, uint8_t value);
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void DS9IOWrite32(struct DS* ds, uint32_t address, uint32_t value);
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uint16_t DS9IORead(struct DS* ds, uint32_t address);
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uint32_t DS9IORead32(struct DS* ds, uint32_t address);
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CXX_GUARD_END
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20
src/ds/io.c
20
src/ds/io.c
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@ -207,6 +207,7 @@ uint16_t DS7IORead(struct DS* ds, uint32_t address) {
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case DS_REG_TM2CNT_HI:
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case DS_REG_TM3CNT_HI:
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case DS_REG_IPCSYNC:
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case DS_REG_IPCFIFOCNT:
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case DS_REG_IME:
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case DS_REG_IE_LO:
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case DS_REG_IE_HI:
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@ -223,6 +224,15 @@ uint16_t DS7IORead(struct DS* ds, uint32_t address) {
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return 0;
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}
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uint32_t DS7IORead32(struct DS* ds, uint32_t address) {
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switch (address) {
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case DS_REG_IPCFIFORECV_LO:
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return DSIPCReadFIFO(&ds->ds7);
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default:
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return DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
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}
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}
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void DS9IOInit(struct DS* ds) {
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memset(ds->memory.io9, 0, sizeof(ds->memory.io9));
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}
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@ -328,6 +338,7 @@ uint16_t DS9IORead(struct DS* ds, uint32_t address) {
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case DS_REG_TM2CNT_HI:
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case DS_REG_TM3CNT_HI:
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case DS_REG_IPCSYNC:
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case DS_REG_IPCFIFOCNT:
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case DS_REG_IME:
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case DS_REG_IE_LO:
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case DS_REG_IE_HI:
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@ -343,3 +354,12 @@ uint16_t DS9IORead(struct DS* ds, uint32_t address) {
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}
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return 0;
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}
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uint32_t DS9IORead32(struct DS* ds, uint32_t address) {
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switch (address) {
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case DS_REG_IPCFIFORECV_LO:
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return DSIPCReadFIFO(&ds->ds9);
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default:
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return DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
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}
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}
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20
src/ds/ipc.c
20
src/ds/ipc.c
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@ -48,3 +48,23 @@ void DSIPCWriteFIFO(struct DSCommon* dscore, int32_t value) {
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dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1] = DSIPCFIFOCNTFillRecvFull(dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1]);
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}
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}
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int32_t DSIPCReadFIFO(struct DSCommon* dscore) {
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if (!DSIPCFIFOCNTIsEnable(dscore->memory.io[DS_REG_IPCFIFOCNT >> 1])) {
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return 0;
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}
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int32_t value = ((int32_t*) dscore->ipc->memory.io)[DS_REG_IPCFIFOSEND_LO >> 2]; // TODO: actual last value
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CircleBufferRead32(&dscore->fifo, &value);
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size_t fullness = CircleBufferSize(&dscore->fifo);
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dscore->memory.io[DS_REG_IPCFIFOCNT >> 1] = DSIPCFIFOCNTClearRecvFull(dscore->memory.io[DS_REG_IPCFIFOCNT >> 1]);
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dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1] = DSIPCFIFOCNTClearSendFull(dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1]);
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if (fullness == 0) {
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dscore->memory.io[DS_REG_IPCFIFOCNT >> 1] = DSIPCFIFOCNTFillRecvEmpty(dscore->memory.io[DS_REG_IPCFIFOCNT >> 1]);
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dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1] = DSIPCFIFOCNTFillSendEmpty(dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1]);
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if (DSIPCFIFOCNTIsSendIRQ(dscore->ipc->memory.io[DS_REG_IPCFIFOCNT >> 1])) {
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// TODO: Adaptive time slicing?
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DSRaiseIRQ(dscore->ipc->cpu, dscore->ipc->memory.io, DS_IRQ_IPC_NOT_EMPTY);
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}
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}
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return value;
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}
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@ -237,7 +237,7 @@ uint32_t DS7Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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mLOG(DS_MEM, STUB, "Unimplemented DS7 Load32: %08X", address);
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break;
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case DS_REGION_IO:
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value = DS7IORead(ds, address & 0x00FFFFFC) | (DS7IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
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value = DS7IORead32(ds, address & 0x00FFFFFC);
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break;
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default:
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mLOG(DS_MEM, STUB, "Unimplemented DS7 Load32: %08X", address);
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@ -681,7 +681,7 @@ uint32_t DS9Load32(struct ARMCore* cpu, uint32_t address, int* cycleCounter) {
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mLOG(DS_MEM, STUB, "Unimplemented DS9 Load32: %08X", address);
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break;
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case DS_REGION_IO:
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value = DS9IORead(ds, address & 0x00FFFFFC) | (DS9IORead(ds, (address & 0x00FFFFFC) | 2) << 16);
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value = DS9IORead32(ds, address & 0x00FFFFFC);
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break;
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case DS9_REGION_BIOS:
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// TODO: Fix undersized BIOS
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