diff --git a/CHANGES b/CHANGES
index b7daf5539..4799884aa 100644
--- a/CHANGES
+++ b/CHANGES
@@ -1,5 +1,6 @@
 0.9.1: (Future)
 Emulation fixes:
+ - ARM: Fix LDM^ with empty rlist (fixes mgba.io/i/2127)
  - Core: Fix first event scheduling after loading savestate
  - GB Serialize: Fix switching speed modes when loading a state (fixes mgba.io/i/2097)
  - GB: Fix skipping BIOS
diff --git a/src/arm/isa-arm.c b/src/arm/isa-arm.c
index 56dcca987..c573cdbbd 100644
--- a/src/arm/isa-arm.c
+++ b/src/arm/isa-arm.c
@@ -421,7 +421,7 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
 
 #define ARM_MS_PRE_load \
 	enum PrivilegeMode privilegeMode; \
-	if (!(rs & 0x8000)) { \
+	if (!(rs & 0x8000) && rs) { \
 		privilegeMode = cpu->privilegeMode; \
 		ARMSetPrivilegeMode(cpu, MODE_SYSTEM); \
 	}
@@ -429,7 +429,7 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
 #define ARM_MS_POST_store ARMSetPrivilegeMode(cpu, privilegeMode);
 
 #define ARM_MS_POST_load \
-	if (!(rs & 0x8000)) { \
+	if (!(rs & 0x8000) && rs) { \
 		ARMSetPrivilegeMode(cpu, privilegeMode); \
 	} else if (_ARMModeHasSPSR(cpu->cpsr.priv)) { \
 		cpu->cpsr = cpu->spsr; \