From 337d4dc1e658e4efd6c111a05248a7116e0020b2 Mon Sep 17 00:00:00 2001
From: Jeffrey Pfau <jeffrey@endrift.com>
Date: Tue, 30 Apr 2013 01:57:36 -0700
Subject: [PATCH] Implement addressing mode 1 ROR with register

---
 src/arm/isa-arm.c | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/src/arm/isa-arm.c b/src/arm/isa-arm.c
index 196bf4453..2e141e535 100644
--- a/src/arm/isa-arm.c
+++ b/src/arm/isa-arm.c
@@ -76,7 +76,28 @@ static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
 
 static inline void _shiftRORR(struct ARMCore* cpu, uint32_t opcode) {
 	int rm = opcode & 0x0000000F;
-	ARM_STUB;
+	int rs = (opcode >> 8) & 0x0000000F;
+	++cpu->cycles;
+	int shift = cpu->gprs[rs];
+	if (rs == ARM_PC) {
+		shift += 4;
+	}
+	shift &= 0xFF;
+	int shiftVal =  cpu->gprs[rm];
+	if (rm == ARM_PC) {
+		shiftVal += 4;
+	}
+	int rotate = shift & 0x1F;
+	if (!shift) {
+		cpu->shifterOperand = shiftVal;
+		cpu->shifterCarryOut = cpu->cpsr.c;
+	} else if (rotate) {
+		cpu->shifterOperand = ARM_ROR(shiftVal, rotate);
+		cpu->shifterCarryOut = (shiftVal >> (rotate - 1)) & 1;
+	} else {
+		cpu->shifterOperand = shiftVal;
+		cpu->shifterCarryOut = ARM_SIGN(shiftVal);
+	}
 }
 
 static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {