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Revert "Revert "GBA Memory: Improve gamepak prefetch timing""
This reverts commit 95e1dd9c35
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@ -4,6 +4,7 @@ Emulation fixes:
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- ARM: Fix STR storing PC after address calculation
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- GBA DMA: Linger last DMA on bus (fixes mgba.io/i/301 and mgba.io/i/1320)
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- GBA Memory: Misaligned SRAM writes are ignored
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- GBA Memory: Improve gamepak prefetch timing
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- GBA Serialize: Fix serializing DMA transfer register
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- GBA Serialize: Fix audio serialization for desynced FIFOs
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- GBA Serialize: Fix audio DMA timing deserialization
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@ -1626,17 +1626,19 @@ int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
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maxLoads -= previousLoads;
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}
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int32_t s = cpu->memory.activeSeqCycles16 + 1;
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int32_t s = cpu->memory.activeSeqCycles16;
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int32_t n2s = cpu->memory.activeNonseqCycles16 - cpu->memory.activeSeqCycles16 + 1;
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// Figure out how many sequential loads we can jam in
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int32_t stall = s;
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int32_t stall = s + 1;
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int32_t loads = 1;
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while (stall < wait && loads < maxLoads) {
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stall += s;
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++loads;
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}
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memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * (loads + previousLoads - 1);
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if (stall > wait) {
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// The wait cannot take less time than the prefetch stalls
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wait = stall;
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@ -1645,10 +1647,9 @@ int32_t GBAMemoryStall(struct ARMCore* cpu, int32_t wait) {
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// This instruction used to have an N, convert it to an S.
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wait -= n2s;
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memory->lastPrefetchedPc = cpu->gprs[ARM_PC] + WORD_SIZE_THUMB * (loads + previousLoads - 1);
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// The next |loads|S waitstates disappear entirely, so long as they're all in a row
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cpu->cycles -= (s - 1) * loads;
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wait -= stall - 1;
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return wait;
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}
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