mirror of https://github.com/mgba-emu/mgba.git
ARM: Shuffle around inlining in ARM core
This commit is contained in:
Vicki Pfau
parent
870c2f8bab
commit
2983c83c38
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@ -14,7 +14,7 @@
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#define PSR_STATE_MASK 0x00000020
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// Addressing mode 1
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static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
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static void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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@ -49,7 +49,7 @@ static inline void _shiftLSL(struct ARMCore* cpu, uint32_t opcode) {
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}
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}
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static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
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static void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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@ -84,7 +84,7 @@ static inline void _shiftLSR(struct ARMCore* cpu, uint32_t opcode) {
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}
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}
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static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
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static void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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@ -119,7 +119,7 @@ static inline void _shiftASR(struct ARMCore* cpu, uint32_t opcode) {
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}
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}
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static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
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static void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
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int rm = opcode & 0x0000000F;
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if (opcode & 0x00000010) {
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int rs = (opcode >> 8) & 0x0000000F;
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@ -153,7 +153,7 @@ static inline void _shiftROR(struct ARMCore* cpu, uint32_t opcode) {
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}
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}
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static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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static void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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int rotate = (opcode & 0x00000F00) >> 7;
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int immediate = opcode & 0x000000FF;
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if (!rotate) {
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@ -168,62 +168,54 @@ static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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// Instruction definitions
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// Beware pre-processor antics
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ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
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ATTRIBUTE_NOINLINE static void _additionS(struct ARMCore* cpu, int rd, int32_t m, int32_t n, int32_t d) {
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) {
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cpu->cpsr = cpu->spsr;
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_ARMReadCPSR(cpu);
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} else {
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cpu->cpsr.flags = 0;
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !d;
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cpu->cpsr.c = ARM_CARRY_FROM(m, n, d);
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cpu->cpsr.v = ARM_V_ADDITION(m, n, d);
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}
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}
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ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int32_t m, int32_t n, int32_t d) {
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ATTRIBUTE_NOINLINE static void _subtractionS(struct ARMCore* cpu, int rd, int32_t m, int32_t n, int32_t d) {
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) {
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cpu->cpsr = cpu->spsr;
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_ARMReadCPSR(cpu);
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} else {
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cpu->cpsr.flags = 0;
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !d;
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cpu->cpsr.c = ARM_BORROW_FROM(m, n, d);
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cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
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}
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}
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ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
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ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int rd, int32_t d) {
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) {
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cpu->cpsr = cpu->spsr;
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_ARMReadCPSR(cpu);
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} else {
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !d; \
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cpu->cpsr.c = cpu->shifterCarryOut; \
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cpu->cpsr.z = !d;
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cpu->cpsr.c = cpu->shifterCarryOut;
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}
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}
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#define ARM_ADDITION_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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_additionS(cpu, M, N, D); \
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}
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#define ARM_SUBTRACTION_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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_subtractionS(cpu, M, N, D); \
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}
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#define ARM_SUBTRACTION_CARRY_S(M, N, D, C) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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cpu->cpsr.n = ARM_SIGN(D); \
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cpu->cpsr.z = !(D); \
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cpu->cpsr.c = ARM_BORROW_FROM_CARRY(M, N, D, C); \
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cpu->cpsr.v = ARM_V_SUBTRACTION(M, N, D); \
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}
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#define ARM_NEUTRAL_S(M, N, D) \
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) { \
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cpu->cpsr = cpu->spsr; \
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_ARMReadCPSR(cpu); \
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} else { \
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_neutralS(cpu, D); \
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ATTRIBUTE_NOINLINE static void _subtractionCarryS(struct ARMCore* cpu, int rd, int32_t m, int32_t n, int32_t d, int32_t c) {
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if (rd == ARM_PC && _ARMModeHasSPSR(cpu->cpsr.priv)) {
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cpu->cpsr = cpu->spsr;
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_ARMReadCPSR(cpu);
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} else {
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cpu->cpsr.n = ARM_SIGN(d);
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cpu->cpsr.z = !(d);
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cpu->cpsr.c = ARM_BORROW_FROM_CARRY(m, n, d, c);
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cpu->cpsr.v = ARM_V_SUBTRACTION(m, n, d);
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}
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}
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#define ARM_NEUTRAL_HI_S(DLO, DHI) \
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cpu->cpsr.n = ARM_SIGN(DHI); \
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@ -468,60 +460,60 @@ ATTRIBUTE_NOINLINE static void _neutralS(struct ARMCore* cpu, int32_t d) {
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// Begin ALU definitions
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DEFINE_ALU_INSTRUCTION_ARM(ADD, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(ADD, _additionS(cpu, rd, n, cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = n + cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(ADC, ARM_ADDITION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(ADC, _additionS(cpu, rd, n, cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = n + cpu->shifterOperand + cpu->cpsr.c;)
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DEFINE_ALU_INSTRUCTION_ARM(AND, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(AND, _neutralS(cpu, rd, cpu->gprs[rd]),
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cpu->gprs[rd] = n & cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(BIC, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(BIC, _neutralS(cpu, rd, cpu->gprs[rd]),
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cpu->gprs[rd] = n & ~cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, ARM_ADDITION_S(n, cpu->shifterOperand, aluOut),
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMN, _additionS(cpu, rd, n, cpu->shifterOperand, aluOut),
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int32_t aluOut = n + cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, ARM_SUBTRACTION_S(n, cpu->shifterOperand, aluOut),
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(CMP, _subtractionS(cpu, rd, n, cpu->shifterOperand, aluOut),
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int32_t aluOut = n - cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(EOR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(EOR, _neutralS(cpu, rd, cpu->gprs[rd]),
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cpu->gprs[rd] = n ^ cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(MOV, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(MOV, _neutralS(cpu, rd, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(MVN, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(MVN, _neutralS(cpu, rd, cpu->gprs[rd]),
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cpu->gprs[rd] = ~cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(ORR, ARM_NEUTRAL_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(ORR, _neutralS(cpu, rd, cpu->gprs[rd]),
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cpu->gprs[rd] = n | cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_ARM(RSB, ARM_SUBTRACTION_S(cpu->shifterOperand, n, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(RSB, _subtractionS(cpu, rd, cpu->shifterOperand, n, cpu->gprs[rd]),
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cpu->gprs[rd] = cpu->shifterOperand - n;)
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DEFINE_ALU_INSTRUCTION_ARM(RSC, ARM_SUBTRACTION_CARRY_S(cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
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DEFINE_ALU_INSTRUCTION_ARM(RSC, _subtractionCarryS(cpu, rd, cpu->shifterOperand, n, cpu->gprs[rd], !cpu->cpsr.c),
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cpu->gprs[rd] = cpu->shifterOperand - n - !cpu->cpsr.c;)
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DEFINE_ALU_INSTRUCTION_ARM(SBC, ARM_SUBTRACTION_CARRY_S(n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
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DEFINE_ALU_INSTRUCTION_ARM(SBC, _subtractionCarryS(cpu, rd, n, cpu->shifterOperand, cpu->gprs[rd], !cpu->cpsr.c),
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cpu->gprs[rd] = n - cpu->shifterOperand - !cpu->cpsr.c;)
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DEFINE_ALU_INSTRUCTION_ARM(SUB, ARM_SUBTRACTION_S(n, cpu->shifterOperand, cpu->gprs[rd]),
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DEFINE_ALU_INSTRUCTION_ARM(SUB, _subtractionS(cpu, rd, n, cpu->shifterOperand, cpu->gprs[rd]),
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cpu->gprs[rd] = n - cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TEQ, _neutralS(cpu, -1, aluOut),
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int32_t aluOut = n ^ cpu->shifterOperand;)
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(n, cpu->shifterOperand, aluOut),
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DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, _neutralS(cpu, -1, aluOut),
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int32_t aluOut = n & cpu->shifterOperand;)
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// End ALU definitions
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// Begin multiply definitions
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), S, 1)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]), S)
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], _neutralS(cpu, -1, cpu->gprs[rdHi]), S, 1)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], _neutralS(cpu, -1, cpu->gprs[rd]), S)
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
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int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]) + ((uint32_t) cpu->gprs[rd]);
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