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Core: Fix cache writes that span multiple tiles

This commit is contained in:
Vicki Pfau 2022-06-27 21:10:16 -07:00
parent 99f067e539
commit 2969a8bf7a
4 changed files with 16 additions and 5 deletions
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1
include/mgba/core/map-cache.h
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@ -23,6 +23,7 @@ DECL_BITS(mMapCacheSystemInfo, TilesWide, 8, 4);
DECL_BITS(mMapCacheSystemInfo, TilesHigh, 12, 4); DECL_BITS(mMapCacheSystemInfo, TilesHigh, 12, 4);
DECL_BITS(mMapCacheSystemInfo, MacroTileSize, 16, 7); DECL_BITS(mMapCacheSystemInfo, MacroTileSize, 16, 7);
DECL_BITS(mMapCacheSystemInfo, MapAlign, 23, 2); DECL_BITS(mMapCacheSystemInfo, MapAlign, 23, 2);
DECL_BITS(mMapCacheSystemInfo, WriteAlign, 25, 2);
DECL_BITFIELD(mMapCacheEntryFlags, uint16_t); DECL_BITFIELD(mMapCacheEntryFlags, uint16_t);
DECL_BITS(mMapCacheEntryFlags, PaletteId, 0, 4); DECL_BITS(mMapCacheEntryFlags, PaletteId, 0, 4);

17
src/core/map-cache.c
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@ -70,11 +70,20 @@ void mMapCacheDeinit(struct mMapCache* cache) {
void mMapCacheWriteVRAM(struct mMapCache* cache, uint32_t address) { void mMapCacheWriteVRAM(struct mMapCache* cache, uint32_t address) {
if (address >= cache->mapStart && address < cache->mapStart + cache->mapSize) { if (address >= cache->mapStart && address < cache->mapStart + cache->mapSize) {
uint32_t align = 1 << (mMapCacheSystemInfoGetWriteAlign(cache->sysConfig) - mMapCacheSystemInfoGetMapAlign(cache->sysConfig));
address -= cache->mapStart; address -= cache->mapStart;
struct mMapCacheEntry* status = &cache->status[address >> mMapCacheSystemInfoGetMapAlign(cache->sysConfig)]; address >>= mMapCacheSystemInfoGetMapAlign(cache->sysConfig);
++status->vramVersion;
status->flags = mMapCacheEntryFlagsClearVramClean(status->flags); uint32_t i;
status->tileStatus[mMapCacheEntryFlagsGetPaletteId(status->flags)].vramClean = 0; for (i = 0; i < align; ++i) {
if (address + i >= (cache->mapSize >> mMapCacheSystemInfoGetMapAlign(cache->sysConfig))) {
break;
}
struct mMapCacheEntry* status = &cache->status[address + i];
++status->vramVersion;
status->flags = mMapCacheEntryFlagsClearVramClean(status->flags);
status->tileStatus[mMapCacheEntryFlagsGetPaletteId(status->flags)].vramClean = 0;
}
} }
} }

1
src/gb/renderers/cache-set.c
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@ -119,6 +119,7 @@ void GBVideoCacheWriteVideoRegister(struct mCacheSet* cache, uint16_t address, u
sysconfig = mMapCacheSystemInfoSetMacroTileSize(sysconfig, 5); sysconfig = mMapCacheSystemInfoSetMacroTileSize(sysconfig, 5);
sysconfig = mMapCacheSystemInfoSetPaletteBPP(sysconfig, 1); sysconfig = mMapCacheSystemInfoSetPaletteBPP(sysconfig, 1);
sysconfig = mMapCacheSystemInfoSetMapAlign(sysconfig, 0); sysconfig = mMapCacheSystemInfoSetMapAlign(sysconfig, 0);
sysconfig = mMapCacheSystemInfoSetWriteAlign(sysconfig, 0);
sysconfig = mMapCacheSystemInfoSetTilesHigh(sysconfig, 5); sysconfig = mMapCacheSystemInfoSetTilesHigh(sysconfig, 5);
sysconfig = mMapCacheSystemInfoSetTilesWide(sysconfig, 5); sysconfig = mMapCacheSystemInfoSetTilesWide(sysconfig, 5);
mMapCacheConfigureSystem(map, sysconfig); mMapCacheConfigureSystem(map, sysconfig);

2
src/gba/renderers/cache-set.c
View File

@ -160,7 +160,7 @@ static void GBAVideoCacheWriteBGCNT(struct mCacheSet* cache, size_t bg, uint16_t
int size = GBARegisterBGCNTGetSize(value); int size = GBARegisterBGCNTGetSize(value);
int tilesWide = 0; int tilesWide = 0;
int tilesHigh = 0; int tilesHigh = 0;
mMapCacheSystemInfo sysconfig = 0; mMapCacheSystemInfo sysconfig = mMapCacheSystemInfoSetWriteAlign(0, 1);
if (map->mapParser == mapParser0) { if (map->mapParser == mapParser0) {
map->tileCache = mTileCacheSetGetPointer(&cache->tiles, p); map->tileCache = mTileCacheSetGetPointer(&cache->tiles, p);
sysconfig = mMapCacheSystemInfoSetPaletteBPP(sysconfig, 2 + p); sysconfig = mMapCacheSystemInfoSetPaletteBPP(sysconfig, 2 + p);