GB: Fix IRQ disabling on the same T-cycle as an assert

This commit is contained in:
Vicki Pfau 2018-08-09 19:11:26 -07:00
parent 1fb4d2be4d
commit 25cda2d7b2
4 changed files with 9 additions and 6 deletions

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@ -45,6 +45,7 @@ Bugfixes:
- GBA Video: Improve sprite cycle counting (fixes mgba.io/i/1126)
- GB, GBA Savedata: Fix savestate loading overwriting saves on reset
- GBA Video: Make layer disabling work consistently
- GB: Fix IRQ disabling on the same T-cycle as an assert
Misc:
- GBA Timer: Use global cycles for timers
- GBA: Extend oddly-sized ROMs to full address space (fixes mgba.io/i/722)

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@ -1 +0,0 @@
fail: true

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@ -625,7 +625,11 @@ void GBUpdateIRQs(struct GB* gb) {
}
gb->cpu->halted = false;
if (!gb->memory.ime || gb->cpu->irqPending) {
if (!gb->memory.ime) {
gb->cpu->irqPending = false;
return;
}
if (gb->cpu->irqPending) {
return;
}
LR35902RaiseIRQ(gb->cpu);
@ -661,12 +665,11 @@ void GBProcessEvents(struct LR35902Core* cpu) {
void GBSetInterrupts(struct LR35902Core* cpu, bool enable) {
struct GB* gb = (struct GB*) cpu->master;
mTimingDeschedule(&gb->timing, &gb->eiPending);
if (!enable) {
gb->memory.ime = enable;
mTimingDeschedule(&gb->timing, &gb->eiPending);
gb->memory.ime = false;
GBUpdateIRQs(gb);
} else {
mTimingDeschedule(&gb->timing, &gb->eiPending);
mTimingSchedule(&gb->timing, &gb->eiPending, 4);
}
}

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@ -137,7 +137,7 @@ static void _LR35902Step(struct LR35902Core* cpu) {
}
void LR35902Tick(struct LR35902Core* cpu) {
if (cpu->cycles >= cpu->nextEvent) {
while (cpu->cycles >= cpu->nextEvent) {
cpu->irqh.processEvents(cpu);
}
_LR35902Step(cpu);