From c0120cd58608da068d1218796a02f2f3468608b0 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Thu, 4 Jul 2019 13:44:23 -0700 Subject: [PATCH 01/20] OpenGL: Fix 1.x interframe blending --- src/platform/opengl/gl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/platform/opengl/gl.c b/src/platform/opengl/gl.c index bb7afbc6f..8ac36ae91 100644 --- a/src/platform/opengl/gl.c +++ b/src/platform/opengl/gl.c @@ -117,7 +117,6 @@ void mGLContextDrawFrame(struct VideoBackend* v) { glMatrixMode(GL_MODELVIEW); glLoadIdentity(); if (v->interframeBlending) { - glEnable(GL_BLEND); glBlendFunc(GL_CONSTANT_ALPHA, GL_ONE_MINUS_CONSTANT_ALPHA); glBlendColor(1, 1, 1, 0.5); glBindTexture(GL_TEXTURE_2D, context->tex[context->activeTex ^ 1]); @@ -129,6 +128,7 @@ void mGLContextDrawFrame(struct VideoBackend* v) { glTexParameterf(GL_TEXTURE_2D, GL_TEXTURE_MAG_FILTER, GL_NEAREST); } glDrawArrays(GL_TRIANGLE_FAN, 0, 4); + glEnable(GL_BLEND); } glBindTexture(GL_TEXTURE_2D, context->tex[context->activeTex]); if (v->filter) { From ca8559549c2b77b5adb958557c3a6c9d6ebc5d47 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Thu, 4 Jul 2019 14:13:27 -0700 Subject: [PATCH 02/20] Qt: Fix GL display not updating while paused --- src/platform/qt/DisplayGL.cpp | 3 --- src/platform/qt/DisplayGL.h | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/platform/qt/DisplayGL.cpp b/src/platform/qt/DisplayGL.cpp index 94069c96d..06ff72f11 100644 --- a/src/platform/qt/DisplayGL.cpp +++ b/src/platform/qt/DisplayGL.cpp @@ -64,7 +64,6 @@ DisplayGL::DisplayGL(const QSurfaceFormat& format, QWidget* parent) } m_painter = new PainterGL(windowHandle(), m_gl, forceVersion); - setUpdatesEnabled(false); // Prevent paint events, which can cause race conditions } DisplayGL::~DisplayGL() { @@ -475,8 +474,6 @@ void PainterGL::swap() { } if (!m_queue.isEmpty()) { QMetaObject::invokeMethod(this, "draw", Qt::QueuedConnection); - } else { - m_swapTimer.start(); } } diff --git a/src/platform/qt/DisplayGL.h b/src/platform/qt/DisplayGL.h index 40cc05b77..88f18a58a 100644 --- a/src/platform/qt/DisplayGL.h +++ b/src/platform/qt/DisplayGL.h @@ -60,7 +60,7 @@ public slots: void resizeContext() override; protected: - virtual void paintEvent(QPaintEvent*) override {} + virtual void paintEvent(QPaintEvent*) override { forceDraw(); } virtual void resizeEvent(QResizeEvent*) override; private: From 916d14cd780a90cd8d712bb7932755c65b555b08 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Thu, 4 Jul 2019 14:18:30 -0700 Subject: [PATCH 03/20] Core: Unify duplicated loading functionality, make loads always preload with fixed ROM buffer --- src/core/core.c | 41 +++++++++-------------------------------- 1 file changed, 9 insertions(+), 32 deletions(-) diff --git a/src/core/core.c b/src/core/core.c index 67e54b46b..0a79eabe2 100644 --- a/src/core/core.c +++ b/src/core/core.c @@ -114,6 +114,9 @@ struct mCore* mCoreFind(const char* path) { } bool mCoreLoadFile(struct mCore* core, const char* path) { +#ifdef FIXED_ROM_BUFFER + return mCorePreloadFile(core, path); +#else struct VFile* rom = mDirectorySetOpenPath(&core->dirs, path, core->isROM); if (!rom) { return false; @@ -124,43 +127,15 @@ bool mCoreLoadFile(struct mCore* core, const char* path) { rom->close(rom); } return ret; +#endif } bool mCorePreloadVF(struct mCore* core, struct VFile* vf) { - struct VFile* vfm; -#ifdef FIXED_ROM_BUFFER - extern uint32_t* romBuffer; - extern size_t romBufferSize; - vfm = VFileFromMemory(romBuffer, romBufferSize); -#else - vfm = VFileMemChunk(NULL, vf->size(vf)); -#endif - - uint8_t buffer[2048]; - ssize_t read; - vf->seek(vf, 0, SEEK_SET); - while ((read = vf->read(vf, buffer, sizeof(buffer))) > 0) { - vfm->write(vfm, buffer, read); - } - vf->close(vf); - bool ret = core->loadROM(core, vfm); - if (!ret) { - vfm->close(vfm); - } - return ret; + return mCorePreloadVFCB(core, vf, NULL, NULL); } bool mCorePreloadFile(struct mCore* core, const char* path) { - struct VFile* rom = mDirectorySetOpenPath(&core->dirs, path, core->isROM); - if (!rom) { - return false; - } - - bool ret = mCorePreloadVF(core, rom); - if (!ret) { - rom->close(rom); - } - return ret; + return mCorePreloadFileCB(core, path, NULL, NULL); } bool mCorePreloadVFCB(struct mCore* core, struct VFile* vf, void (cb)(size_t, size_t, void*), void* context) { @@ -182,7 +157,9 @@ bool mCorePreloadVFCB(struct mCore* core, struct VFile* vf, void (cb)(size_t, si while ((read = vf->read(vf, buffer, sizeof(buffer))) > 0) { vfm->write(vfm, buffer, read); total += read; - cb(total, size, context); + if (cb) { + cb(total, size, context); + } } vf->close(vf); bool ret = core->loadROM(core, vfm); From 5c5be73c473a957af45eff152425e4c0207a0d6d Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Thu, 4 Jul 2019 17:45:03 -0700 Subject: [PATCH 04/20] GB MBC: Support for unlicensed Wisdom Tree Game Boy mapper --- CHANGES | 1 + README.md | 1 + include/mgba/gb/interface.h | 1 + src/gb/mbc.c | 42 +++++++++++++++++++++++++++++++++++++ 4 files changed, 45 insertions(+) diff --git a/CHANGES b/CHANGES index 13f5c13e8..a8304684e 100644 --- a/CHANGES +++ b/CHANGES @@ -17,6 +17,7 @@ Features: - Ports: Ability to crop SGB borders off screen (closes mgba.io/i/1204) - Cheats: Add support for loading Libretro-style cht files - GBA Cheats: Add support for loading EZ Flash-style cht files + - Support for unlicensed Wisdom Tree Game Boy mapper Emulation fixes: - GBA: All IRQs have 7 cycle delay (fixes mgba.io/i/539, mgba.io/i/1208) - GBA: Reset now reloads multiboot ROMs diff --git a/README.md b/README.md index 803e1de0f..111eaa337 100644 --- a/README.md +++ b/README.md @@ -49,6 +49,7 @@ The following mappers are fully supported: - MBC5 - MBC5+Rumble - MBC7 +- Wisdom Tree (unlicensed) The following mappers are partially supported: diff --git a/include/mgba/gb/interface.h b/include/mgba/gb/interface.h index 300846c6a..d17593f21 100644 --- a/include/mgba/gb/interface.h +++ b/include/mgba/gb/interface.h @@ -34,6 +34,7 @@ enum GBMemoryBankControllerType { GB_HuC3 = 0x12, GB_POCKETCAM = 0x13, GB_TAMA5 = 0x14, + GB_UNL_WISDOM_TREE = 0x20, GB_MBC3_RTC = 0x103, GB_MBC5_RUMBLE = 0x105 }; diff --git a/src/gb/mbc.c b/src/gb/mbc.c index e87a2a36f..f499f5d18 100644 --- a/src/gb/mbc.c +++ b/src/gb/mbc.c @@ -35,6 +35,7 @@ static void _GBHuC1(struct GB*, uint16_t address, uint8_t value); static void _GBHuC3(struct GB*, uint16_t address, uint8_t value); static void _GBPocketCam(struct GB* gb, uint16_t address, uint8_t value); static void _GBTAMA5(struct GB* gb, uint16_t address, uint8_t value); +static void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value); static uint8_t _GBMBC2Read(struct GBMemory*, uint16_t address); static uint8_t _GBMBC6Read(struct GBMemory*, uint16_t address); @@ -119,6 +120,24 @@ static bool _isMulticart(const uint8_t* mem) { return success; } +static bool _isWisdomTree(const uint8_t* mem) { + int i; + for (i = 0x134; i < 0x14C; i += 4) { + if (*(uint32_t*) &mem[i] != 0) { + return false; + } + } + for (i = 0xF0; i < 0x100; i += 4) { + if (*(uint32_t*) &mem[i] != 0) { + return false; + } + } + if (mem[0x14D] != 0xE7) { + return false; + } + return true; +} + void GBMBCSwitchSramBank(struct GB* gb, int bank) { size_t bankStart = bank * GB_SIZE_EXTERNAL_RAM; if (bankStart + GB_SIZE_EXTERNAL_RAM > gb->sramSize) { @@ -180,6 +199,11 @@ void GBMBCInit(struct GB* gb) { if (gb->memory.mbcType == GB_MBC_AUTODETECT) { switch (cart->type) { case 0: + if (_isWisdomTree(gb->memory.rom)) { + gb->memory.mbcType = GB_UNL_WISDOM_TREE; + break; + } + // Fall through case 8: case 9: gb->memory.mbcType = GB_MBC_NONE; @@ -310,6 +334,9 @@ void GBMBCInit(struct GB* gb) { gb->memory.cam->startRequestImage(gb->memory.cam, GBCAM_WIDTH, GBCAM_HEIGHT, mCOLOR_ANY); } break; + case GB_UNL_WISDOM_TREE: + gb->memory.mbcWrite = _GBWisdomTree; + break; } gb->memory.currentBank = 1; @@ -1167,6 +1194,21 @@ uint8_t _GBTAMA5Read(struct GBMemory* memory, uint16_t address) { } } +void _GBWisdomTree(struct GB* gb, uint16_t address, uint8_t value) { + UNUSED(value); + int bank = address & 0x3F; + switch (address >> 14) { + case 0x0: + GBMBCSwitchBank0(gb, bank * 2); + GBMBCSwitchBank(gb, bank * 2 + 1); + break; + default: + // TODO + mLOG(GB_MBC, STUB, "Wisdom Tree unknown address: %04X:%02X", address, value); + break; + } +} + void GBMBCRTCRead(struct GB* gb) { struct GBMBCRTCSaveBuffer rtcBuffer; struct VFile* vf = gb->sramVf; From 322828737f4334f20d1596b3006fa2619996e91d Mon Sep 17 00:00:00 2001 From: Lothar Serra Mari Date: Sun, 28 Jul 2019 09:58:30 +0200 Subject: [PATCH 05/20] README: Update German README translation --- README_DE.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/README_DE.md b/README_DE.md index 8a1fae9ed..d0e0ab18c 100644 --- a/README_DE.md +++ b/README_DE.md @@ -49,6 +49,7 @@ Die folgenden Mapper werden vollständig unterstützt: - MBC5 - MBC5+Rumble (MBC5+Rüttel-Modul) - MBC7 +- Wisdom Tree (nicht lizenziert) Die folgenden Mapper werden teilweise unterstützt: @@ -85,7 +86,7 @@ Andere Unix-ähnliche Plattformen wie OpenBSD sind ebenfalls dafür bekannt, mit ### Systemvoraussetzungen -Die Systemvoraussetzungen sind minimal. Jeder Computer, der mit Windows Vista oder neuer läuft, sollte in der Lage sein, die Emulation zu bewältigen. Unterstützung für OpenGL 1.1 oder neuer ist ebenfalls voraussgesetzt. +Die Systemvoraussetzungen sind minimal. Jeder Computer, der mit Windows Vista oder neuer läuft, sollte in der Lage sein, die Emulation zu bewältigen. Unterstützung für OpenGL 1.1 oder neuer ist ebenfalls voraussgesetzt. OpenGL 3.0 oder neuer wird für Shader und erweiterte Funktionen benötigt. Downloads --------- From 5018364c0140a0eb8ae8d3368651edd66784a4d9 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sat, 6 Jul 2019 15:21:04 -0700 Subject: [PATCH 06/20] cinema: Update mooneye-gb tests --- .../add_sp_e_timing/baseline_0000.png | Bin 1227 -> 1217 bytes .../acceptance/add_sp_e_timing/test.gb | Bin 32768 -> 32768 bytes .../acceptance/add_sp_e_timing/test.sym | 340 ++++------ .../acceptance/bits/mem_oam/baseline_0000.png | Bin 518 -> 528 bytes .../acceptance/bits/mem_oam/test.gb | Bin 32768 -> 32768 bytes .../acceptance/bits/mem_oam/test.sym | 252 ++------ .../acceptance/bits/reg_f/baseline_0000.png | Bin 1166 -> 1148 bytes .../mooneye-gb/acceptance/bits/reg_f/test.gb | Bin 32768 -> 32768 bytes .../mooneye-gb/acceptance/bits/reg_f/test.sym | 304 ++++----- .../bits/unused_hwio-GS/baseline_0000.png | Bin 518 -> 528 bytes .../acceptance/bits/unused_hwio-GS/test.gb | Bin 32768 -> 32768 bytes .../acceptance/bits/unused_hwio-GS/test.sym | 602 +++++++++++------- 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32768 bytes .../acceptance/ppu/stat_lyc_onoff/test.sym | 80 +++ .../ppu/vblank_stat_intr-GS/baseline_0000.png | Bin 0 -> 1206 bytes .../vblank_stat_intr-GS}/test.gb | Bin 32768 -> 32768 bytes .../ppu/vblank_stat_intr-GS/test.sym | 155 +++++ .../mooneye-gb/acceptance/push_timing/test.gb | Bin 32768 -> 32768 bytes .../acceptance/push_timing/test.sym | 319 ++++------ .../acceptance/rapid_di_ei/baseline_0000.png | Bin 1200 -> 1186 bytes .../mooneye-gb/acceptance/rapid_di_ei/test.gb | Bin 32768 -> 32768 bytes .../acceptance/rapid_di_ei/test.sym | 304 ++++----- .../ret_cc_timing/baseline_0000.png | Bin 518 -> 528 bytes .../acceptance/ret_cc_timing/test.gb | Bin 32768 -> 32768 bytes .../acceptance/ret_cc_timing/test.sym | 275 ++------ .../acceptance/ret_timing/baseline_0000.png | Bin 518 -> 528 bytes .../mooneye-gb/acceptance/ret_timing/test.gb | Bin 32768 -> 32768 bytes .../mooneye-gb/acceptance/ret_timing/test.sym | 275 ++------ .../reti_intr_timing/baseline_0000.png | Bin 1193 -> 1171 bytes .../acceptance/reti_intr_timing/test.gb | Bin 32768 -> 32768 bytes .../acceptance/reti_intr_timing/test.sym | 304 ++++----- .../acceptance/reti_timing/baseline_0000.png | Bin 518 -> 528 bytes .../mooneye-gb/acceptance/reti_timing/test.gb | Bin 32768 -> 32768 bytes .../acceptance/reti_timing/test.sym | 275 ++------ .../acceptance/rst_timing/baseline_0000.png | Bin 1221 -> 1199 bytes .../mooneye-gb/acceptance/rst_timing/test.gb | Bin 32768 -> 32768 bytes .../mooneye-gb/acceptance/rst_timing/test.sym | 325 ++++------ .../boot_sclk_align-dmgABCXmgb/test.sav | 0 .../boot_sclk_align-dmgABCXmgb/test.sym | 198 ------ .../boot_sclk_align-dmgABCmgb/manifest.yml | 1 + .../test.gb | Bin 32768 -> 32768 bytes .../serial/boot_sclk_align-dmgABCmgb/test.sym | 123 ++++ .../timer/div_write/baseline_0000.png | Bin 518 -> 528 bytes .../acceptance/timer/div_write/test.gb | Bin 32768 -> 32768 bytes .../acceptance/timer/div_write/test.sym | 242 ++----- .../acceptance/timer/rapid_toggle/test.gb | Bin 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.../acceptance/timer/tim10/test.sym | 304 ++++----- .../timer/tim10_div_trigger/baseline_0000.png | Bin 1208 -> 1193 bytes .../timer/tim10_div_trigger/test.gb | Bin 32768 -> 32768 bytes .../timer/tim10_div_trigger/test.sym | 304 ++++----- .../acceptance/timer/tim11/baseline_0000.png | Bin 1203 -> 1185 bytes .../mooneye-gb/acceptance/timer/tim11/test.gb | Bin 32768 -> 32768 bytes .../acceptance/timer/tim11/test.sym | 304 ++++----- .../timer/tim11_div_trigger/baseline_0000.png | Bin 1203 -> 1185 bytes .../timer/tim11_div_trigger/test.gb | Bin 32768 -> 32768 bytes .../timer/tim11_div_trigger/test.sym | 304 ++++----- .../timer/tima_reload/baseline_0000.png | Bin 1244 -> 1229 bytes .../acceptance/timer/tima_reload/test.gb | Bin 32768 -> 32768 bytes .../acceptance/timer/tima_reload/test.sym | 304 ++++----- .../tima_write_reloading/baseline_0000.png | Bin 1209 -> 1176 bytes .../timer/tima_write_reloading/test.gb | Bin 32768 -> 32768 bytes .../timer/tima_write_reloading/test.sym | 304 ++++----- .../tma_write_reloading/baseline_0000.png | Bin 1179 -> 1156 bytes .../timer/tma_write_reloading/test.gb | Bin 32768 -> 32768 bytes .../timer/tma_write_reloading/test.sym | 304 ++++----- .../mbc1/bits_ram_en/manifest.yml | 1 + .../bits_ram_en}/test.gb | Bin 65536 -> 65536 bytes .../emulator-only/mbc1/bits_ram_en/test.sym | 84 +++ .../mbc1/multicart_rom_8Mb/baseline_0000.png | Bin 518 -> 528 bytes .../mbc1/multicart_rom_8Mb/test.gb | Bin 1048576 -> 1048576 bytes .../mbc1/multicart_rom_8Mb/test.sym | 285 ++------- .../mbc1/ram_256Kb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/ram_256Kb/test.gb | Bin 65536 -> 65536 bytes .../emulator-only/mbc1/ram_256Kb/test.sym | 312 +++------ .../mbc1/ram_64Kb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/ram_64Kb/test.gb | Bin 65536 -> 65536 bytes .../emulator-only/mbc1/ram_64Kb/test.sym | 301 ++------- .../mbc1/rom_16Mb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/rom_16Mb/test.gb | Bin 2097152 -> 2097152 bytes .../emulator-only/mbc1/rom_16Mb/test.sym | 285 ++------- .../mbc1/rom_1Mb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/rom_1Mb/test.gb | Bin 131072 -> 131072 bytes .../emulator-only/mbc1/rom_1Mb/test.sym | 285 ++------- .../mbc1/rom_2Mb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/rom_2Mb/test.gb | Bin 262144 -> 262144 bytes .../emulator-only/mbc1/rom_2Mb/test.sym | 285 ++------- .../mbc1/rom_4Mb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/rom_4Mb/test.gb | Bin 524288 -> 524288 bytes .../emulator-only/mbc1/rom_4Mb/test.sym | 285 ++------- .../mbc1/rom_512Kb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/rom_512Kb/test.gb | Bin 65536 -> 65536 bytes .../emulator-only/mbc1/rom_512Kb/test.sym | 285 ++------- .../mbc1/rom_8Mb/baseline_0000.png | Bin 518 -> 528 bytes .../emulator-only/mbc1/rom_8Mb/test.gb | Bin 1048576 -> 1048576 bytes .../emulator-only/mbc1/rom_8Mb/test.sym | 285 ++------- .../mbc1_rom_4banks/baseline_0000.png | Bin 518 -> 0 bytes .../emulator-only/mbc1_rom_4banks/test.sym | 205 ------ .../madness/mgb_oam_dma_halt_sprites/test.gb | Bin 32768 -> 32768 bytes .../madness/mgb_oam_dma_halt_sprites/test.sym | 220 +------ .../manual-only/sprite_priority/test.gb | Bin 32768 -> 32768 bytes .../manual-only/sprite_priority/test.sym | 218 +------ .../misc/bits/unused_hwio-C/baseline_0000.png | Bin 518 -> 528 bytes .../misc/bits/unused_hwio-C/test.gb | Bin 32768 -> 32768 bytes .../misc/bits/unused_hwio-C/test.sym | 602 +++++++++++------- .../mooneye-gb/misc/boot_div-A/manifest.yml | 3 + cinema/gb/mooneye-gb/misc/boot_div-A/test.gb | Bin 0 -> 32768 bytes cinema/gb/mooneye-gb/misc/boot_div-A/test.sym | 120 ++++ .../misc/boot_div-cgb0/manifest.yml | 1 + .../gb/mooneye-gb/misc/boot_div-cgb0/test.gb | Bin 0 -> 32768 bytes .../gb/mooneye-gb/misc/boot_div-cgb0/test.sym | 120 ++++ .../misc/boot_div-cgbABCDE/manifest.yml | 1 + .../mooneye-gb/misc/boot_div-cgbABCDE/test.gb | Bin 0 -> 32768 bytes .../misc/boot_div-cgbABCDE/test.sym | 120 ++++ .../misc/boot_hwio-C/baseline_0000.png | Bin 518 -> 528 bytes cinema/gb/mooneye-gb/misc/boot_hwio-C/test.gb | Bin 32768 -> 32768 bytes .../gb/mooneye-gb/misc/boot_hwio-C/test.sym | 261 ++------ .../misc/boot_regs-A/baseline_0000.png | Bin 1354 -> 1344 bytes .../mooneye-gb/misc/boot_regs-A/manifest.yml | 3 +- cinema/gb/mooneye-gb/misc/boot_regs-A/test.gb | Bin 32768 -> 32768 bytes .../gb/mooneye-gb/misc/boot_regs-A/test.sym | 316 ++++----- .../misc/boot_regs-cgb/baseline_0000.png | Bin 1320 -> 1314 bytes .../misc/boot_regs-cgb/manifest.yml | 3 +- .../gb/mooneye-gb/misc/boot_regs-cgb/test.gb | Bin 32768 -> 32768 bytes .../gb/mooneye-gb/misc/boot_regs-cgb/test.sym | 316 ++++----- .../gpu/vblank_stat_intr-C/baseline_0000.png | Bin 1355 -> 0 bytes .../misc/gpu/vblank_stat_intr-C/manifest.yml | 1 - .../misc/gpu/vblank_stat_intr-C/test.gb | Bin 32768 -> 0 bytes .../misc/gpu/vblank_stat_intr-C/test.sym | 216 ------- .../ppu/vblank_stat_intr-C}/manifest.yml | 1 + .../misc/ppu/vblank_stat_intr-C/test.gb | Bin 0 -> 32768 bytes .../misc/ppu/vblank_stat_intr-C/test.sym | 155 +++++ cinema/gb/mooneye-gb/update.py | 4 +- 329 files changed, 10528 insertions(+), 17407 deletions(-) create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-S/manifest.yml create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-S/test.gb create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-S/test.sym rename cinema/gb/mooneye-gb/acceptance/{gpu/hblank_ly_scx_timing-GS => boot_div-dmg0}/manifest.yml (100%) create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-dmg0/test.gb create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-dmg0/test.sym rename cinema/gb/mooneye-gb/acceptance/{gpu/lcdon_timing-dmgABCXmgbS => boot_div-dmgABCmgb}/manifest.yml (100%) create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.gb create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div2-S/manifest.yml create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div2-S/test.gb create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_div2-S/test.sym delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/baseline_0000.png delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/test.sav delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/baseline_0000.png rename cinema/gb/mooneye-gb/acceptance/{boot_regs-dmgABCX => boot_hwio-dmgABCmgb}/test.gb (93%) create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.sym delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/baseline_0000.png delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/baseline_0000.png rename cinema/gb/mooneye-gb/acceptance/{hdma_lcdc => boot_regs-dmgABC}/test.gb (95%) create mode 100644 cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.sym delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABCX/baseline_0000.png delete mode 100644 cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABCX/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/ei_sequence/baseline_0000.png create mode 100644 cinema/gb/mooneye-gb/acceptance/ei_sequence/test.gb create mode 100644 cinema/gb/mooneye-gb/acceptance/ei_sequence/test.sym delete mode 100644 cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/baseline_0000.png delete mode 100644 cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/test.sym delete mode 100644 cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/baseline_0000.png delete mode 100644 cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/test.sym delete mode 100644 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cinema/gb/mooneye-gb/acceptance/{boot_hwio-dmgABCXmgb => oam_dma/sources-dmgABCmgbS}/test.gb (91%) create mode 100644 cinema/gb/mooneye-gb/acceptance/oam_dma/sources-dmgABCmgbS/test.sym rename cinema/gb/mooneye-gb/acceptance/{serial/boot_sclk_align-dmgABCXmgb => ppu/hblank_ly_scx_timing-GS}/manifest.yml (100%) rename cinema/gb/mooneye-gb/acceptance/{gpu/intr_2_0_timing => ppu/hblank_ly_scx_timing-GS}/test.gb (95%) create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/baseline_0000.png rename cinema/gb/mooneye-gb/acceptance/{gpu/intr_2_mode3_timing => ppu/intr_1_2_timing-GS}/test.gb (95%) create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/intr_2_0_timing/baseline_0000.png rename cinema/gb/mooneye-gb/acceptance/{gpu/intr_1_2_timing-GS => ppu/intr_2_0_timing}/test.gb (95%) create mode 100644 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cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/baseline_0000.png create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/test.gb create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/baseline_0000.png rename cinema/gb/mooneye-gb/acceptance/{gpu/intr_2_mode0_timing => ppu/vblank_stat_intr-GS}/test.gb (94%) create mode 100644 cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/test.sym delete mode 100644 cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sav delete mode 100644 cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sym create mode 100644 cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/manifest.yml rename cinema/gb/mooneye-gb/acceptance/serial/{boot_sclk_align-dmgABCXmgb => boot_sclk_align-dmgABCmgb}/test.gb (93%) create mode 100644 cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/test.sym create mode 100644 cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/manifest.yml rename cinema/gb/mooneye-gb/emulator-only/{mbc1_rom_4banks => mbc1/bits_ram_en}/test.gb (96%) create mode 100644 cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.sym delete mode 100644 cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/baseline_0000.png delete mode 100644 cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/test.sym create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-A/manifest.yml create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-A/test.gb create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-A/test.sym create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-cgb0/manifest.yml create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-cgb0/test.gb create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-cgb0/test.sym create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/manifest.yml create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/test.gb create mode 100644 cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/test.sym delete mode 100644 cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/baseline_0000.png delete mode 100755 cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/manifest.yml delete mode 100644 cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.gb delete mode 100644 cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.sym rename cinema/gb/mooneye-gb/{acceptance/hdma_lcdc => misc/ppu/vblank_stat_intr-C}/manifest.yml (68%) create mode 100644 cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/test.gb create mode 100644 cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/test.sym diff --git a/cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/baseline_0000.png index ff29c9a761f073707fba7edeb49d832d9d4650f1..274ead1dea6aa400581617d391509b20149f6240 100644 GIT binary patch literal 1217 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diff --git a/cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/test.sym b/cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/test.sym index 71a70bfcd..35c7019e8 100644 --- a/cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/add_sp_e_timing/test.sym @@ -1,206 +1,144 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/add_sp_e_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0150 _wait_ly_4 -00:0156 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0150 main@wait_ly_5 +00:0156 main@wait_ly_6 00:0180 test_finish -00:01c4 wram_test -00:01d3 hiram_test -00:01d3 test_round1 -00:01d5 _wait_ly_6 -00:01db _wait_ly_7 -00:01f0 finish_round1 -00:01ff test_round2 -00:0201 _wait_ly_8 -00:0207 _wait_ly_9 -00:021d finish_round2 -00:c014 result_tmp -00:c016 result_round1 +00:01c9 wram_test +00:01d8 hiram_test +00:01d8 test_round1 +00:01da test_round1@wait_ly_7 +00:01e0 test_round1@wait_ly_8 +00:01f5 finish_round1 +00:0204 test_round2 +00:0206 test_round2@wait_ly_9 +00:020c test_round2@wait_ly_10 +00:0222 finish_round2 +00:ff91 result_tmp +00:ff93 result_round1 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000002 _sizeof_result_tmp +00000002 _sizeof_result_round1 +00000030 _sizeof_main +00000049 _sizeof_test_finish +0000000f _sizeof_wram_test +00000000 _sizeof_hiram_test +0000001d _sizeof_test_round1 +0000000f _sizeof_finish_round1 +0000001e _sizeof_test_round2 diff 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z-%ofX{dT}pQYzrJkd~nm+(l$UK^$Mp01MM9Aeddq?Dd%m>9?69q!jZcNre#IBuqe87KJhL52c@Q{1E+Ooiw%wb3BI`GVE_OC diff --git a/cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym b/cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym index 9cc9099d8..72dd8a625 100644 --- a/cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/bits/mem_oam/test.sym @@ -1,212 +1,50 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/bits/mem_oam.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts 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_print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:016f test_finish -00:0183 _wait_ly_4 -00:0189 _wait_ly_5 -00:019f _print_results_halt_1 -00:01a2 _test_ok_cb_0 -00:01aa _print_sl_data55 -00:01b2 _print_sl_out55 -00:01b5 fail_1 -00:01c9 _wait_ly_6 -00:01cf _wait_ly_7 -00:01e5 _print_results_halt_2 -00:01e8 _test_failure_cb_0 -00:01f0 _print_sl_data56 -00:01fd _print_sl_out56 -00:0200 fail_0 -00:0214 _wait_ly_8 -00:021a _wait_ly_9 -00:0230 _print_results_halt_3 -00:0233 _test_failure_cb_1 -00:023b _print_sl_data57 -00:0248 _print_sl_out57 +00:0176 test_finish@quit_inline_1 +00:0187 fail_1 +00:018e fail_1@quit_inline_2 +00:01a4 fail_0 +00:01ab fail_0@quit_inline_3 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0160 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bb clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48cf memcpy +01:48d8 memset +01:4898 print_hex4 +01:48c5 print_hex8 +01:48e8 print_inline_string +01:48a4 print_load_font +01:48b0 print_newline +01:48e1 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c017 regs_save -00:c017 regs_save.f -00:c018 regs_save.a -00:c019 regs_save.c -00:c01a regs_save.b -00:c01b regs_save.e -00:c01c regs_save.d -00:c01d regs_save.l -00:c01e regs_save.h -00:c01f regs_flags -00:c020 regs_assert -00:c020 regs_assert.f -00:c021 regs_assert.a -00:c022 regs_assert.c -00:c023 regs_assert.b -00:c024 regs_assert.e -00:c025 regs_assert.d -00:c026 regs_assert.l -00:c027 regs_assert.h -00:c028 memdump_len -00:c029 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:0161 _test_data_0 00:0177 _finish_0 00:0187 _test_data_1 @@ -497,39 +335,357 @@ 00:1807 _finish_152 00:1817 _test_data_153 00:182d _finish_153 -00:1841 _wait_ly_4 -00:1847 _wait_ly_5 -00:185d _print_results_halt_1 -00:1860 _test_ok_cb_0 -00:1868 _print_sl_data55 -00:1870 _print_sl_out55 -00:1873 run_testcase -00:189e _wait_ly_6 -00:18a4 _wait_ly_7 -00:18ba _print_results_halt_2 -00:18bd test_failure_cb -00:18c5 _print_sl_data56 -00:18d1 _print_sl_out56 -00:18df _print_sl_data57 -00:18e3 _print_sl_out57 -00:18f1 _print_sl_data58 -00:1901 _print_sl_out58 -00:190f _print_sl_data59 -00:191c _print_sl_out59 -00:192d _print_sl_data60 -00:193a _print_sl_out60 -00:194b _print_sl_data61 -00:1958 _print_sl_out61 -00:195e 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@@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-dmg0.gb". + +[labels] +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h diff --git a/cinema/gb/mooneye-gb/acceptance/gpu/lcdon_timing-dmgABCXmgbS/manifest.yml b/cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/manifest.yml similarity index 100% rename from cinema/gb/mooneye-gb/acceptance/gpu/lcdon_timing-dmgABCXmgbS/manifest.yml rename to cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/manifest.yml diff --git a/cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.gb 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file mode 100644 index 000000000..79e783897 --- /dev/null +++ b/cinema/gb/mooneye-gb/acceptance/boot_div-dmgABCmgb/test.sym @@ -0,0 +1,120 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_div-dmgABCmgb.gb". + +[labels] +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 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check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml b/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml index 1e96f6ccf..898a81837 100644 --- a/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml +++ b/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/manifest.yml @@ -1 +1,2 @@ -config: {gb.model: SGB} +config: + gb.model: SGB diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.gb b/cinema/gb/mooneye-gb/acceptance/boot_hwio-S/test.gb index f046094b904fe9358f7513c83ae855843c995f9c..2821ae22553f0531d80625194b1ec3c3c8e92459 100644 GIT binary patch delta 557 zcmZo@U}|V!+Th1nzp+7);lH3ila#-3o%`uZ4OXcghh8xXD+4)&$ec`MP9icV5}6Z- z%<)9#IKnx#{~8X3F)IH5U*~RD&j7OSv*Jz0!ynwwZtyt!!XqTLxJ1F1_U-PQ*|7S%8CXlih9=@KzzK$Wz9tw^j3Mvf08vma?>hY@qM1sr!8{--g z;OZRW>Y~8#s|hCY!o%G^L;(yKel>$cCvRo)<}>~OpMl{&!~Z|_AjW1v=Jz%e1#&hy zd|T&ex*(#5-X&z^ncqlT=IH~CH|Mb5PF8}%!egVk|U=q%*TCSkZ#>~em z#v#Y6CaS08P;s`?qY{X#fVdinYk;^Gh$TcF?3{o!8ggKe_`Cjr(*x%R-VeO$?F1h< z*!_9net5SB$kw_O5DQQ5JNbaouJHlWdRqn{Q22TB8UH^n3#Mc2#|)HCDhf0RGB_}P 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"/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-S.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bb clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48cf memcpy +01:48d8 memset +01:4898 print_hex4 +01:48c5 print_hex8 +01:48e8 print_inline_string +01:48a4 print_load_font +01:48b0 print_newline +01:48e1 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_ok_cb_0 -00:020d _print_sl_data55 -00:0215 _print_sl_out55 -00:0218 mismatch -00:023b _wait_ly_6 -00:0241 _wait_ly_7 -00:0257 _print_results_halt_2 -00:025a mismatch_cb -00:0262 _print_sl_data56 -00:0270 _print_sl_out56 -00:028a _print_sl_data57 -00:0294 _print_sl_out57 -00:02a5 _print_sl_data58 -00:02af _print_sl_out58 -00:02b8 hwio_data -00:c014 mismatch_addr -00:c016 mismatch_data -00:c017 mismatch_mem +00:0150 main +00:01d9 main@quit_inline_1 +00:01ea mismatch +00:0200 mismatch@quit_inline_2 +00:024f hwio_data +00:ff80 mismatch_addr +00:ff82 mismatch_data +00:ff83 mismatch_mem + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000002 _sizeof_mismatch_addr +00000001 _sizeof_mismatch_data +00000001 _sizeof_mismatch_mem +0000009a _sizeof_main +00000065 _sizeof_mismatch diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmg0/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bb clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48cf memcpy +01:48d8 memset +01:4898 print_hex4 +01:48c5 print_hex8 +01:48e8 print_inline_string +01:48a4 print_load_font +01:48b0 print_newline +01:48e1 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 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__check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_ok_cb_0 -00:020d _print_sl_data55 -00:0215 _print_sl_out55 -00:0218 mismatch -00:023b _wait_ly_6 -00:0241 _wait_ly_7 -00:0257 _print_results_halt_2 -00:025a mismatch_cb -00:0262 _print_sl_data56 -00:0270 _print_sl_out56 -00:028a _print_sl_data57 -00:0294 _print_sl_out57 -00:02a5 _print_sl_data58 -00:02af _print_sl_out58 -00:02b8 hwio_data -00:c014 mismatch_addr -00:c016 mismatch_data -00:c017 mismatch_mem +00:0150 main +00:01d9 main@quit_inline_1 +00:01ea mismatch +00:0200 mismatch@quit_inline_2 +00:024f hwio_data +00:ff80 mismatch_addr +00:ff82 mismatch_data +00:ff83 mismatch_mem + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000002 _sizeof_mismatch_addr +00000001 _sizeof_mismatch_data +00000001 _sizeof_mismatch_mem +0000009a _sizeof_main +00000065 _sizeof_mismatch diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCXmgb/baseline_0000.png deleted file mode 100644 index 30590ffab18e5deb12be845930a52ab18642fc14..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 518 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|Vn(PZ!6KiaBquU+ii&U|?{x z{qsNmo1B;Hnym>_oA=IKKFMK%PG{+y=amayKVL83P|Yc$UNGlCA=7aXVT-=? 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. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCXmgb.gb". - -[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d 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_print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_ok_cb_0 -00:020d _print_sl_data55 -00:0215 _print_sl_out55 -00:0218 mismatch -00:023b _wait_ly_6 -00:0241 _wait_ly_7 -00:0257 _print_results_halt_2 -00:025a mismatch_cb -00:0262 _print_sl_data56 -00:0270 _print_sl_out56 -00:028a _print_sl_data57 -00:0294 _print_sl_out57 -00:02a5 _print_sl_data58 -00:02af _print_sl_out58 -00:02b8 hwio_data -00:c014 mismatch_addr -00:c016 mismatch_data -00:c017 mismatch_mem diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/baseline_0000.png new file mode 100644 index 0000000000000000000000000000000000000000..f9e5e47b50a4d548ddbc988a8e76364d30f505cf GIT binary patch literal 528 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|VoAPZ!6KiaBquU(7mWz~FE( z<;Va1cWgxt&B%VfEU&=!xnok3TT$lH;@jICuivi!&oIyXfkoqEmOfz%KM+GNxySPP z*F*Dd<=5Z6-dB81|M;InsWNlk%!+)xc#7K&NVrW=$u)AwfPok&xV7Hs3VP7pZii@^*>OsMihy~NwWM5i5 zcv5ew3n>WnBqm-wVU%SZ} zl^qE%n&lJOSW#;%UJfNbue)6A0)r<(coc;BAj}2fb`Yk5knBUDL)Y(e5@JzP4Di>r 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z-MONx)3PmAIKo&N#t^U3QQD5J<)NkP5TespY-iZJsCu2acj;j7hp}H#t)Ir0b+GlT V*srP98?j|S*y;|hU(;ru`WI0i=?VY< diff --git a/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.sym b/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.sym new file mode 100644 index 000000000..3f71b5a1d --- /dev/null +++ b/cinema/gb/mooneye-gb/acceptance/boot_hwio-dmgABCmgb/test.sym @@ -0,0 +1,57 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_hwio-dmgABCmgb.gb". + +[labels] +01:48bb clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48cf memcpy +01:48d8 memset +01:4898 print_hex4 +01:48c5 print_hex8 +01:48e8 print_inline_string +01:48a4 print_load_font +01:48b0 print_newline +01:48e1 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte +01:4000 font +00:0150 main +00:01d9 main@quit_inline_1 +00:01ea mismatch +00:0200 mismatch@quit_inline_2 +00:024f hwio_data +00:ff80 mismatch_addr +00:ff82 mismatch_data +00:ff83 mismatch_mem + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000002 _sizeof_mismatch_addr +00000001 _sizeof_mismatch_data +00000001 _sizeof_mismatch_mem +0000009a _sizeof_main +00000065 _sizeof_mismatch diff --git a/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg/baseline_0000.png deleted file mode 100644 index ca834e18a5af5f709acf3553d285ccfe45e04f10..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1327 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|U!9PZ!6KiaBrR-k!BYfv4r= z&tHGzE59u&mksl9@i?|=&HuDzwh2pEI6Hs+`u9(-Y5MxryaGEt5{gs|EQMysaQgJI zsJSyu{;aojPu%*qw;PO@LclT~iUVUwct@2a*ne)Z&tW{Wk>Regp?Wrc4 z_Fit%RrH_wU#5;N^6lC6-m(3ULnGfC6-^Ojo^(q6aqRz$+wR-L*JxjqN_i_ad9%0p ze)GJyHqrlzFVuF+{5<#s!?ntdCnp|wvZvqNuw&NE@>7vK0+t6~zARc}Ve+Qs!JY$( zIYMR5Ctg2wzxq2-M#?P0@}_J3x#L`Sd9s4TyC$F5c<8nKwOgB?Mntl02wZbjZx{Eu zt#6`@@}AdTc1?@=aIHrC@%pd(wy)k%B>X%0-NDD{ua_j&Oj{myr{ZDQ21)x~mM^=6 z15fa)r7!FL_V>`vOOyVbzF{MGfBNA!-0JTS1}^qG-Ouw;KY8-f-81W^U2i$ONB+*Q z)~~k?I_;`U>8Q7yanL?)!TjK!m3f|72WKq5C3H34U3BWfsm*I9hFRY=D)Y5Zo|QRW zzRz;9X>e`3a(D2m7>g6LHf%Pr{rt^7O_^W_mk=Wmz_O01FW@-8P z={NbmIeuu~zR2m(!C1R(KZBX3PZsh$WO;Q(MZxsv+a5Ru{Z07Tc$42wCWZG_cciu)OySq>Q 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print_regs -0001:4c34 _print_sl_data0 -0001:4c3a _print_sl_out0 -0001:4c47 _print_sl_data1 -0001:4c4d _print_sl_out1 -0001:4c5f _print_sl_data2 -0001:4c65 _print_sl_out2 -0001:4c72 _print_sl_data3 -0001:4c78 _print_sl_out3 -0001:4c8a _print_sl_data4 -0001:4c90 _print_sl_out4 -0001:4c9d _print_sl_data5 -0001:4ca3 _print_sl_out5 -0001:4cb5 _print_sl_data6 -0001:4cbb _print_sl_out6 -0001:4cc8 _print_sl_data7 -0001:4cce _print_sl_out7 -0001:4000 font -0000:c000 regs_save -0000:c000 regs_save.f -0000:c001 regs_save.a -0000:c002 regs_save.c -0000:c003 regs_save.b -0000:c004 regs_save.e -0000:c005 regs_save.d -0000:c006 regs_save.l -0000:c007 regs_save.h -0000:c008 regs_flags -0000:c009 regs_assert -0000:c009 regs_assert.f -0000:c00a regs_assert.a -0000:c00b regs_assert.c -0000:c00c regs_assert.b -0000:c00d regs_assert.e -0000:c00e regs_assert.d -0000:c00f regs_assert.l -0000:c010 regs_assert.h -0000:c011 memdump_len -0000:c012 memdump_addr -0001:47f0 memcpy -0001:47f9 memset -0001:4802 clear_vram -0001:480d reset_screen -0001:481a process_results -0001:481f _wait_ly_0 -0001:4825 _wait_ly_1 -0001:4841 _wait_ly_2 -0001:4847 _wait_ly_3 -0001:4860 _process_results_cb -0001:486b _print_sl_data8 -0001:4875 _print_sl_out8 -0001:488f _print_sl_data9 -0001:489a _print_sl_out9 -0001:48b2 _print_sl_data10 -0001:48be _print_sl_out10 -0001:48bf dump_mem -0001:48cf _wait_ly_4 -0001:48d5 _wait_ly_5 -0001:48f1 _dump_mem_line -0001:491b _check_asserts -0001:4929 _print_sl_data11 -0001:492c _print_sl_out11 -0001:4938 _print_sl_data12 -0001:493a _print_sl_out12 -0001:4942 _print_sl_data13 -0001:4945 _print_sl_out13 -0001:494f __check_assert_fail0 -0001:495a _print_sl_data14 -0001:495d _print_sl_out14 -0001:4960 __check_assert_ok0 -0001:4968 _print_sl_data15 -0001:496d _print_sl_out15 -0001:496f __check_assert_skip0 -0001:4977 _print_sl_data16 -0001:497f _print_sl_out16 -0001:497f __check_assert_out0 -0001:498b _print_sl_data17 -0001:498d _print_sl_out17 -0001:4995 _print_sl_data18 -0001:4998 _print_sl_out18 -0001:49a2 __check_assert_fail1 -0001:49ad _print_sl_data19 -0001:49b0 _print_sl_out19 -0001:49b3 __check_assert_ok1 -0001:49bb _print_sl_data20 -0001:49c0 _print_sl_out20 -0001:49c2 __check_assert_skip1 -0001:49ca _print_sl_data21 -0001:49d2 _print_sl_out21 -0001:49d2 __check_assert_out1 -0001:49dd _print_sl_data22 -0001:49e0 _print_sl_out22 -0001:49ec _print_sl_data23 -0001:49ee _print_sl_out23 -0001:49f6 _print_sl_data24 -0001:49f9 _print_sl_out24 -0001:4a03 __check_assert_fail2 -0001:4a0e _print_sl_data25 -0001:4a11 _print_sl_out25 -0001:4a14 __check_assert_ok2 -0001:4a1c _print_sl_data26 -0001:4a21 _print_sl_out26 -0001:4a23 __check_assert_skip2 -0001:4a2b _print_sl_data27 -0001:4a33 _print_sl_out27 -0001:4a33 __check_assert_out2 -0001:4a3f _print_sl_data28 -0001:4a41 _print_sl_out28 -0001:4a49 _print_sl_data29 -0001:4a4c _print_sl_out29 -0001:4a56 __check_assert_fail3 -0001:4a61 _print_sl_data30 -0001:4a64 _print_sl_out30 -0001:4a67 __check_assert_ok3 -0001:4a6f _print_sl_data31 -0001:4a74 _print_sl_out31 -0001:4a76 __check_assert_skip3 -0001:4a7e _print_sl_data32 -0001:4a86 _print_sl_out32 -0001:4a86 __check_assert_out3 -0001:4a91 _print_sl_data33 -0001:4a94 _print_sl_out33 -0001:4aa0 _print_sl_data34 -0001:4aa2 _print_sl_out34 -0001:4aaa _print_sl_data35 -0001:4aad _print_sl_out35 -0001:4ab7 __check_assert_fail4 -0001:4ac2 _print_sl_data36 -0001:4ac5 _print_sl_out36 -0001:4ac8 __check_assert_ok4 -0001:4ad0 _print_sl_data37 -0001:4ad5 _print_sl_out37 -0001:4ad7 __check_assert_skip4 -0001:4adf _print_sl_data38 -0001:4ae7 _print_sl_out38 -0001:4ae7 __check_assert_out4 -0001:4af3 _print_sl_data39 -0001:4af5 _print_sl_out39 -0001:4afd _print_sl_data40 -0001:4b00 _print_sl_out40 -0001:4b0a __check_assert_fail5 -0001:4b15 _print_sl_data41 -0001:4b18 _print_sl_out41 -0001:4b1b __check_assert_ok5 -0001:4b23 _print_sl_data42 -0001:4b28 _print_sl_out42 -0001:4b2a __check_assert_skip5 -0001:4b32 _print_sl_data43 -0001:4b3a _print_sl_out43 -0001:4b3a __check_assert_out5 -0001:4b45 _print_sl_data44 -0001:4b48 _print_sl_out44 -0001:4b54 _print_sl_data45 -0001:4b56 _print_sl_out45 -0001:4b5e _print_sl_data46 -0001:4b61 _print_sl_out46 -0001:4b6b __check_assert_fail6 -0001:4b76 _print_sl_data47 -0001:4b79 _print_sl_out47 -0001:4b7c __check_assert_ok6 -0001:4b84 _print_sl_data48 -0001:4b89 _print_sl_out48 -0001:4b8b __check_assert_skip6 -0001:4b93 _print_sl_data49 -0001:4b9b _print_sl_out49 -0001:4b9b __check_assert_out6 -0001:4ba7 _print_sl_data50 -0001:4ba9 _print_sl_out50 -0001:4bb1 _print_sl_data51 -0001:4bb4 _print_sl_out51 -0001:4bbe __check_assert_fail7 -0001:4bc9 _print_sl_data52 -0001:4bcc _print_sl_out52 -0001:4bcf __check_assert_ok7 -0001:4bd7 _print_sl_data53 -0001:4bdc _print_sl_out53 -0001:4bde __check_assert_skip7 -0001:4be6 _print_sl_data54 -0001:4bee _print_sl_out54 -0001:4bee __check_assert_out7 -0000:01d2 invalid_sp -0000:01d7 _wait_ly_6 -0000:01dd _wait_ly_7 -0000:01f9 _wait_ly_8 -0000:01ff _wait_ly_9 -0000:0218 _test_failure_cb_0 -0000:0220 _print_sl_data55 -0000:0231 _print_sl_out55 -0000:c014 sp_save diff --git a/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.gb b/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.gb index 533f1368184b1b1725ab4d7598dbea96b9273969..56c676a0bc9caa993f5ba0aeedbb28f7ed877b11 100644 GIT binary patch delta 1139 zcmaizPe>F|9LL|Rl%iSMW()@TW(nH}qlKW59LC-CPd;fN1BDI|xrG!eu7R!DjHR{e zy1RDr+R1Kfd5|uFEGrJnL>=nTA>PG3%9F)PshQrJZCuwBhxxtvzM1dm`+GBwQB{Yk zI_9r)O7rKE8Pj8!8(TA`VZcXQuS~;)z3W*|*j)XR+VB9Jz+pUzCvXH$;V7QQaU2sl zJSl|D^s)%>1QQ=c6Gxc%Dmw8L6W{5hC=(fR2~RVzCXV4a6Fr zfZznLR8b`}FJDF#%pD+&EU?)IRhdi_f_rnh<*?2jR)E(IcrKI3UIEH~oo`v7&jz2# zWNI&PH<#~x*9!340pl`>?jNA+c;^Qe*kpraGMU~V%yaq9K`Wru4tOb(_(1{m{prUV zw!n59d?AzAK_KIj{m5x;S|i=uYPzeZtXcEFnbS#^mNR$@48FWUu^s*bM^oNm8(Iqt z?K=$`{fW3#TWVFWM|v&NyO989H9?|30P!0!xJAdfHE!$B96Wot=;$HkWXb9B+NujK zX-L0@9@7fZ8m9Gx)(9=WN)o;Fy6cnx|0jXH*oP5r6DzSK{>ClIVZ^#VUCA{}f6y=| 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--git a/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym b/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym index 062765d0b..4afeccdca 100644 --- a/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/boot_regs-dmg0/test.sym @@ -1,199 +1,125 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmg0.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:01d3 invalid_sp +00:01da invalid_sp@quit_inline_1 +00:ff91 sp_save + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 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a/cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.sym b/cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.sym new file mode 100644 index 000000000..702e844b8 --- /dev/null +++ b/cinema/gb/mooneye-gb/acceptance/boot_regs-dmgABC/test.sym @@ -0,0 +1,125 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-dmgABC.gb". + +[labels] +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:01d3 invalid_sp +00:01da invalid_sp@quit_inline_1 +00:ff91 sp_save + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000002 _sizeof_sp_save +00000083 _sizeof_main diff --git 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print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save diff --git a/cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/baseline_0000.png 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B<6Hm$ diff --git a/cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym b/cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym index bc2c5e877..6cf9ad808 100644 --- a/cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/boot_regs-mgb/test.sym @@ -1,199 +1,125 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:01d3 invalid_sp +00:01da invalid_sp@quit_inline_1 +00:ff91 sp_save + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:01d3 invalid_sp +00:01da invalid_sp@quit_inline_1 +00:ff91 sp_save + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:01d3 invalid_sp +00:01da invalid_sp@quit_inline_1 +00:ff91 sp_save + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000002 _sizeof_sp_save +00000083 _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/call_cc_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/call_cc_timing/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0184 test_finish -00:0198 _wait_ly_6 -00:019e _wait_ly_7 -00:01b4 _print_results_halt_1 -00:01b7 _test_ok_cb_0 -00:01bf _print_sl_data55 -00:01c7 _print_sl_out55 -00:01ca wram_test -00:01cd fail_round1 -00:01e1 _wait_ly_8 -00:01e7 _wait_ly_9 -00:01fd _print_results_halt_2 -00:0200 _test_failure_cb_0 -00:0208 _print_sl_data56 -00:0216 _print_sl_out56 -00:0219 fail_round2 -00:022d _wait_ly_10 -00:0233 _wait_ly_11 -00:0249 _print_results_halt_3 -00:024c _test_failure_cb_1 -00:0254 _print_sl_data57 -00:0262 _print_sl_out57 +00:018b test_finish@quit_inline_1 +00:019c wram_test +00:019f fail_round1 +00:01a6 fail_round1@quit_inline_2 +00:01bd fail_round2 +00:01c4 fail_round2@quit_inline_3 00:1f80 hiram_test -00:1f87 _wait_ly_12 -00:1f8d _wait_ly_13 +00:1f87 hiram_test@wait_ly_7 +00:1f8d hiram_test@wait_ly_8 00:1fa1 test_round2 -00:1fa8 _wait_ly_14 -00:1fae _wait_ly_15 +00:1fa8 test_round2@wait_ly_9 +00:1fae test_round2@wait_ly_10 00:1fca finish_round1 00:1ada finish_round2 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000034 _sizeof_main +00000018 _sizeof_test_finish +00000003 _sizeof_wram_test +0000001e _sizeof_fail_round1 +0000191d _sizeof_fail_round2 +000004a6 _sizeof_finish_round2 +00000021 _sizeof_hiram_test +00000029 _sizeof_test_round2 diff --git a/cinema/gb/mooneye-gb/acceptance/call_cc_timing2/baseline_0000.png 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z6B@%R!kK%3*%LA|!f!JNQAy?)N{Qq{&xn3L^j8pY4y95g^a8I;4HLQ`AsHroCw81G%F zk2$dx$?nNSw0BOy9rQjj+(9i4Z^XtxC#fX59ldX%6&q0=cRe1=I4aE<{1J9CmV+_) zYjlv-LTkEhsVao1^rB(5dnaVC8TL-@?!6uQQ?m6zXytdeJ_`M!Y<(75#?DqJSo~P& G|KvXuVeO~@ diff --git a/cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym b/cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym index bef813fa7..1df29700d 100644 --- a/cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/call_cc_timing2/test.sym @@ -1,204 +1,138 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_cc_timing2.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0177 test_finish -00:01cf hiram_test -00:01d2 _wait_ly_6 -00:01d8 _wait_ly_7 -00:01ec finish_round1 -00:01ed _wait_ly_8 -00:01f3 _wait_ly_9 -00:0208 finish_round2 -00:0209 _wait_ly_10 -00:020f _wait_ly_11 -00:0225 finish_round3 +00:01d2 hiram_test +00:01d5 hiram_test@wait_ly_7 +00:01db hiram_test@wait_ly_8 +00:01ef finish_round1 +00:01f0 finish_round1@wait_ly_9 +00:01f6 finish_round1@wait_ly_10 +00:020b finish_round2 +00:020c finish_round2@wait_ly_11 +00:0212 finish_round2@wait_ly_12 +00:0228 finish_round3 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000027 _sizeof_main +0000005b _sizeof_test_finish +0000001d _sizeof_hiram_test +0000001c _sizeof_finish_round1 +0000001d _sizeof_finish_round2 diff --git a/cinema/gb/mooneye-gb/acceptance/call_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/call_timing/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/call_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/call_timing/test.gb index da3eec14929927f82a10015b0652c55b33313042..d98a4139e123921a403a43ea9ccd8b16b0ba85e0 100644 GIT binary patch delta 431 zcmZo@U}|V!+Th1n|1|US2bX{S3crBl1chIU3=M+w7#Rf^&hGS3{P$OI4vgLKU$8-* zF##lgxZ(e2#csyKAKcF_@i=?QBP6xBM8V&iL5$(#Sq7=kipvmEZjPQlRtiD>p?)q3 zh74j(CqFA5L6O}Y&QvThQJ{&gz;udz zlfwu0dP9Z>jI16L(=~4Sk{++x{YyJh5lfckr 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b/cinema/gb/mooneye-gb/acceptance/call_timing/test.sym @@ -1,223 +1,66 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/call_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0184 test_finish -00:0198 _wait_ly_6 -00:019e _wait_ly_7 -00:01b4 _print_results_halt_1 -00:01b7 _test_ok_cb_0 -00:01bf _print_sl_data55 -00:01c7 _print_sl_out55 -00:01ca wram_test -00:01cd fail_round1 -00:01e1 _wait_ly_8 -00:01e7 _wait_ly_9 -00:01fd _print_results_halt_2 -00:0200 _test_failure_cb_0 -00:0208 _print_sl_data56 -00:0216 _print_sl_out56 -00:0219 fail_round2 -00:022d _wait_ly_10 -00:0233 _wait_ly_11 -00:0249 _print_results_halt_3 -00:024c _test_failure_cb_1 -00:0254 _print_sl_data57 -00:0262 _print_sl_out57 +00:018b test_finish@quit_inline_1 +00:019c wram_test +00:019f fail_round1 +00:01a6 fail_round1@quit_inline_2 +00:01bd fail_round2 +00:01c4 fail_round2@quit_inline_3 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0158 _wait_ly_4 -00:015e _wait_ly_5 +00:0150 main +00:0158 main@wait_ly_5 +00:015e main@wait_ly_6 00:016d test_round1 00:0177 _delay_long_time_0 00:0186 finish_round1 -00:0189 _wait_ly_6 -00:018f _wait_ly_7 +00:0189 finish_round1@wait_ly_7 +00:018f finish_round1@wait_ly_8 00:019e test_round2 00:01a8 _delay_long_time_1 00:01b4 test_finish -00:01c8 _wait_ly_8 -00:01ce _wait_ly_9 -00:01e4 _print_results_halt_1 -00:01e7 _test_ok_cb_0 -00:01ef _print_sl_data55 -00:01f7 _print_sl_out55 -00:01fa fail_halt -00:020e _wait_ly_10 -00:0214 _wait_ly_11 -00:022a _print_results_halt_2 -00:022d _test_failure_cb_0 -00:0235 _print_sl_data56 -00:0240 _print_sl_out56 -00:0243 fail_round1 -00:0257 _wait_ly_12 -00:025d _wait_ly_13 -00:0273 _print_results_halt_3 -00:0276 _test_failure_cb_1 -00:027e _print_sl_data57 -00:028c _print_sl_out57 -00:028f fail_round2 -00:02a3 _wait_ly_14 -00:02a9 _wait_ly_15 -00:02bf _print_results_halt_4 -00:02c2 _test_failure_cb_2 -00:02ca _print_sl_data58 -00:02d8 _print_sl_out58 +00:01bb test_finish@quit_inline_1 +00:01cc fail_halt +00:01d3 fail_halt@quit_inline_2 +00:01e7 fail_round1 +00:01ee fail_round1@quit_inline_3 +00:0205 fail_round2 +00:020c fail_round2@quit_inline_4 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +0000001d _sizeof_main +0000000a _sizeof_test_round1 +0000000f _sizeof__delay_long_time_0 +00000018 _sizeof_finish_round1 +0000000a _sizeof_test_round2 +0000000c _sizeof__delay_long_time_1 +00000018 _sizeof_test_finish +0000001b _sizeof_fail_halt +0000001e _sizeof_fail_round1 diff --git a/cinema/gb/mooneye-gb/acceptance/div_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/div_timing/baseline_0000.png index 67f91d46142956cb2da784f7759ee9088a9d3c54..a5f8b0adc988507313c70070ae3ccc7aea7b8b46 100644 GIT binary patch delta 1020 zcmV-B!6p3L_t(|ob8?6mZKmL260c`|CQYfcNq^ti~Nkum#Ujd)F4`d zG%&jD`yN1-KW}FM=7L~x5G)RY#X+z*2o?vy;(S5~+qT8;L&D;1+X%0n@HzfOABmeb z_t`CDQpwuv)zGltQu<%cw(ooCY+hxbuY+UblAaoip&-)UZ-30NkyVKNl;GQvbY6ID znO&PDYvt*FuX~R_ETs>h_$hm??emqCew(Y6+l}p2*{o8O6F%oJiQ`i3-B4WY8)Ra| zxNEef|IPGX@01wleC{{NL5W!f%AYv&WQl`daS$vHg2h3wI0zO8!QwP_bcEA@QfCf~ zbUM4ql78}0Nq=1j$~qIDO1t18WQT_0s{Zt6%wM<;UtYKILu0n=1FJk*tHL{#ucQ6X#U~&A$!NJXV@a zZ0z=0eLl1EpGS4bPsMM}UDBs+JAKifW=kGg;snu-U3y}Vo z-+%+-!SWCXlRyM3f8*tO(V;LEa?~TEo#%5NUY-}7O=@c5e)2h$H{Y9dyNgjuLf?Cn z9_`2*PT!mKJO8w@NOA-wzEq}xQW+s_oi-w_mZKmL1$9pT|CeVUvSU0-w+M7>uT?KQ<0!UN zAT+Sa{QLVmfi6E+2LQ1kSR4e4gJ5wGEDnOjL9jTlX`1GFUVdMv#p~nNpEhaqsY^B| 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0232 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram 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check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:01a0 test +00:01b2 fail +00:01b9 fail@quit_inline_1 +00:01d0 test_finish + +[definitions] +0000023b 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"/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ei_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0160 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000010 _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/gpu/hblank_ly_scx_timing-GS/baseline_0000.png deleted file mode 100644 index 30590ffab18e5deb12be845930a52ab18642fc14..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 518 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|Vn(PZ!6KiaBquU+ii&U|?{x z{qsNmo1B;Hnym>_oA=IKKFMK%PG{+y=amayKVL83P|Yc$UNGlCA=7aXVT-=? z!k=yOkD14xIsL}yU*6ou>NjH3zniQ39G*S5wqpCv-MoGwmU%1ReYcCb`1o>KP3^w? ztOf5>mpy*jtQ#kFe`4bIZO>aK*KeA(W&QeB-gmZts{j0uW&QSw+MxBj7WH4RJhN-X q{>0ypYS_V6!tEYqAjbqaH2yLz>&fNk@rld;#jmHUpUXO@geCx}Th!

. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/hblank_ly_scx_timing-GS.gb". - -[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 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-00:03d1 _print_sl_out55 -00:03d4 test_fail -00:0404 _wait_ly_8 -00:040a _wait_ly_9 -00:0420 _print_results_halt_2 -00:0423 _test_failure_dump_cb_0 -00:042e _print_sl_data56 -00:0438 _print_sl_out56 -00:044c _print_sl_data57 -00:0458 _print_sl_out57 -00:045b standard_delay -00:0473 setup_and_wait -00:0473 _wait_ly_10 -00:0479 _wait_ly_11 -00:048d fail_halt -00:04a1 _wait_ly_12 -00:04a7 _wait_ly_13 -00:04bd _print_results_halt_3 -00:04c0 _test_failure_cb_0 -00:04c8 _print_sl_data58 -00:04d3 _print_sl_out58 diff --git a/cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/gpu/intr_1_2_timing-GS/baseline_0000.png deleted file mode 100644 index 3b4cc1095ac76045182ea615a70719f7a873b83c..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1199 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|QH$r;B4q#hkZu?@n4}Ai!35 z`g?uq`PSu1tTPo=Bqi;4<(Ii~B;RWJ)7XFg_0|Tx`fzrJjS3MmEZxlsg#tQ!O-CI! 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"/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/gpu/intr_1_2_timing-GS.gb". - -[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d 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_print_results_halt_1 -00:01fe _test_failure_cb_0 -00:0206 _print_sl_data55 -00:0211 _print_sl_out55 diff --git a/cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/baseline_0000.png deleted file mode 100644 index 7eb77961da7e3261e5d57cdefc5e0db8d295ea3e..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 1195 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|QHur;B4q#hkZu?@n4}Ai!35 z`g?uq`PStItTPo=Bqi;4<(GxZ9NWVAGgyB8^=!u2f9w1hk{mZ!aEP%Ve54Q|!_wWH zP&n`OCL6i_uVt1xdhfT(-Qrp7Z<|{D;nxb$Bd0F=zkFtMzy6ey4)=#?K+_c&E(J#L&%X=#i zPCF6&@%`cDleg~w5vqB5<6e!^%eTx~s@k~VN0QBH>EFKsb45=(ZLx}+ed>wL(yseb z??2l}|FOf?o$k*i-P48t*4bXWlOuX z_`mAb{fpO<4&0e5aqi~r&s)CrM}1dMEK$proE^Dm8{7O%(sO+TN;b`kSbo?j{F)X} zci*x1>rJ1%^xw1o(d0c(cs(ySMP6_LB{^6;BGTdKnX9(gxm?}%;PR$@uh$2yVYdkG zx%%1a_2v7KGrUe8jM=i4_r|aP1*I#hKGZ3d@8{fU+dl2_`@{d$ekIntzk2$|M()>j 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts 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-01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 00:0167 test_round1 00:0184 finish_round1 00:0193 test_round2 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 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quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0175 _wait_ly_4 -00:017b _wait_ly_5 -00:0191 _print_results_halt_1 -00:0194 _test_failure_cb_0 -00:019c _print_sl_data55 -00:01a8 _print_sl_out55 -00:01ab test_finish +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0168 main@quit_inline_1 +00:017d test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert 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"/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/halt_ime1_timing2-GS.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed 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-01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 00:0167 test_round1 00:0183 _delay_long_time_0 00:0193 finish_round1 @@ -200,38 +92,65 @@ 00:01f8 finish_round3 00:0207 test_round4 00:0221 finish_round4 -00:0268 fail_halt -00:027c _wait_ly_5 -00:0282 _wait_ly_6 -00:0298 _print_results_halt_1 -00:029b _test_failure_cb_0 -00:02a3 _print_sl_data55 -00:02ae _print_sl_out55 -00:02b1 fail_round1 -00:02c5 _wait_ly_7 -00:02cb _wait_ly_8 -00:02e1 _print_results_halt_2 -00:02e4 _test_failure_cb_1 -00:02ec _print_sl_data56 -00:02fa _print_sl_out56 -00:02fd fail_round2 -00:0311 _wait_ly_9 -00:0317 _wait_ly_10 -00:032d _print_results_halt_3 -00:0330 _test_failure_cb_2 -00:0338 _print_sl_data57 -00:0346 _print_sl_out57 -00:0349 fail_round3 -00:035d _wait_ly_11 -00:0363 _wait_ly_12 -00:0379 _print_results_halt_4 -00:037c _test_failure_cb_3 -00:0384 _print_sl_data58 -00:0392 _print_sl_out58 -00:0395 fail_round4 -00:03a9 _wait_ly_13 -00:03af _wait_ly_14 -00:03c5 _print_results_halt_5 -00:03c8 _test_failure_cb_4 -00:03d0 _print_sl_data59 -00:03de _print_sl_out59 +00:026d fail_halt +00:0274 fail_halt@quit_inline_1 +00:0288 fail_round1 +00:028f fail_round1@quit_inline_2 +00:02a6 fail_round2 +00:02ad fail_round2@quit_inline_3 +00:02c4 fail_round3 +00:02cb fail_round3@quit_inline_4 +00:02e2 fail_round4 +00:02e9 fail_round4@quit_inline_5 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d 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_print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 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"/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/if_ie_registers.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/if_ie_registers.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:01ef test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram 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information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/instr/daa.gb". + +[labels] +01:68ee clear_vram +01:68ad disable_lcd_safe +01:68b3 disable_lcd_safe@wait_ly_0 +01:6902 memcpy +01:690b memset +01:6866 print_bin4 +01:68cb print_hex4 +01:68f8 print_hex8 +01:691b print_inline_string +01:68d7 print_load_font +01:68e3 print_newline +01:6914 print_string +01:67f0 quit +01:6805 quit@cb_return +01:680a quit@wait_ly_1 +01:6810 quit@wait_ly_2 +01:6816 quit@wait_ly_3 +01:681c quit@wait_ly_4 +01:6826 quit@success +01:684d quit@failure +01:6862 quit@halt +01:6863 quit@halt_execution_0 +01:6899 reset_screen +01:68bc serial_send_byte +01:6000 font +00:0150 main +00:0163 main@quit_inline_1 +00:0174 run_tests +00:01a9 fail +00:0274 fail@wait_ly_5 +00:027a fail@wait_ly_6 +00:0281 fail@halt_execution_1 +00:0284 testcases1 +01:4000 testcases2 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000033 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created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/interrupts/ie_push.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/interrupts/ie_push.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:0200 round1 00:0214 finish_round1 00:021d round2 @@ -197,86 +33,59 @@ 00:0238 finish_round3 00:023f round4 00:0253 finish_round4 -00:0270 _wait_ly_4 -00:0276 _wait_ly_5 -00:028c _print_results_halt_1 -00:028f _test_ok_cb_0 -00:0297 _print_sl_data55 -00:029f _print_sl_out55 +00:0263 finish_round4@quit_inline_1 00:1000 fail_round1_nointr -00:1017 _wait_ly_6 -00:101d _wait_ly_7 -00:1033 _print_results_halt_2 -00:1036 _test_failure_cb_0 -00:103e _print_sl_data56 -00:104f _print_sl_out56 -00:1052 fail_round1_nocancel -00:1069 _wait_ly_8 -00:106f _wait_ly_9 -00:1085 _print_results_halt_3 -00:1088 _test_failure_cb_1 -00:1090 _print_sl_data57 -00:10a2 _print_sl_out57 -00:10a5 fail_round1_if -00:10bc _wait_ly_10 -00:10c2 _wait_ly_11 -00:10d8 _print_results_halt_4 -00:10db _test_failure_cb_2 -00:10e3 _print_sl_data58 -00:10f3 _print_sl_out58 -00:10f6 fail_round2_intr -00:110d _wait_ly_12 -00:1113 _wait_ly_13 -00:1129 _print_results_halt_5 -00:112c _test_failure_cb_3 -00:1134 _print_sl_data59 -00:1146 _print_sl_out59 -00:1149 fail_round3_nointr -00:1160 _wait_ly_14 -00:1166 _wait_ly_15 -00:117c _print_results_halt_6 -00:117f _test_failure_cb_4 -00:1187 _print_sl_data60 -00:1198 _print_sl_out60 -00:119b fail_round3_cancel -00:11b2 _wait_ly_16 -00:11b8 _wait_ly_17 -00:11ce _print_results_halt_7 -00:11d1 _test_failure_cb_5 -00:11d9 _print_sl_data61 -00:11ed _print_sl_out61 -00:11f0 fail_round3_if -00:1207 _wait_ly_18 -00:120d _wait_ly_19 -00:1223 _print_results_halt_8 -00:1226 _test_failure_cb_6 -00:122e _print_sl_data62 -00:123e _print_sl_out62 -00:1241 fail_round4_nointr -00:1258 _wait_ly_20 -00:125e _wait_ly_21 -00:1274 _print_results_halt_9 -00:1277 _test_failure_cb_7 -00:127f _print_sl_data63 -00:1290 _print_sl_out63 -00:1293 fail_round4_cancel -00:12aa _wait_ly_22 -00:12b0 _wait_ly_23 -00:12c6 _print_results_halt_10 -00:12c9 _test_failure_cb_8 -00:12d1 _print_sl_data64 -00:12e5 _print_sl_out64 -00:12e8 fail_round4_if -00:12ff _wait_ly_24 -00:1305 _wait_ly_25 -00:131b _print_results_halt_11 -00:131e _test_failure_cb_9 -00:1326 _print_sl_data65 -00:1333 _print_sl_out65 -00:1336 fail_round4_vblank -00:134d _wait_ly_26 -00:1353 _wait_ly_27 -00:1369 _print_results_halt_12 -00:136c _test_failure_cb_10 -00:1374 _print_sl_data66 -00:1383 _print_sl_out66 +00:100a fail_round1_nointr@quit_inline_2 +00:1024 fail_round1_nocancel +00:102e fail_round1_nocancel@quit_inline_3 +00:1049 fail_round1_if +00:1053 fail_round1_if@quit_inline_4 +00:106c fail_round2_intr +00:1076 fail_round2_intr@quit_inline_5 +00:1091 fail_round3_nointr +00:109b fail_round3_nointr@quit_inline_6 +00:10b5 fail_round3_cancel +00:10bf fail_round3_cancel@quit_inline_7 +00:10dc fail_round3_if +00:10e6 fail_round3_if@quit_inline_8 +00:10ff fail_round4_nointr +00:1109 fail_round4_nointr@quit_inline_9 +00:1123 fail_round4_cancel +00:112d fail_round4_cancel@quit_inline_10 +00:114a fail_round4_if +00:1154 fail_round4_if@quit_inline_11 +00:116a fail_round4_vblank +00:1174 fail_round4_vblank@quit_inline_12 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +000000b0 _sizeof_main +00000014 _sizeof_round1 +00000009 _sizeof_finish_round1 +00000007 _sizeof_round2 +00000011 _sizeof_round3 +00000003 _sizeof_target +00000007 _sizeof_finish_round3 +00000014 _sizeof_round4 +00000dad _sizeof_finish_round4 +00000024 _sizeof_fail_round1_nointr +00000025 _sizeof_fail_round1_nocancel +00000023 _sizeof_fail_round1_if +00000025 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zvL+v4n6WIj!GA`_pzd39eM{3YM1wa?t6w{#YAwHZ_F(O2zMoU2*L^F0u=E?>FRIcz TzJ>puqAAgV)4N@zW6%EsJ*48k diff --git a/cinema/gb/mooneye-gb/acceptance/intr_timing/test.sym b/cinema/gb/mooneye-gb/acceptance/intr_timing/test.sym index 78f547ba7..378f26caa 100644 --- a/cinema/gb/mooneye-gb/acceptance/intr_timing/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/intr_timing/test.sym @@ -1,208 +1,132 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/intr_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/intr_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0157 test_round1 -00:01a7 _wait_ly_4 -00:01ad _wait_ly_5 -00:01c3 _print_results_halt_1 -00:01c6 _test_failure_cb_0 -00:01ce _print_sl_data55 -00:01dc _print_sl_out55 -00:01df finish_round1 -00:01e1 test_round2 -00:0232 _wait_ly_6 -00:0238 _wait_ly_7 -00:024e _print_results_halt_2 -00:0251 _test_failure_cb_1 -00:0259 _print_sl_data56 -00:0267 _print_sl_out56 -00:026a finish_round2 -00:026f test_finish +00:019a test_round1@quit_inline_1 +00:01b1 finish_round1 +00:01b3 test_round2 +00:01f7 test_round2@quit_inline_2 +00:020e finish_round2 +00:0213 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000007 _sizeof_main +0000005a _sizeof_test_round1 +00000002 _sizeof_finish_round1 +0000005b _sizeof_test_round2 +00000005 _sizeof_finish_round2 diff --git a/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.gb index ccd0466aa54a19e7ffccd326ec2d6e2816a813cb..87240e73152c6b835ec0b0ace888b65bb4bbf958 100644 GIT binary patch delta 431 zcmZo@U}|V!+Th1n|Mbb{4=(@u6@CH92@1ay85#uVF)|7;oZac6`0uaa92mRdzhHwr zV**J0aKr!4irtKdKe(S=;&JwpM@VXMiGsg3gBZifTMSa46_+8T+#Ef9tQ3O$L;YM7 z3>n0nPJUKAf+D*)oT*r1qCgkZ;rW}-NbO@`?4R5%uK*<1$m=uhW!zlI6e+Q}f$0?c zCWjB~^@a=&7+F1zK0RCIaW>84>R{&tq|uNAgT&wU51bx2Kk$Cwm1!sVz`^d%1NX!0 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b/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.sym index d91d4810d..7cd29900a 100644 --- a/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/jp_cc_timing/test.sym @@ -1,223 +1,66 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_cc_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_cc_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0184 test_finish -00:0198 _wait_ly_6 -00:019e _wait_ly_7 -00:01b4 _print_results_halt_1 -00:01b7 _test_ok_cb_0 -00:01bf _print_sl_data55 -00:01c7 _print_sl_out55 -00:01ca wram_test -00:01cd fail_round1 -00:01e1 _wait_ly_8 -00:01e7 _wait_ly_9 -00:01fd _print_results_halt_2 -00:0200 _test_failure_cb_0 -00:0208 _print_sl_data56 -00:0216 _print_sl_out56 -00:0219 fail_round2 -00:022d _wait_ly_10 -00:0233 _wait_ly_11 -00:0249 _print_results_halt_3 -00:024c _test_failure_cb_1 -00:0254 _print_sl_data57 -00:0262 _print_sl_out57 +00:018b test_finish@quit_inline_1 +00:019c wram_test +00:019f fail_round1 +00:01a6 fail_round1@quit_inline_2 +00:01bd fail_round2 +00:01c4 fail_round2@quit_inline_3 00:1f80 hiram_test -00:1f87 _wait_ly_12 -00:1f8d _wait_ly_13 +00:1f87 hiram_test@wait_ly_7 +00:1f8d hiram_test@wait_ly_8 00:1fa1 test_round2 -00:1fa8 _wait_ly_14 -00:1fae _wait_ly_15 +00:1fa8 test_round2@wait_ly_9 +00:1fae test_round2@wait_ly_10 00:1fca finish_round1 00:1ada finish_round2 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000034 _sizeof_main +00000018 _sizeof_test_finish +00000003 _sizeof_wram_test +0000001e _sizeof_fail_round1 +0000191d _sizeof_fail_round2 +000004a6 _sizeof_finish_round2 +00000021 _sizeof_hiram_test +00000029 _sizeof_test_round2 diff --git a/cinema/gb/mooneye-gb/acceptance/jp_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/jp_timing/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/jp_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/jp_timing/test.gb index 671a7bbcf64be7e2043b5fff054eef3e77ccc8de..ca092b922f61e397bdf39680ad926de551284df4 100644 GIT binary patch delta 431 zcmZo@U}|V!+Th1n|1|#d2bX{S3crBl1chIU3=M+w7#Rf^&hGS3{P$OI4vgLKU$8-* zF##lgxZ(e2#csyKAKcF_@i=?QBP6xBM8V&iL5$(#VFszsipvmEZjPQlRtiD>p?)q3 zh74j(CqFA5L6O}Y&QvThQJ{&gz;udz zlfwu0dP9Z>jI16L(=~4Sk{++x{YyJh5lfckr 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100644 --- a/cinema/gb/mooneye-gb/acceptance/jp_timing/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/jp_timing/test.sym @@ -1,223 +1,66 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/jp_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0184 test_finish -00:0198 _wait_ly_6 -00:019e _wait_ly_7 -00:01b4 _print_results_halt_1 -00:01b7 _test_ok_cb_0 -00:01bf _print_sl_data55 -00:01c7 _print_sl_out55 -00:01ca wram_test -00:01cd fail_round1 -00:01e1 _wait_ly_8 -00:01e7 _wait_ly_9 -00:01fd _print_results_halt_2 -00:0200 _test_failure_cb_0 -00:0208 _print_sl_data56 -00:0216 _print_sl_out56 -00:0219 fail_round2 -00:022d _wait_ly_10 -00:0233 _wait_ly_11 -00:0249 _print_results_halt_3 -00:024c _test_failure_cb_1 -00:0254 _print_sl_data57 -00:0262 _print_sl_out57 +00:018b test_finish@quit_inline_1 +00:019c wram_test +00:019f fail_round1 +00:01a6 fail_round1@quit_inline_2 +00:01bd fail_round2 +00:01c4 fail_round2@quit_inline_3 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0187 test_finish -00:01cb wram_test -00:01d1 hiram_test -00:01d3 _wait_ly_6 -00:01d9 _wait_ly_7 -00:01ee finish_round1 -00:01f0 _wait_ly_8 -00:01f6 _wait_ly_9 -00:020c finish_round2 +00:01d0 wram_test +00:01d6 hiram_test +00:01d8 hiram_test@wait_ly_7 +00:01de hiram_test@wait_ly_8 +00:01f3 finish_round1 +00:01f5 finish_round1@wait_ly_9 +00:01fb finish_round1@wait_ly_10 +00:0211 finish_round2 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 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"/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma/sources-dmgABCmgbS.gb". + +[labels] +01:495d clear_oam +01:4967 clear_vram +01:4971 clear_wram +01:491a disable_lcd_safe +01:4920 disable_lcd_safe@wait_ly_0 +01:4938 memcmp +01:497b memcpy +01:4984 memset +01:4994 print_inline_string +01:4946 print_load_font +01:4952 print_newline +01:498d print_string +01:4890 quit +01:48a5 quit@cb_return +01:48aa quit@wait_ly_1 +01:48b0 quit@wait_ly_2 +01:48b6 quit@wait_ly_3 +01:48bc quit@wait_ly_4 +01:48c6 quit@success +01:48ed quit@failure +01:4902 quit@halt +01:4903 quit@halt_execution_0 +01:4906 reset_screen +01:4929 serial_send_byte +01:40a0 font +00:0150 main +00:015c prepare_part1 +00:015f test_0000 +00:0174 test_0000@quit_inline_1 +00:0189 test_3f00 +00:019e test_3f00@quit_inline_2 +00:01b3 test_4000 +00:01c8 test_4000@quit_inline_3 +00:01dd test_7f00 +00:01f2 test_7f00@quit_inline_4 +00:0207 prepare_part2 +00:0213 test_8000 +00:0228 test_8000@quit_inline_5 +00:023d test_9f00 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0171 test_finish -00:01a1 hiram_test -00:01a6 _wait_ly_6 -00:01ac _wait_ly_7 -00:01c6 _wait_ly_8 -00:01cc _wait_ly_9 +00:01a8 hiram_test +00:01ad hiram_test@wait_ly_7 +00:01b3 hiram_test@wait_ly_8 +00:01cd hiram_test@wait_ly_9 +00:01d3 hiram_test@wait_ly_10 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000021 _sizeof_main +00000037 _sizeof_test_finish diff --git a/cinema/gb/mooneye-gb/acceptance/oam_dma_start/test.gb b/cinema/gb/mooneye-gb/acceptance/oam_dma_start/test.gb index 88687e9c468007878e31da3ac49658ecd5bca8c0..d4ba64b11b250337fd0452d883f52a5c9d28ff3a 100644 GIT binary patch delta 1278 zcmai!Pe>F|9LL{`rJ?1&P1%fcW(eDeA|*&9ALFk7a)b#BG(1%37E+|Ng0`FOSXt}e zbrHowhoXbsHtQf=f?8G_mVpkHo#I{e&_PBPDJA#y-fYvl{>fo}Gru?Q`}zLn&Eq$U z!YT?on$HGsK;#11sq7e@7BiXVZ=a)DnZyHyc@E&bHYxD|44;)ih9AT5qW~F!2QfOg zhtA=3*ww|0I1SH{l68z&3;%PE5%)uE!rj9bUL40YYZF+G7W?qRm+(q4Ktbd~1E?Pj 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z%dOm!fMp`Ed<%FBMmO-hC}g4MB>_WE-ug3X#7F%aBz!F(SweV6KHv$XkT4k}T$lVH z;3t8?fL}SZ)G)z02cD?Pk57sS$HgkbJx9QEBJk8DKk%FrDD*rnU}(upuSh*FeI5c{ z6_At>KF3#O zfrO>Se{+Wdhn~>d)>6$h%H!^s+b!8~ALT~$h8%4F`xNS^r z`|){lZS2~dZY#K8@)1TUEkF(aH=4zbfLb0. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_start.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_start.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:015f test_round1 -00:0186 _wait_ly_4 -00:018c _wait_ly_5 +00:0186 test_round1@wait_ly_5 +00:018c test_round1@wait_ly_6 00:019c fail_round1 -00:01b0 _wait_ly_6 -00:01b6 _wait_ly_7 -00:01cc _print_results_halt_1 -00:01cf _test_failure_cb_0 -00:01d7 _print_sl_data55 -00:01ed _print_sl_out55 -00:01f0 finish_round1 -00:01fd test_round2 -00:022a _wait_ly_8 -00:0230 _wait_ly_9 -00:0240 fail_round2 -00:0254 _wait_ly_10 -00:025a _wait_ly_11 -00:0270 _print_results_halt_2 -00:0273 _test_failure_cb_1 -00:027b _print_sl_data56 -00:0291 _print_sl_out56 -00:0294 finish_round2 -00:0299 test_finish -00:c014 vector_10 -00:c016 vector_38 -00:c018 round1_oam -00:c019 round1_b +00:01a3 fail_round1@quit_inline_1 +00:01c2 finish_round1 +00:01cf test_round2 +00:01fc test_round2@wait_ly_7 +00:0202 test_round2@wait_ly_8 +00:0212 fail_round2 +00:0219 fail_round2@quit_inline_2 +00:0238 finish_round2 +00:023d test_finish +00:ff91 vector_10 +00:ff93 vector_38 +00:ff95 round1_oam +00:ff96 round1_b + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 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index bcd8a4683..5c38cd42c 100644 --- a/cinema/gb/mooneye-gb/acceptance/oam_dma_timing/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/oam_dma_timing/test.sym @@ -1,199 +1,130 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/oam_dma_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0171 test_finish -00:01a1 hiram_test -00:01a6 _wait_ly_6 -00:01ac _wait_ly_7 -00:01bd _wait_ly_8 -00:01c3 _wait_ly_9 +00:01a8 hiram_test +00:01ad hiram_test@wait_ly_7 +00:01b3 hiram_test@wait_ly_8 +00:01c4 hiram_test@wait_ly_9 +00:01ca hiram_test@wait_ly_10 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 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"/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/pop_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/pop_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 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-01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:02ad test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +0000015d _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/manifest.yml b/cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/manifest.yml similarity index 100% rename from cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/manifest.yml rename to cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/manifest.yml diff --git a/cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.gb similarity index 95% rename from cinema/gb/mooneye-gb/acceptance/gpu/intr_2_0_timing/test.gb rename to cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.gb index aa8bd6e1310fb12ed9754983d399882e70a6bee0..f5109ff84a9be60b783bd1166d0e31fb5c3a6281 100644 GIT binary patch delta 1181 zcmZo@U}|V!+Th1nuf_WLgUi2ugO!gBTxGXq22 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a/cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.sym b/cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.sym new file mode 100644 index 000000000..d8b8c49b7 --- /dev/null +++ b/cinema/gb/mooneye-gb/acceptance/ppu/hblank_ly_scx_timing-GS/test.sym @@ -0,0 +1,100 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/hblank_ly_scx_timing-GS.gb". + +[labels] +01:4940 clear_vram +01:48ff disable_lcd_safe +01:4905 disable_lcd_safe@wait_ly_0 +01:4954 memcpy +01:495d memset +01:491d print_hex4 +01:494a print_hex8 +01:496d print_inline_string +01:4929 print_load_font +01:4935 print_newline +01:47f0 print_reg_dump +01:4966 print_string +01:4875 quit +01:488a quit@cb_return +01:488f quit@wait_ly_1 +01:4895 quit@wait_ly_2 +01:489b quit@wait_ly_3 +01:48a1 quit@wait_ly_4 +01:48ab quit@success +01:48d2 quit@failure +01:48e7 quit@halt +01:48e8 quit@halt_execution_0 +01:48eb reset_screen +01:490e serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 +00:0395 main@quit_inline_1 +00:03a6 test_fail +00:03ce test_fail@quit_inline_2 +00:03fc standard_delay +00:0414 setup_and_wait +00:0414 setup_and_wait@wait_ly_7 +00:041a setup_and_wait@wait_ly_8 +00:042e fail_halt +00:0435 fail_halt@quit_inline_3 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000256 _sizeof_main +00000056 _sizeof_test_fail +00000018 _sizeof_standard_delay +0000001a _sizeof_setup_and_wait diff --git a/cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/ppu/intr_1_2_timing-GS/baseline_0000.png new file mode 100644 index 0000000000000000000000000000000000000000..be650fa9ce32cdd5c050ca0db86ea4e159f26f1d GIT binary patch literal 1171 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|QHxr;B4q#hkZu?`~SGAi!3t z{r>-{cdg5NQWIQebUvQ`ZuZ>_KEDjdpMlR(Bh@ZEy?>X{L5D+({oo^o2pN{{=7d54 zopaf7PhEXnCs+IXaMZ64xBi8n z$+q6lxAgwA%covWe;a!=K=TxP+;4vN<6Cd-UcBRm_=#rG$Ez+*|EF(UwJ$hn(r2sx zUYuTMf*1VhboQTSf#y`dbob+1qywaS7EC)=@vFV=(?`4ANlGW#Eq}4@4v>*D+7^FQ z`~Kp`J&QMY#nt=gnyf7BSZTH)k*A{M$j+eKvsKPnxUGJnRC(^{<%j3iyB3Mts#a+4 zb5qP)xYQ(N#jkln=@Tbp7yMqoHNC1P@B35D!oCS#_Au*buyCerowd8a!=m@)-pUu9FTZTr`z!dZ(4Fbox`sT*EGJ#L z&Y^j*+5YQhDV|f->#GiFujDYgm$I{jQ&#GQ;9Z~Dw^sKv)=d7r`o*K#3D?h_Ui$Nf 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+01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 +00:01b2 setup_and_wait_mode1 +00:01b2 setup_and_wait_mode1@wait_ly_7 +00:01c5 setup_and_wait_mode2 +00:01d2 fail_halt +00:01d9 fail_halt@quit_inline_1 + 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"/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/lcdon_timing-dmgABCmgbS.gb". + +[labels] +01:4d03 clear_oam +01:4d0d clear_vram +01:4cc2 disable_lcd_safe +01:4cc8 disable_lcd_safe@wait_ly_0 +01:4d21 memcpy +01:4d2a memset +01:4ce0 print_hex4 +01:4d17 print_hex8 +01:4d3a print_inline_string +01:4cec print_load_font +01:4cf8 print_newline +01:4d33 print_string +01:4c38 quit +01:4c4d quit@cb_return +01:4c52 quit@wait_ly_1 +01:4c58 quit@wait_ly_2 +01:4c5e quit@wait_ly_3 +01:4c64 quit@wait_ly_4 +01:4c6e quit@success +01:4c95 quit@failure +01:4caa quit@halt +01:4cab quit@halt_execution_0 +01:4cae reset_screen +01:4cd1 serial_send_byte +01:4000 font +00:0150 main +00:015a test_ly +00:0166 test_stat_lyc0 +00:0175 test_stat_lyc1 +00:0185 test_oam_access +00:0191 test_vram_access +00:019d test_finish +00:01a4 test_finish@quit_inline_1 +01:4ac9 cycle_counts +01:4ae1 expect_ly +01:4afc expect_stat_lyc0 +01:4b1f expect_stat_lyc1 +01:4b42 expect_oam_access +01:4b65 expect_vram_access +01:4b89 verify_results +01:4ba0 verify_fail +01:4bc1 verify_fail@quit_inline_2 +00:ff80 v_pass1_results +00:ff88 v_pass2_results +00:ff90 v_pass3_results +00:ff98 v_fail_round +00:ff99 v_fail_expect +00:ff9a v_fail_actual +00:ff9b v_fail_str +00:ff9b v_fail_str_l +00:ff9c v_fail_str_h +01:47f0 test_passes +01:47f0 test_pass1 +01:48e2 test_pass2 +01:49d5 test_pass3 + +[definitions] +0000000a _sizeof_clear_oam +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000018 _sizeof_cycle_counts +0000001b _sizeof_expect_ly +00000023 _sizeof_expect_stat_lyc0 +00000023 _sizeof_expect_stat_lyc1 +00000023 _sizeof_expect_oam_access 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+fail: true diff --git a/cinema/gb/mooneye-gb/acceptance/ppu/lcdon_write_timing-GS/test.gb b/cinema/gb/mooneye-gb/acceptance/ppu/lcdon_write_timing-GS/test.gb new file mode 100644 index 0000000000000000000000000000000000000000..e79fc6238a607436ff4414de1b8cb10c93283e05 GIT binary patch literal 32768 zcmeI4QAk@?7=TZ%S$eD1-P9^qxzw99xF}X!DqC>3mz&!=%}p&znHz`?Hd)dZoXYC9 z*rjPwJJ_DK2Ol;Nwzs~`4aV3gjCRsu*50u`6jo><4lE_CrP8{tvL!ozj@M*;-qZYl zJm;SO{Qo)U|G#sN;De`B+TKEzh8;iOPb9AIB6T&V$Q-FBy9n=Y`|u;uaQph?-8*+~ zeRlEU@z`X;@7M3#{_OLM-ycxlnwpx7&&Ky3kIFOgQ!`|Alu&UTAp0kNePsP)T1^qF zF5)IdD`vWD!j>9#lMJ+FXg~7II+pH-EfTTx$ZK@GJam{elic>+2h1J`AOR$R1dsp{ zKmter2_OL^fCP{L5DYr&4W)o>Ynz=;!&pd;NY%s;yNN7%@IRKY!vxb8|%2^t6lsH#vi-LCBspeu^qTlq47j$?Dn zvZjGe6n#FOiq9vCp!2*a!rVMBNuVo=t~;HgD9h>c`L}glXKR4J-yaUAQf&ToTGLV~ zjCxhL|Bz7A z1@?;0c*FXc%)){_9x_j-q1JWqXFCi0RTXqeg45u1+Wv+S4i67cPlv;X0d`o43ClPX zip54oOfy6U?7AL}9z7a~^!Ky*CCR%fY=2pPYzFYJwsV}F|M0NA9@qt;zTWF)w{WRI8Igj`}_Jp12S-aqtUT3&_URpX8Che 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quit@wait_ly_3 +01:4919 quit@wait_ly_4 +01:4923 quit@success +01:494a quit@failure +01:495f quit@halt +01:4960 quit@halt_execution_0 +01:49b6 reset_screen +01:49d9 serial_send_byte +01:4000 font +00:0150 main +00:015a test_oam_access +00:0166 test_vram_access +00:0172 test_finish +00:0179 test_finish@quit_inline_1 +01:47f0 nop_counts +01:4803 expect_oam_access +01:4820 expect_vram_access +01:483e verify_results +01:4855 verify_fail +01:4876 verify_fail@quit_inline_2 +00:c000 v_test_code +00:c12c v_test_results +00:ff80 v_fail_round +00:ff81 v_fail_expect +00:ff82 v_fail_actual +00:ff83 v_fail_str +00:ff83 v_fail_str_l +00:ff84 v_fail_str_h +01:4963 run_tests +01:497c test_case +01:49b0 test_case_prologue +01:49b4 test_case_epilogue +01:49b6 test_case_end + +[definitions] +0000000a _sizeof_clear_oam +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000013 _sizeof_nop_counts +0000001d _sizeof_expect_oam_access +0000001e _sizeof_expect_vram_access +00000017 _sizeof_verify_results +00000098 _sizeof_verify_fail +0000012c _sizeof_v_test_code +00000013 _sizeof_v_test_results +00000001 _sizeof_v_fail_round +00000001 _sizeof_v_fail_expect +00000001 _sizeof_v_fail_actual +00000002 _sizeof_v_fail_str +00000001 _sizeof_v_fail_str_l +00000001 _sizeof_v_fail_str_h +00000019 _sizeof_run_tests +00000034 _sizeof_test_case +00000004 _sizeof_test_case_prologue +00000002 _sizeof_test_case_epilogue +00000000 _sizeof_test_case_end +0000000a _sizeof_main +0000000c _sizeof_test_oam_access +0000000c _sizeof_test_vram_access diff --git a/cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/baseline_0000.png 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HcmV?d00001 diff --git a/cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/test.sym b/cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/test.sym new file mode 100644 index 000000000..005ebb19a --- /dev/null +++ b/cinema/gb/mooneye-gb/acceptance/ppu/stat_irq_blocking/test.sym @@ -0,0 +1,102 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ppu/stat_irq_blocking.gb". + +[labels] +01:4940 clear_vram +01:48ff disable_lcd_safe +01:4905 disable_lcd_safe@wait_ly_0 +01:4954 memcpy +01:495d memset +01:491d print_hex4 +01:494a print_hex8 +01:496d print_inline_string +01:4929 print_load_font +01:4935 print_newline +01:47f0 print_reg_dump +01:4966 print_string +01:4875 quit +01:488a quit@cb_return +01:488f quit@wait_ly_1 +01:4895 quit@wait_ly_2 +01:489b quit@wait_ly_3 +01:48a1 quit@wait_ly_4 +01:48ab quit@success +01:48d2 quit@failure +01:48e7 quit@halt +01:48e8 quit@halt_execution_0 +01:48eb reset_screen +01:490e serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 test_round1 +00:0156 test_round1@wait_ly_5 +00:015c test_round1@wait_ly_6 +00:016b fail_round1 +00:0173 fail_round1@quit_inline_1 +00:018e test_round2 +00:0198 ly_iteration +00:01ae finish_round2 +00:01b6 finish_round2@quit_inline_2 +00:01c7 fail_round2 +00:01ec fail_round2@quit_inline_3 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000001 _sizeof_main +0000001a _sizeof_test_round1 +00000023 _sizeof_fail_round1 +0000000a _sizeof_test_round2 +00000016 _sizeof_ly_iteration +00000019 _sizeof_finish_round2 diff --git a/cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/ppu/stat_lyc_onoff/baseline_0000.png new file mode 100644 index 0000000000000000000000000000000000000000..f9e5e47b50a4d548ddbc988a8e76364d30f505cf GIT binary patch literal 528 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|VoAPZ!6KiaBquU(7mWz~FE( z<;Va1cWgxt&B%VfEU&=!xnok3TT$lH;@jICuivi!&oIyXfkoqEmOfz%KM+GNxySPP z*F*Dd<=5Z6-dB81|M;InsWNlk%!+)xcY&$;KG^WAfoyd*0tPe*=!I$@r96fxHm`}Wsj@zz#RS94mtFY3isq3+o8;d!y` z&aL5lckljq`P#MPgTvc?xpnu><&UpjZL{7U85tfrGqmq`!5kYpJtq44gp^pD*!R0` z*?!(q{FTIonnic{g84u`FPaami~gZm-}bjZ6pQ)gZ_?&c;#_QQ@o?o6uX5Y#eB z9p+8JQ&EXOA$)=n77wi+a6h;`OU(HAOHd&00JNY0w4eaAOHd&00JNY0w4ea zAOHd&00JNY0w4eaAOHd&00JNY0w4eaAOHd&00JNY0w4eaAOHd&00JNY0w4eaAOHd& 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+01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte +01:4000 font +00:0150 main +00:0158 round1 +00:015b round1@wait_ly_5 +00:0161 round1@wait_ly_6 +00:017f round1@quit_inline_1 +00:01a9 round1@quit_inline_2 +00:01d3 round1@quit_inline_3 +00:01ec round2 +00:01f0 round2@wait_ly_7 +00:01f6 round2@wait_ly_8 +00:0214 round2@quit_inline_4 +00:023e round2@quit_inline_5 +00:0268 round2@quit_inline_6 +00:0281 round3 +00:0285 round3@wait_ly_9 +00:028b round3@wait_ly_10 +00:02a7 round3@quit_inline_7 +00:02d1 round3@quit_inline_8 +00:02fb round3@quit_inline_9 +00:0314 round4 +00:0315 round4@wait_ly_11 +00:031b round4@wait_ly_12 +00:0337 round4@quit_inline_10 +00:035d round4@quit_inline_11 +00:0377 finish +00:037e finish@quit_inline_12 +00:038f fail_intr_round1 +00:0396 fail_intr_round1@quit_inline_13 +00:03ad fail_intr_round2 +00:03b4 fail_intr_round2@quit_inline_14 +00:03cb fail_intr_round3 +00:03d2 fail_intr_round3@quit_inline_15 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_main +00000094 _sizeof_round1 +00000095 _sizeof_round2 +00000093 _sizeof_round3 +00000063 _sizeof_round4 +00000018 _sizeof_finish +0000001e _sizeof_fail_intr_round1 +0000001e _sizeof_fail_intr_round2 diff --git a/cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/ppu/vblank_stat_intr-GS/baseline_0000.png new file mode 100644 index 0000000000000000000000000000000000000000..1574fdc6a64b6573e506495cf6091ae2cee7581f GIT binary patch literal 1206 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|QH~r;B4q#hkZuFHW0nz{Be6 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check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0169 fail_halt +00:0170 fail_halt@quit_inline_1 +00:017e test_round1 +00:018a test_round1@wait_ly_5 +00:01d5 finish_round1 +00:01f3 test_round2 +00:01ff test_round2@wait_ly_6 +00:024b finish_round2 +00:026d test_round3 +00:0279 test_round3@wait_ly_7 +00:02c4 finish_round3 +00:02e2 test_round4 +00:02ee test_round4@wait_ly_8 +00:033a finish_round4 +00:033c test_finish +00:ff91 intr_vec_vblank +00:ff94 intr_vec_stat +00:ff97 round1 +00:ff98 round2 +00:ff99 round3 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000003 _sizeof_intr_vec_vblank +00000003 _sizeof_intr_vec_stat +00000001 _sizeof_round1 +00000001 _sizeof_round2 +00000001 _sizeof_round3 +00000019 _sizeof_main +00000015 _sizeof_fail_halt +00000057 _sizeof_test_round1 +0000001e _sizeof_finish_round1 +00000058 _sizeof_test_round2 +00000022 _sizeof_finish_round2 +00000057 _sizeof_test_round3 +0000001e _sizeof_finish_round3 +00000058 _sizeof_test_round4 +00000002 _sizeof_finish_round4 diff --git a/cinema/gb/mooneye-gb/acceptance/push_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/push_timing/test.gb index b57ffa261007595fa41d9d04fab180de42126a30..b04fcf068acfb1b40918d2dc036392ff70a7e19b 100644 GIT binary patch delta 1123 zcmai!PiWIn9LHZebh7$qwRVJwTT;fXh_Zp83=LVjfA$RnQ`o?RimNgdH`X3z=S-$f zyT2)T+11m$b-KgwB1-6JC;>0t-(@|HCuQn}w*HbD+s=(W@_YHchE%z8q?;&DTi{O~tCO)66MG zTgfs$;k`(!6^~jlN3i)8_l55dMWW%+2(s32oDIQD2kEt%qGbX|KBeuDo7&w4y+&5ClsC#Zh!rC^}0DN6=Ft=q(o*&>~DK zlv+32u-S~wLCm8?gBPJG%3G~Gk1cVh4^|yLpwt~|IMVDp?-$3+tN1ZQ3}PJO3B&{h z>k|bD&N~hfvA>fa`ZX!PlxD)G0EwTG#MIwsE8J^3?E`Cd2w8ATFsd;?2xOa{zzS2k_XtbiLo}W`FcU a7W2E=pEXrWX+OL5*?faj#)`+)ci|61YQU}l delta 1440 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"/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/push_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/push_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0177 test_finish -00:01bb hiram_test -00:01c2 _wait_ly_6 -00:01c8 _wait_ly_7 -00:01e2 _wait_ly_8 -00:01e8 _wait_ly_9 +00:01c0 hiram_test +00:01c7 hiram_test@wait_ly_7 +00:01cd hiram_test@wait_ly_8 +00:01e7 hiram_test@wait_ly_9 +00:01ed hiram_test@wait_ly_10 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:018b test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +0000003b _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/ret_cc_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/ret_cc_timing/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/ret_cc_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/ret_cc_timing/test.gb index acb9f20cd2fead45846a61bb0dc0c08cae7e13dd..c6f0a0b2f3f8ec2f0e96fae7ee783d62c3a82de3 100644 GIT binary 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"/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/ret_cc_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:015c test_round1 -00:015c _wait_ly_4 -00:0162 _wait_ly_5 -00:017c _wait_ly_6 -00:0182 _wait_ly_7 +00:015c test_round1@wait_ly_5 +00:0162 test_round1@wait_ly_6 +00:017c test_round1@wait_ly_7 +00:0182 test_round1@wait_ly_8 00:0192 finish_round1 -00:01a9 _wait_ly_8 -00:01af _wait_ly_9 -00:01c5 _print_results_halt_1 -00:01c8 _test_failure_cb_0 -00:01d0 _print_sl_data55 -00:01de _print_sl_out55 -00:01e1 test_round2 -00:01e1 _wait_ly_10 -00:01e7 _wait_ly_11 -00:01fb _wait_ly_12 -00:0201 _wait_ly_13 -00:0212 finish_round2 -00:0229 _wait_ly_14 -00:022f _wait_ly_15 -00:0245 _print_results_halt_2 -00:0248 _test_failure_cb_1 -00:0250 _print_sl_data56 -00:025e _print_sl_out56 -00:0261 test_success -00:0275 _wait_ly_16 -00:027b _wait_ly_17 -00:0291 _print_results_halt_3 -00:0294 _test_ok_cb_0 -00:029c _print_sl_data57 -00:02a4 _print_sl_out57 -00:02a7 hiram_cb +00:019c finish_round1@quit_inline_1 +00:01b3 test_round2 +00:01b3 test_round2@wait_ly_9 +00:01b9 test_round2@wait_ly_10 +00:01cd test_round2@wait_ly_11 +00:01d3 test_round2@wait_ly_12 +00:01e4 finish_round2 +00:01ee finish_round2@quit_inline_2 +00:0205 test_success +00:020c test_success@quit_inline_3 +00:021d hiram_cb + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +0000000c _sizeof_main +00000036 _sizeof_test_round1 +00000021 _sizeof_finish_round1 +00000031 _sizeof_test_round2 +00000021 _sizeof_finish_round2 +00000018 _sizeof_test_success diff --git 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:015c test_round1 -00:015c _wait_ly_4 -00:0162 _wait_ly_5 -00:017c _wait_ly_6 -00:0182 _wait_ly_7 +00:015c test_round1@wait_ly_5 +00:0162 test_round1@wait_ly_6 +00:017c test_round1@wait_ly_7 +00:0182 test_round1@wait_ly_8 00:0193 finish_round1 -00:01aa _wait_ly_8 -00:01b0 _wait_ly_9 -00:01c6 _print_results_halt_1 -00:01c9 _test_failure_cb_0 -00:01d1 _print_sl_data55 -00:01df _print_sl_out55 -00:01e2 test_round2 -00:01e2 _wait_ly_10 -00:01e8 _wait_ly_11 -00:01fc _wait_ly_12 -00:0202 _wait_ly_13 -00:0214 finish_round2 -00:022b _wait_ly_14 -00:0231 _wait_ly_15 -00:0247 _print_results_halt_2 -00:024a _test_failure_cb_1 -00:0252 _print_sl_data56 -00:0260 _print_sl_out56 -00:0263 test_success -00:0277 _wait_ly_16 -00:027d _wait_ly_17 -00:0293 _print_results_halt_3 -00:0296 _test_ok_cb_0 -00:029e _print_sl_data57 -00:02a6 _print_sl_out57 -00:02a9 hiram_cb +00:019d finish_round1@quit_inline_1 +00:01b4 test_round2 +00:01b4 test_round2@wait_ly_9 +00:01ba test_round2@wait_ly_10 +00:01ce test_round2@wait_ly_11 +00:01d4 test_round2@wait_ly_12 +00:01e6 finish_round2 +00:01f0 finish_round2@quit_inline_2 +00:0207 test_success +00:020e test_success@quit_inline_3 +00:021f hiram_cb + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +0000000c _sizeof_main +00000037 _sizeof_test_round1 +00000021 _sizeof_finish_round1 +00000032 _sizeof_test_round2 +00000021 _sizeof_finish_round2 +00000018 _sizeof_test_success diff --git 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b/cinema/gb/mooneye-gb/acceptance/reti_intr_timing/test.sym @@ -1,192 +1,122 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_intr_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_intr_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0160 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000010 _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/reti_timing/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/reti_timing/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/reti_timing/test.gb b/cinema/gb/mooneye-gb/acceptance/reti_timing/test.gb index d9027634381da679912063c20077082f83652bf1..0eaf8f63603f00caee2f81cfd4489497ad1001d1 100644 GIT binary patch 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b/cinema/gb/mooneye-gb/acceptance/reti_timing/test.sym index cc3bd7b43..02ea4c17b 100644 --- a/cinema/gb/mooneye-gb/acceptance/reti_timing/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/reti_timing/test.sym @@ -1,223 +1,64 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/reti_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:015c test_round1 -00:015c _wait_ly_4 -00:0162 _wait_ly_5 -00:017c _wait_ly_6 -00:0182 _wait_ly_7 +00:015c test_round1@wait_ly_5 +00:0162 test_round1@wait_ly_6 +00:017c test_round1@wait_ly_7 +00:0182 test_round1@wait_ly_8 00:0193 finish_round1 -00:01aa _wait_ly_8 -00:01b0 _wait_ly_9 -00:01c6 _print_results_halt_1 -00:01c9 _test_failure_cb_0 -00:01d1 _print_sl_data55 -00:01df _print_sl_out55 -00:01e2 test_round2 -00:01e2 _wait_ly_10 -00:01e8 _wait_ly_11 -00:01fc _wait_ly_12 -00:0202 _wait_ly_13 -00:0214 finish_round2 -00:022b _wait_ly_14 -00:0231 _wait_ly_15 -00:0247 _print_results_halt_2 -00:024a _test_failure_cb_1 -00:0252 _print_sl_data56 -00:0260 _print_sl_out56 -00:0263 test_success -00:0277 _wait_ly_16 -00:027d _wait_ly_17 -00:0293 _print_results_halt_3 -00:0296 _test_ok_cb_0 -00:029e _print_sl_data57 -00:02a6 _print_sl_out57 -00:02a9 hiram_cb +00:019d finish_round1@quit_inline_1 +00:01b4 test_round2 +00:01b4 test_round2@wait_ly_9 +00:01ba test_round2@wait_ly_10 +00:01ce test_round2@wait_ly_11 +00:01d4 test_round2@wait_ly_12 +00:01e6 finish_round2 +00:01f0 finish_round2@quit_inline_2 +00:0207 test_success +00:020e test_success@quit_inline_3 +00:021f hiram_cb + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +0000000c _sizeof_main +00000037 _sizeof_test_round1 +00000021 _sizeof_finish_round1 +00000032 _sizeof_test_round2 +00000021 _sizeof_finish_round2 +00000018 _sizeof_test_success diff --git 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wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/rst_timing.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/rst_timing.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0151 _wait_ly_4 -00:0157 _wait_ly_5 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0151 main@wait_ly_5 +00:0157 main@wait_ly_6 00:0177 test_finish -00:01bb hiram_test -00:01be _wait_ly_6 -00:01c4 _wait_ly_7 -00:01d9 finish_round1 -00:01dc _wait_ly_8 -00:01e2 _wait_ly_9 -00:01f8 finish_round2 +00:01c0 hiram_test +00:01c3 hiram_test@wait_ly_7 +00:01c9 hiram_test@wait_ly_8 +00:01de finish_round1 +00:01e1 finish_round1@wait_ly_9 +00:01e7 finish_round1@wait_ly_10 +00:01fd finish_round2 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000027 _sizeof_main +00000049 _sizeof_test_finish +0000001e _sizeof_hiram_test +0000001f _sizeof_finish_round1 diff --git a/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sav b/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sav deleted file mode 100644 index e69de29bb..000000000 diff --git a/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sym b/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sym deleted file mode 100644 index f266d3b95..000000000 --- a/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.sym +++ /dev/null @@ -1,198 +0,0 @@ -; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/serial/boot_sclk_align-dmgABCXmgb.gb". - -[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:3828 _wait_ly_4 -00:382e _wait_ly_5 -00:3844 _print_results_halt_1 -00:3847 _test_failure_cb_0 -00:384f _print_sl_data55 -00:385e _print_sl_out55 -00:3861 test_finish diff --git a/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/manifest.yml b/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/manifest.yml new file mode 100644 index 000000000..a697ada66 --- /dev/null +++ b/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/manifest.yml @@ -0,0 +1 @@ +fail: true diff --git a/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.gb b/cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCmgb/test.gb similarity index 93% rename from cinema/gb/mooneye-gb/acceptance/serial/boot_sclk_align-dmgABCXmgb/test.gb rename to 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-0,0 +1,123 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/serial/boot_sclk_align-dmgABCmgb.gb". + +[labels] +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:381b main@quit_inline_1 +00:3833 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +000036e3 _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/timer/div_write/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/timer/div_write/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/acceptance/timer/div_write/test.gb b/cinema/gb/mooneye-gb/acceptance/timer/div_write/test.gb index 60f4ec3257fad5408d07ecb9454c315af46344a8..33adee403fdf80ca73f96bd1413386a96cb495aa 100644 GIT binary patch delta 314 zcmZo@U}|V!nh?m;#yFXgY3(FNKPH1slLHv#R6i@0G9Lcmes+n+*-IWFsl_D<{@x5? z3@1M;_9DbLzh@M*n^+LD$>9Tgy&=N`MplobPtR6)oK5pMJHtbfVa7>ChySPleQ^2L zukZ^R{&tq|uNA zgT&wU51bx2Kk$Cwm1!sVz`^d%1NX!0JwUeBoq$+)df&+hjCPF=nAY1e0D;2KlZpZj zf(#CfAJ`A?^r(F%|4!bfHUEOjNkxVRMh1oThYxvFY&;>QB+M=GJsilYQsS2Q!Nt7% Ugp$P1gJ(~B96h<2kx9cG0B0zR*8l(j delta 1450 zcma)*Ur19?9LLY^PTkyQIZUdAW{la4{}KmFPBRYR8PeoqQIgC1?Ht@=g;oJQ4fvna=+hw&*%F)XS;=h zR47Q(XQdUGnTN%DFf7^LnKRI#S%;F=$)vTL4&qsB9)giwvs@Y|-@!JyPGfugA@rKh35evzGY*hPervaqHRFZDin~f(@xqLjELl#!)yN6zFkG>l2h9#Eq zMRU1$HlNB2i%>WIC_;k&kQ#^wZ%+y5wVLxdneFP~|<_1^G#qM#vqPmn6}q!@y8d?`gr1nF~-SBS5XqpL6{Sxhjem=sJp^#cx~M}3hrEHWt#AXw#J z(1u#lu+M3D$^A;fJElaz7b-PHG?-(AiPCiYQXGMo-MJ{UhAoAUzG3aB|4td8KtXQ&4N@TdKYL#ri$ZAeD iR-L`?_yZ#P*s. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/div_write.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/div_write.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48af clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48b9 memcpy +01:48c2 memset +01:48d2 print_inline_string +01:4898 print_load_font +01:48a4 print_newline +01:48cb print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:0150 test -00:0182 _wait_ly_4 -00:0188 _wait_ly_5 -00:019e _print_results_halt_1 -00:01a1 _test_ok_cb_0 -00:01a9 _print_sl_data55 -00:01b1 _print_sl_out55 -00:01b4 test_failure -00:01c8 _wait_ly_6 -00:01ce _wait_ly_7 -00:01e4 _print_results_halt_2 -00:01e7 _test_failure_cb_0 -00:01ef _print_sl_data56 -00:01fa _print_sl_out56 +00:0175 test@quit_inline_1 +00:0186 quit_failure +00:018d quit_failure@quit_inline_2 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000000 _sizeof_test +00000036 _sizeof_main diff --git a/cinema/gb/mooneye-gb/acceptance/timer/rapid_toggle/test.gb b/cinema/gb/mooneye-gb/acceptance/timer/rapid_toggle/test.gb index 95522c15d70fd7b0f66b52d734893771579f6913..53145176bb3b9aebe568ad37af0fd17e2b004f39 100644 GIT binary patch delta 1094 zcmZo@U}|V!nh?k|fpPLj#QJS_y6-O928HPJ4qjy1_Iy_SD3~Y{|~*mH6rvOY%T^H-~ltB-T%V`LIwc+4-Bkoutp!4#y0;C{e(1v^c^nn z76wO}BQSEMfUznK=D9(6!oonOK@>QlC~!t7sE4U=K~dp~PytimfuaDI5x_Qr?Kla{ z0E|byjy^qW<$YGo`)rE0BEyW6iVpuz|NG$buV3L8kemP};q0pA3hHdke600i9CEyB zqIyaW6=yxYD}lHQh^v9P28e5cSVGjn&Iw4PAqNJDzv~}3J#c>D{lLpk@PUKfp9k)T ztGz+C)}4S@czWN-2aI-&517{5G5~?X&y&yi|8ZF`9b-Rcpmb7Eph1wq)q(K?`{91? z+Gq0bFQ}YUWN2VyP*{I>hWFRg=4T_kKOT$b U`3WV7p9jw_^genLn4^PC0N>57hyVZp delta 1447 zcmZvcQD{?F7{||d(>7@m+s4~WsFI! zyMg&4zPS0YK8-RMgFy+KgR(u8%Zk#=Pa{IBM{7rN?RNXdJ?KyUHn9=3F8sPaoX{i2 z>p5J_CnClh;jHp*eP_gYIp)M!6&SCrZD!-F1xt)p*zMQr|83V@b!zp=`c%D8Kb(ry zCsJ?g*|mY(mMN>b4@_zOZ_F68;c8Ay8ZKqB`En&wDl?Cp;yo_z&5*s49D^FwMAGGQ zrc}unXH`)$KfjXv7z^Ppl|(C}=Uc-3l&6xdpvR`a@GSV94PZ4T7qABos)aJ00lW-s}dJS;S+^OUt$dJ_142trD zgPb+NE;hsVAITU(;f(a-oDCWy7JNyvyI4SiF#wlIhPZq&w}8w=^0XNSKgzv=$&lIW zGyjynWWqWrh5VbOLW+}V$a>B#=9V#Gle9L;AaIz*5eWfIi24aTq~A%{O-dz*16>yCPROn20X;4k9&NDnJU zd!1DOQY$>J-3s0sO*lHFO>u-hoTsr3@iW>172lfaSh|iOI-E1DPVJ. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/rapid_toggle.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/rapid_toggle.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test -00:0186 _wait_ly_4 -00:018c _wait_ly_5 -00:01a2 _print_results_halt_1 -00:01a5 _test_failure_cb_0 -00:01ad _print_sl_data55 -00:01bb _print_sl_out55 -00:01be test_finish +00:0179 test@quit_inline_1 +00:0190 test_finish + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000000 _sizeof_test diff --git a/cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/timer/tim00_div_trigger/baseline_0000.png index 4776438956f1106f4ee1cf646921c699f7f1e237..1ee21b2aed704f04063ac8a58c940925d991869a 100644 GIT binary patch delta 1012 zcmV_mZKmL1#wUQ|Cil|>@ps0T7_oP-c-FzGSRlR z1VvDnbzKYS^5@eDz+4b44uZu&us8@72f^YXSe#cWWm%T`J)~K@EDO!+B)r~#s*jzU zKKJI7HPr4`b8qNaZY%zmv#jgd+L}k%+x_4@aZAq?i=`pbUw>{**hv*CKPC9IByIos zp3?l)#I$mExyPl~8C&t;RX>^A+TUKg((iM$ayqg9lbI?-dBRdWa-pSD~I0Un6sKjlr8RHj@-IvE{^3a)pdZT1A@-uII(U0v(}l{n|<(r^psPCt2?`tX%IB-m#tcI9wz@t^89ll5572i&TAdA?chKj-EXbj4n94}8qbqoNIbs~?~EgLXn(M|+T-oZ@+;>o*EaW|wEj*Ry^>WPa>dT1Z(Q`VNZJn0 zMyhuCEi#Uau0d{vYGtxpTt}YHf!6PD&OqvN1LM#RlRyL(f9FSV!hX$c`8<*HYtgOC ztx@;tI2VKi@BWL5_Bi(a?Z?rL*N4M7^Dgc89o5fQ2F10e-^MRb=!gF`eoAm_#Ddw| z)B3+tsha!H+IVl0AHn~++XS7CY8o5fg|@6#Xi1vUY=9Q^4=sf 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000000 _sizeof_test diff --git a/cinema/gb/mooneye-gb/acceptance/timer/tim01/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/timer/tim01/baseline_0000.png index 2edb1ad917967098e3b6d7101c32ac33e89f8613..4c3588c0f922ee20105b6fa27a35e5ec6f525bae 100644 GIT binary patch delta 1026 zcmV+d1pWKD39Si`B!6^CL_t(|ob8>_cB3#11Lv5y-TSLQgOYy&)X`biO+T6=tZwJfFB|T>>rh>@&a({Eel~f_~*MbjQ()!J1 zPIIb>Y31s2_e;+oEX9XUer2xf`uf_m{yKXrhcnkFnW@s0H+HJiGg;ywSR4e4gJ5wGEDnOjL9jTDCpyxqpwyXx z8ONnWy*W?blYeR@pWsD~cEK)~rJ+i>@G2v&UocY*d&;)4i(bA@shV`M#8fG4crpD_ zntCS4l3T{y5C`SoPj44((zz`=uB^jy=b0dmJ<9#G2=@BI>+0mbVz`dq5c~!z`Nv_% zKKT5%EtQttuLCqWfAv8rpZHgj1l{hy3&z3XH131*>wiJx;5@1Sf|KRNpzFQw*_HIr zxDPIkS+7z#Na;Ves*J7MqE+I%EMf%h?(y4CKxyJb>yN4@V7Ix@A%YOme~a3?Koy7f4Mj)Ox{$#Y)uP<96d9S7fYkQF4)p~P)B-~!`daasg#y1vc>jsBzD zO5~o89|l|>>iaIpk%-qt=SdGGWn<>!SZ^LgZ$drT{Ms(#%Ny3$`E4kyze9S@WF>1g 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information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim01.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed 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_print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000000 _sizeof_test diff --git a/cinema/gb/mooneye-gb/acceptance/timer/tim10/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/timer/tim10/baseline_0000.png index 4776438956f1106f4ee1cf646921c699f7f1e237..1ee21b2aed704f04063ac8a58c940925d991869a 100644 GIT binary patch delta 1012 zcmV_mZKmL1#wUQ|Cil|>@ps0T7_oP-c-FzGSRlR z1VvDnbzKYS^5@eDz+4b44uZu&us8@72f^YXSe#cWWm%T`J)~K@EDO!+B)r~#s*jzU zKKJI7HPr4`b8qNaZY%zmv#jgd+L}k%+x_4@aZAq?i=`pbUw>{**hv*CKPC9IByIos zp3?l)#I$mExyPl~8C&t;RX>^A+TUKg((iM$ayqg9lbI?-dBRdWa-pSD~I0Un6sKjlr8RHj@-IvE{^3a)pdZT1A@-uII(U0v(}l{n|<(r^psPCt2?`tX%IB-m#tcI9wz@t^89ll5572i&TAdA?chKj-EXbj4n94}8qbqoNIbs~?~EgLXn(M|+T-oZ@+;>o*EaW|wEj*Ry^>WPa>dT1Z(Q`VNZJn0 zMyhuCEi#Uau0d{vYGtxpTt}YHf!6PD&OqvN1LM#RlRyL(f9FSV!hX$c`8<*HYtgOC ztx@;tI2VKi@BWL5_Bi(a?Z?rL*N4M7^Dgc89o5fQ2F10e-^MRb=!gF`eoAm_#Ddw| z)B3+tsha!H+IVl0AHn~++XS7CY8o5fg|@6#Xi1vUY=9Q^4=sf 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z-k@K=NSS&<48ZejD?thv=`@j7v9I8xYcXeNj5BAczDQA=u$1_-tVEYh}?)I-KmSr180{6=i` zw}Y&!LkqhX8jc}h)wUW6Xd;Zt_gL!^XOC4O6-lkHT@KiZkU$5JE}Do*P-vke~X-;O#lD@ diff --git a/cinema/gb/mooneye-gb/acceptance/timer/tim10/test.sym b/cinema/gb/mooneye-gb/acceptance/timer/tim10/test.sym index bcb8a2318..68a19ff09 100644 --- a/cinema/gb/mooneye-gb/acceptance/timer/tim10/test.sym +++ b/cinema/gb/mooneye-gb/acceptance/timer/tim10/test.sym @@ -1,192 +1,122 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim10.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tim10.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000000 _sizeof_test diff --git a/cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/baseline_0000.png b/cinema/gb/mooneye-gb/acceptance/timer/tim10_div_trigger/baseline_0000.png index 5452e96cc5d06376380b0992801c3fa3299f3364..02a54c8140d190d082ceda4689c2b122753c1fb0 100644 GIT binary patch delta 1002 zcmV_J4A7!bYl)`IO+(lC=Hj z`Xm@XD`>+uGhN4uZu&us8@72f^YXSR4e4)7jCHHUmn7 z85HBV3{mg;$$v*uHS!5Q$k8v@h2qeVWB2Eb`3uEV!*L1z`c{O5GGvmK;1!Oz9V?rf+#&sv1|cGIL1{FI4&UiG$Ds2P0o zB+F<=zN?2cP*ESNgn>-UWVKf>1Gtl(vf|hUn9LF|`y{I)&vdAn^Xr&}IOvfByr3N{ zPQ-Tb@qb{}J>)eWWEYKg@HJ}f;85eiY5utNJia;DaBK%}w_X04%S?=sldK!^oW~Tw zgR6S12ERKV+!!HdfsWV?j@F=j#JF#bpzYv$CfxQ9F_G$|JA3p#m#)IXd9g}YaGm}mP4Qx)7=O(4fC4nQ?6#3r1 zc3z%SiSpc}VyN-0=KkEIG$+q_OsS$>uFQAYYW5x3!|MzJgJ|H?TRIkhZ-5n)IspL^f5H9Ah% z0p%xldp@5Dbou#o0~GZImdH!-@5A3sR(bKOl9ywDQRavAoTVp$Me)UW z@EX~##<7PgFGZe@ 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f 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"/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tma_write_reloading.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/acceptance/timer/tma_write_reloading.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main 00:0150 test + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000000 _sizeof_test diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/manifest.yml b/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/manifest.yml new file mode 100644 index 000000000..a697ada66 --- /dev/null +++ b/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/manifest.yml @@ -0,0 +1 @@ +fail: true diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/test.gb b/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.gb similarity index 96% rename from cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/test.gb rename to cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.gb index 0ae17db5445181d59715f1542e4dd84e756d130f..6117c265b578f74acc6ae49bf2fd4814cea11e5e 100644 GIT binary patch delta 983 zcmZo@U}Hbq4;0E z_Ep3GnpchgpPDfUzGXc7m+=-G)5E7`Tp$HNjsw%fnyuOjH`l*v`oA8i8>*&_=~vT# zuwe?V`E|=RSb@qVn4yxZL6SB=4fP6VKP#SLJp94^>^_gP-#kK6i%S&zy&1$9PD;+5 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a/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.sym b/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.sym new file mode 100644 index 000000000..3abf1f926 --- /dev/null +++ b/cinema/gb/mooneye-gb/emulator-only/mbc1/bits_ram_en/test.sym @@ -0,0 +1,84 @@ +; this file was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/bits_ram_en.gb". + +[labels] +01:48c9 clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:4898 memcmp +01:48dd memcpy +01:48e6 memset +01:48a6 print_hex4 +01:48d3 print_hex8 +01:48f6 print_inline_string +01:48b2 print_load_font +01:48be print_newline +01:48ef print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte +01:4000 font +00:0150 main +00:0164 test_round1 +00:018e test_round2 +00:01ae test_round2@expect_enabled +00:01b3 test_round2@expect_disabled +00:01cc test_round2@quit_inline_1 +00:01dd ram_data_enabled +00:01ed ram_data_disabled +00:01fd compare_ram_data +00:0206 fail_round1_disable +00:020d fail_round1_disable@quit_inline_2 +00:0240 fail_round1_enable +00:0247 fail_round1_enable@quit_inline_3 +00:0279 fail_round1_print_test_address +00:0286 fail_round2_disable +00:028d fail_round2_disable@quit_inline_4 +00:02ab fail_round2_expect +00:02b2 fail_round2_expect@quit_inline_5 +00:2000 ram_en_expectations +00:ff80 test_address +00:ff80 test_address_l +00:ff81 test_address_h +00:ff82 ram_en_value + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +0000000e _sizeof_memcmp +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000002 _sizeof_test_address +00000001 _sizeof_test_address_l +00000001 _sizeof_test_address_h +00000001 _sizeof_ram_en_value +00000014 _sizeof_main +0000002a _sizeof_test_round1 +0000004f _sizeof_test_round2 +00000010 _sizeof_ram_data_enabled +00000010 _sizeof_ram_data_disabled +00000009 _sizeof_compare_ram_data +0000003a _sizeof_fail_round1_disable +00000039 _sizeof_fail_round1_enable +0000000d _sizeof_fail_round1_print_test_address +00000025 _sizeof_fail_round2_disable +00001d55 _sizeof_fail_round2_expect diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/multicart_rom_8Mb/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 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"/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/multicart_rom_8Mb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/multicart_rom_8Mb.gb". [labels] -01:4001 print_load_font -01:400e print_string -01:4018 print_a -01:4022 print_newline -01:402d print_digit -01:403a print_regs -01:4043 _print_sl_data0 -01:4049 _print_sl_out0 -01:4056 _print_sl_data1 -01:405c _print_sl_out1 -01:406e _print_sl_data2 -01:4074 _print_sl_out2 -01:4081 _print_sl_data3 -01:4087 _print_sl_out3 -01:4099 _print_sl_data4 -01:409f _print_sl_out4 -01:40ac _print_sl_data5 -01:40b2 _print_sl_out5 -01:40c4 _print_sl_data6 -01:40ca _print_sl_out6 -01:40d7 _print_sl_data7 -01:40dd _print_sl_out7 +01:40cc clear_vram +01:408b disable_lcd_safe +01:4091 disable_lcd_safe@wait_ly_0 +01:40e0 memcpy +01:40e9 memset +01:40a9 print_hex4 +01:40d6 print_hex8 +01:40f9 print_inline_string +01:40b5 print_load_font +01:40c1 print_newline +01:40f2 print_string +01:4001 quit +01:4016 quit@cb_return +01:401b quit@wait_ly_1 +01:4021 quit@wait_ly_2 +01:4027 quit@wait_ly_3 +01:402d quit@wait_ly_4 +01:4037 quit@success +01:405e quit@failure +01:4073 quit@halt +01:4074 quit@halt_execution_0 +01:4077 reset_screen +01:409a serial_send_byte 01:4134 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:4924 memcpy -01:492d memset -01:4936 memcmp -01:4944 clear_vram -01:494e clear_oam -01:4958 disable_lcd_safe -01:495e _wait_ly_0 -01:4964 _wait_ly_1 -01:496d reset_screen -01:4981 process_results -01:4995 _wait_ly_2 -01:499b _wait_ly_3 -01:49b1 _print_results_halt_0 -01:49b4 _process_results_cb -01:49bf _print_sl_data8 -01:49c9 _print_sl_out8 -01:49e3 _print_sl_data9 -01:49ee _print_sl_out9 -01:4a06 _print_sl_data10 -01:4a12 _print_sl_out10 -01:4a13 dump_mem -01:4a32 _dump_mem_line -01:4a5c _check_asserts -01:4a6a _print_sl_data11 -01:4a6d _print_sl_out11 -01:4a79 _print_sl_data12 -01:4a7b _print_sl_out12 -01:4a83 _print_sl_data13 -01:4a86 _print_sl_out13 -01:4a90 __check_assert_fail0 -01:4a9b _print_sl_data14 -01:4a9e _print_sl_out14 -01:4aa1 __check_assert_ok0 -01:4aa9 _print_sl_data15 -01:4aae _print_sl_out15 -01:4ab0 __check_assert_skip0 -01:4ab8 _print_sl_data16 -01:4ac0 _print_sl_out16 -01:4ac0 __check_assert_out0 -01:4acc _print_sl_data17 -01:4ace _print_sl_out17 -01:4ad6 _print_sl_data18 -01:4ad9 _print_sl_out18 -01:4ae3 __check_assert_fail1 -01:4aee _print_sl_data19 -01:4af1 _print_sl_out19 -01:4af4 __check_assert_ok1 -01:4afc _print_sl_data20 -01:4b01 _print_sl_out20 -01:4b03 __check_assert_skip1 -01:4b0b _print_sl_data21 -01:4b13 _print_sl_out21 -01:4b13 __check_assert_out1 -01:4b1e _print_sl_data22 -01:4b21 _print_sl_out22 -01:4b2d _print_sl_data23 -01:4b2f _print_sl_out23 -01:4b37 _print_sl_data24 -01:4b3a _print_sl_out24 -01:4b44 __check_assert_fail2 -01:4b4f _print_sl_data25 -01:4b52 _print_sl_out25 -01:4b55 __check_assert_ok2 -01:4b5d _print_sl_data26 -01:4b62 _print_sl_out26 -01:4b64 __check_assert_skip2 -01:4b6c _print_sl_data27 -01:4b74 _print_sl_out27 -01:4b74 __check_assert_out2 -01:4b80 _print_sl_data28 -01:4b82 _print_sl_out28 -01:4b8a _print_sl_data29 -01:4b8d _print_sl_out29 -01:4b97 __check_assert_fail3 -01:4ba2 _print_sl_data30 -01:4ba5 _print_sl_out30 -01:4ba8 __check_assert_ok3 -01:4bb0 _print_sl_data31 -01:4bb5 _print_sl_out31 -01:4bb7 __check_assert_skip3 -01:4bbf _print_sl_data32 -01:4bc7 _print_sl_out32 -01:4bc7 __check_assert_out3 -01:4bd2 _print_sl_data33 -01:4bd5 _print_sl_out33 -01:4be1 _print_sl_data34 -01:4be3 _print_sl_out34 -01:4beb _print_sl_data35 -01:4bee _print_sl_out35 -01:4bf8 __check_assert_fail4 -01:4c03 _print_sl_data36 -01:4c06 _print_sl_out36 -01:4c09 __check_assert_ok4 -01:4c11 _print_sl_data37 -01:4c16 _print_sl_out37 -01:4c18 __check_assert_skip4 -01:4c20 _print_sl_data38 -01:4c28 _print_sl_out38 -01:4c28 __check_assert_out4 -01:4c34 _print_sl_data39 -01:4c36 _print_sl_out39 -01:4c3e _print_sl_data40 -01:4c41 _print_sl_out40 -01:4c4b __check_assert_fail5 -01:4c56 _print_sl_data41 -01:4c59 _print_sl_out41 -01:4c5c __check_assert_ok5 -01:4c64 _print_sl_data42 -01:4c69 _print_sl_out42 -01:4c6b __check_assert_skip5 -01:4c73 _print_sl_data43 -01:4c7b _print_sl_out43 -01:4c7b __check_assert_out5 -01:4c86 _print_sl_data44 -01:4c89 _print_sl_out44 -01:4c95 _print_sl_data45 -01:4c97 _print_sl_out45 -01:4c9f _print_sl_data46 -01:4ca2 _print_sl_out46 -01:4cac __check_assert_fail6 -01:4cb7 _print_sl_data47 -01:4cba _print_sl_out47 -01:4cbd __check_assert_ok6 -01:4cc5 _print_sl_data48 -01:4cca _print_sl_out48 -01:4ccc __check_assert_skip6 -01:4cd4 _print_sl_data49 -01:4cdc _print_sl_out49 -01:4cdc __check_assert_out6 -01:4ce8 _print_sl_data50 -01:4cea _print_sl_out50 -01:4cf2 _print_sl_data51 -01:4cf5 _print_sl_out51 -01:4cff __check_assert_fail7 -01:4d0a _print_sl_data52 -01:4d0d _print_sl_out52 -01:4d10 __check_assert_ok7 -01:4d18 _print_sl_data53 -01:4d1d _print_sl_out53 -01:4d1f __check_assert_skip7 -01:4d27 _print_sl_data54 -01:4d2f _print_sl_out54 -01:4d2f __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e 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@@ -1,194 +1,31 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/ram_256Kb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/ram_256Kb.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bd clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:4898 memcmp +01:48c7 memcpy +01:48d0 memset +01:48e0 print_inline_string +01:48a6 print_load_font +01:48b2 print_newline +01:48d9 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:0150 test_round1 00:016e test_round2 00:01d2 test_round3 @@ -196,57 +33,56 @@ 00:02a0 test_round5 00:02fc test_round6 00:0330 test_finish -00:0347 _wait_ly_4 -00:034d _wait_ly_5 -00:0363 _print_results_halt_1 -00:0366 _test_ok_cb_0 -00:036e _print_sl_data55 -00:0376 _print_sl_out55 -00:0379 copy_bank_data -00:0398 check_bank_data -00:03b8 all_ff -00:03c8 all_00 +00:033a test_finish@quit_inline_1 +00:034b copy_bank_data +00:036a check_bank_data +00:038a all_ff +00:039a all_00 00:1000 bank_data 00:1040 clear_ram 00:1062 fail_round1 -00:1079 _wait_ly_6 -00:107f _wait_ly_7 -00:1095 _print_results_halt_2 -00:1098 _test_failure_cb_0 -00:10a0 _print_sl_data56 -00:10ae _print_sl_out56 -00:10b1 fail_round2 -00:10c8 _wait_ly_8 -00:10ce _wait_ly_9 -00:10e4 _print_results_halt_3 -00:10e7 _test_failure_cb_1 -00:10ef _print_sl_data57 -00:10fd _print_sl_out57 -00:1100 fail_round3 -00:1117 _wait_ly_10 -00:111d _wait_ly_11 -00:1133 _print_results_halt_4 -00:1136 _test_failure_cb_2 -00:113e _print_sl_data58 -00:114c _print_sl_out58 -00:114f fail_round4 -00:1166 _wait_ly_12 -00:116c _wait_ly_13 -00:1182 _print_results_halt_5 -00:1185 _test_failure_cb_3 -00:118d _print_sl_data59 -00:119b _print_sl_out59 -00:119e fail_round5 -00:11b5 _wait_ly_14 -00:11bb _wait_ly_15 -00:11d1 _print_results_halt_6 -00:11d4 _test_failure_cb_4 -00:11dc _print_sl_data60 -00:11ea _print_sl_out60 -00:11ed fail_round6 -00:1204 _wait_ly_16 -00:120a _wait_ly_17 -00:1220 _print_results_halt_7 -00:1223 _test_failure_cb_5 -00:122b _print_sl_data61 -00:1239 _print_sl_out61 +00:106c fail_round1@quit_inline_2 +00:1083 fail_round2 +00:108d fail_round2@quit_inline_3 +00:10a4 fail_round3 +00:10ae fail_round3@quit_inline_4 +00:10c5 fail_round4 +00:10cf fail_round4@quit_inline_5 +00:10e6 fail_round5 +00:10f0 fail_round5@quit_inline_6 +00:1107 fail_round6 +00:1111 fail_round6@quit_inline_7 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +0000000e _sizeof_memcmp +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000000 _sizeof_test_round1 +0000001e _sizeof_main +00000064 _sizeof_test_round2 +00000060 _sizeof_test_round3 +0000006e _sizeof_test_round4 +0000005c _sizeof_test_round5 +00000034 _sizeof_test_round6 +0000001b _sizeof_test_finish +0000001f _sizeof_copy_bank_data +00000020 _sizeof_check_bank_data +00000010 _sizeof_all_ff +00000c66 _sizeof_all_00 +00000040 _sizeof_bank_data +00000022 _sizeof_clear_ram +00000021 _sizeof_fail_round1 +00000021 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bd clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:4898 memcmp +01:48c7 memcpy +01:48d0 memset +01:48e0 print_inline_string +01:48a6 print_load_font +01:48b2 print_newline +01:48d9 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 +00:0150 main 00:0150 test_round1 00:016e test_round2 00:01c2 test_round3 00:01cb test_round4 00:01fb test_round5 00:022c test_finish -00:0243 _wait_ly_4 -00:0249 _wait_ly_5 -00:025f _print_results_halt_1 -00:0262 _test_ok_cb_0 -00:026a _print_sl_data55 -00:0272 _print_sl_out55 -00:0275 copy_bank_data -00:028d check_bank_data -00:02a6 all_ff -00:02b6 all_00 +00:0236 test_finish@quit_inline_1 +00:0247 copy_bank_data +00:025f check_bank_data +00:0278 all_ff +00:0288 all_00 00:1000 bank_data 00:1010 clear_ram 00:1032 fail_round1 -00:1049 _wait_ly_6 -00:104f _wait_ly_7 -00:1065 _print_results_halt_2 -00:1068 _test_failure_cb_0 -00:1070 _print_sl_data56 -00:107e _print_sl_out56 -00:1081 fail_round2 -00:1098 _wait_ly_8 -00:109e _wait_ly_9 -00:10b4 _print_results_halt_3 -00:10b7 _test_failure_cb_1 -00:10bf _print_sl_data57 -00:10cd _print_sl_out57 -00:10d0 fail_round3 -00:10e7 _wait_ly_10 -00:10ed _wait_ly_11 -00:1103 _print_results_halt_4 -00:1106 _test_failure_cb_2 -00:110e _print_sl_data58 -00:111c _print_sl_out58 -00:111f fail_round4 -00:1136 _wait_ly_12 -00:113c _wait_ly_13 -00:1152 _print_results_halt_5 -00:1155 _test_failure_cb_3 -00:115d _print_sl_data59 -00:116b _print_sl_out59 -00:116e fail_round5 -00:1185 _wait_ly_14 -00:118b _wait_ly_15 -00:11a1 _print_results_halt_6 -00:11a4 _test_failure_cb_4 -00:11ac _print_sl_data60 -00:11ba _print_sl_out60 +00:103c fail_round1@quit_inline_2 +00:1053 fail_round2 +00:105d fail_round2@quit_inline_3 +00:1074 fail_round3 +00:107e fail_round3@quit_inline_4 +00:1095 fail_round4 +00:109f fail_round4@quit_inline_5 +00:10b6 fail_round5 +00:10c0 fail_round5@quit_inline_6 + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +0000000e _sizeof_memcmp +00000009 _sizeof_memcpy +00000009 _sizeof_memset +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000000 _sizeof_test_round1 +0000001e _sizeof_main +00000054 _sizeof_test_round2 +00000009 _sizeof_test_round3 +00000030 _sizeof_test_round4 +00000031 _sizeof_test_round5 +0000001b _sizeof_test_finish +00000018 _sizeof_copy_bank_data +00000019 _sizeof_check_bank_data +00000010 _sizeof_all_ff +00000d78 _sizeof_all_00 +00000010 _sizeof_bank_data +00000022 _sizeof_clear_ram +00000021 _sizeof_fail_round1 +00000021 _sizeof_fail_round2 +00000021 _sizeof_fail_round3 +00000021 _sizeof_fail_round4 diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_16Mb/baseline_0000.png index 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[labels] -01:4c00 print_load_font -01:4c0d print_string -01:4c17 print_a -01:4c21 print_newline -01:4c2c print_digit -01:4c39 print_regs -01:4c42 _print_sl_data0 -01:4c48 _print_sl_out0 -01:4c55 _print_sl_data1 -01:4c5b _print_sl_out1 -01:4c6d _print_sl_data2 -01:4c73 _print_sl_out2 -01:4c80 _print_sl_data3 -01:4c86 _print_sl_out3 -01:4c98 _print_sl_data4 -01:4c9e _print_sl_out4 -01:4cab _print_sl_data5 -01:4cb1 _print_sl_out5 -01:4cc3 _print_sl_data6 -01:4cc9 _print_sl_out6 -01:4cd6 _print_sl_data7 -01:4cdc _print_sl_out7 +01:48bc clear_vram +01:487b disable_lcd_safe +01:4881 disable_lcd_safe@wait_ly_0 +01:48d0 memcpy +01:48d9 memset +01:4899 print_hex4 +01:48c6 print_hex8 +01:48e9 print_inline_string +01:48a5 print_load_font +01:48b1 print_newline +01:48e2 print_string +01:47f1 quit +01:4806 quit@cb_return +01:480b quit@wait_ly_1 +01:4811 quit@wait_ly_2 +01:4817 quit@wait_ly_3 +01:481d quit@wait_ly_4 +01:4827 quit@success +01:484e quit@failure +01:4863 quit@halt +01:4864 quit@halt_execution_0 +01:4867 reset_screen +01:488a serial_send_byte 01:4001 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f1 memcpy -01:47fa memset -01:4803 memcmp -01:4811 clear_vram -01:481b clear_oam -01:4825 disable_lcd_safe -01:482b _wait_ly_0 -01:4831 _wait_ly_1 -01:483a reset_screen -01:484e process_results -01:4862 _wait_ly_2 -01:4868 _wait_ly_3 -01:487e _print_results_halt_0 -01:4881 _process_results_cb -01:488c _print_sl_data8 -01:4896 _print_sl_out8 -01:48b0 _print_sl_data9 -01:48bb _print_sl_out9 -01:48d3 _print_sl_data10 -01:48df _print_sl_out10 -01:48e0 dump_mem -01:48ff _dump_mem_line -01:4929 _check_asserts -01:4937 _print_sl_data11 -01:493a _print_sl_out11 -01:4946 _print_sl_data12 -01:4948 _print_sl_out12 -01:4950 _print_sl_data13 -01:4953 _print_sl_out13 -01:495d __check_assert_fail0 -01:4968 _print_sl_data14 -01:496b _print_sl_out14 -01:496e __check_assert_ok0 -01:4976 _print_sl_data15 -01:497b _print_sl_out15 -01:497d __check_assert_skip0 -01:4985 _print_sl_data16 -01:498d _print_sl_out16 -01:498d __check_assert_out0 -01:4999 _print_sl_data17 -01:499b _print_sl_out17 -01:49a3 _print_sl_data18 -01:49a6 _print_sl_out18 -01:49b0 __check_assert_fail1 -01:49bb _print_sl_data19 -01:49be _print_sl_out19 -01:49c1 __check_assert_ok1 -01:49c9 _print_sl_data20 -01:49ce _print_sl_out20 -01:49d0 __check_assert_skip1 -01:49d8 _print_sl_data21 -01:49e0 _print_sl_out21 -01:49e0 __check_assert_out1 -01:49eb _print_sl_data22 -01:49ee _print_sl_out22 -01:49fa _print_sl_data23 -01:49fc _print_sl_out23 -01:4a04 _print_sl_data24 -01:4a07 _print_sl_out24 -01:4a11 __check_assert_fail2 -01:4a1c _print_sl_data25 -01:4a1f _print_sl_out25 -01:4a22 __check_assert_ok2 -01:4a2a _print_sl_data26 -01:4a2f _print_sl_out26 -01:4a31 __check_assert_skip2 -01:4a39 _print_sl_data27 -01:4a41 _print_sl_out27 -01:4a41 __check_assert_out2 -01:4a4d _print_sl_data28 -01:4a4f _print_sl_out28 -01:4a57 _print_sl_data29 -01:4a5a _print_sl_out29 -01:4a64 __check_assert_fail3 -01:4a6f _print_sl_data30 -01:4a72 _print_sl_out30 -01:4a75 __check_assert_ok3 -01:4a7d _print_sl_data31 -01:4a82 _print_sl_out31 -01:4a84 __check_assert_skip3 -01:4a8c _print_sl_data32 -01:4a94 _print_sl_out32 -01:4a94 __check_assert_out3 -01:4a9f _print_sl_data33 -01:4aa2 _print_sl_out33 -01:4aae _print_sl_data34 -01:4ab0 _print_sl_out34 -01:4ab8 _print_sl_data35 -01:4abb _print_sl_out35 -01:4ac5 __check_assert_fail4 -01:4ad0 _print_sl_data36 -01:4ad3 _print_sl_out36 -01:4ad6 __check_assert_ok4 -01:4ade _print_sl_data37 -01:4ae3 _print_sl_out37 -01:4ae5 __check_assert_skip4 -01:4aed _print_sl_data38 -01:4af5 _print_sl_out38 -01:4af5 __check_assert_out4 -01:4b01 _print_sl_data39 -01:4b03 _print_sl_out39 -01:4b0b _print_sl_data40 -01:4b0e _print_sl_out40 -01:4b18 __check_assert_fail5 -01:4b23 _print_sl_data41 -01:4b26 _print_sl_out41 -01:4b29 __check_assert_ok5 -01:4b31 _print_sl_data42 -01:4b36 _print_sl_out42 -01:4b38 __check_assert_skip5 -01:4b40 _print_sl_data43 -01:4b48 _print_sl_out43 -01:4b48 __check_assert_out5 -01:4b53 _print_sl_data44 -01:4b56 _print_sl_out44 -01:4b62 _print_sl_data45 -01:4b64 _print_sl_out45 -01:4b6c _print_sl_data46 -01:4b6f _print_sl_out46 -01:4b79 __check_assert_fail6 -01:4b84 _print_sl_data47 -01:4b87 _print_sl_out47 -01:4b8a __check_assert_ok6 -01:4b92 _print_sl_data48 -01:4b97 _print_sl_out48 -01:4b99 __check_assert_skip6 -01:4ba1 _print_sl_data49 -01:4ba9 _print_sl_out49 -01:4ba9 __check_assert_out6 -01:4bb5 _print_sl_data50 -01:4bb7 _print_sl_out50 -01:4bbf _print_sl_data51 -01:4bc2 _print_sl_out51 -01:4bcc __check_assert_fail7 -01:4bd7 _print_sl_data52 -01:4bda _print_sl_out52 -01:4bdd __check_assert_ok7 -01:4be5 _print_sl_data53 -01:4bea _print_sl_out53 -01:4bec __check_assert_skip7 -01:4bf4 _print_sl_data54 -01:4bfc _print_sl_out54 -01:4bfc __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e _sizeof_run_test_suite +0000000e _sizeof_run_tests +0000000e _sizeof_run_test_cases +0000001d _sizeof_test_case +00000009 _sizeof_restore_mbc1 +00000011 _sizeof_switch_bank +0000001f _sizeof_fetch_expected_value diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.gb b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.gb index 9b638d49813c0fa0cb71abfb8fdac0f5e63dcf24..cbb4634e054545ecf03906660b1f5489d0b42c40 100644 GIT binary patch delta 591 zcmZ9IKWGzC9LL|gY7-l@J*462(7p>nT?`e4IHbqrl1rXVn~J8?(M38qSk$4W#=InT z5kcMT=As!K&e+94F4YeHc;DZj&+qYmKOSR2#)7Z% zxcu;giflO~;b(|P_r)vwVvd%*zFmNnV&S(}*{ySE~~laC8#v zbo6W{lR?U`56<;L+y`(E$n0F&B*rrx;K@{BJ~`u4pI7#I*l?|FbXBbKn62S|8DE68Pf7mT{aJ-;w{DZU910`X5;dN% zHN798VthJgdo0mo!0tNZDP0tQZL?--ib3t%$Pso`0en?t0^p9Ivt$46{GTTMHQg delta 1738 zcma)6U5Fc16uxJ&o6T-^yE~nAJFe25q^(4$vRWaw*qFb`PcyqIn=C0RRP;rx;)5V1 zwa)C14?-VA5Z0HqQfMCvrdp&eg*q50I}B3_1?_{Byy(LgZ3+vOK~vAYcV=kN2Zzk$ ze&0Fw`_8@R&KO3-Fd`S`K~Me?Bc}MO05^zpzZfGo#Y6}Uz;TRjA`;{U9HuXLZ+;#dE&&h z?#el33V!6V-LrT-yL(@uP|%4y3Aa7^MMfu)rc>Y^qr-F6ysD7yso9{M(J`xD=HiG;q|6N98{$b4?kP zc17i_q!l9u5T(_2v7i=rHNK80YqHP&jP>bbSU0tZrCeq)2`g9}ar9=`gu$*Y7R#O-1{)!9HZFvhFzF|Iqw z9PDGL2^G40K_w7nqY%{`K+Q25Ats4m%?a3I zIMBqZt=NPiLK?b5`1!U*dL%Ir56KU#qCM;E)$Cb0if_apGhtF49kx>Ar+XtW3D<|N z&&DkYvKrmOu%cwJ4Eh>90gFCW@F+<_6A9kabT2m>*2*01|HwHY@9W~_y--=D9Zo< diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.sym b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.sym index bfe04a18b..6c53eaf47 100644 --- a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.sym +++ b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_1Mb/test.sym @@ -1,226 +1,69 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_1Mb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_1Mb.gb". [labels] -01:4c00 print_load_font -01:4c0d print_string -01:4c17 print_a -01:4c21 print_newline -01:4c2c print_digit -01:4c39 print_regs -01:4c42 _print_sl_data0 -01:4c48 _print_sl_out0 -01:4c55 _print_sl_data1 -01:4c5b _print_sl_out1 -01:4c6d _print_sl_data2 -01:4c73 _print_sl_out2 -01:4c80 _print_sl_data3 -01:4c86 _print_sl_out3 -01:4c98 _print_sl_data4 -01:4c9e _print_sl_out4 -01:4cab _print_sl_data5 -01:4cb1 _print_sl_out5 -01:4cc3 _print_sl_data6 -01:4cc9 _print_sl_out6 -01:4cd6 _print_sl_data7 -01:4cdc _print_sl_out7 +01:48bc clear_vram +01:487b disable_lcd_safe +01:4881 disable_lcd_safe@wait_ly_0 +01:48d0 memcpy +01:48d9 memset +01:4899 print_hex4 +01:48c6 print_hex8 +01:48e9 print_inline_string +01:48a5 print_load_font +01:48b1 print_newline +01:48e2 print_string +01:47f1 quit +01:4806 quit@cb_return +01:480b quit@wait_ly_1 +01:4811 quit@wait_ly_2 +01:4817 quit@wait_ly_3 +01:481d quit@wait_ly_4 +01:4827 quit@success +01:484e quit@failure +01:4863 quit@halt +01:4864 quit@halt_execution_0 +01:4867 reset_screen +01:488a serial_send_byte 01:4001 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f1 memcpy -01:47fa memset -01:4803 memcmp -01:4811 clear_vram -01:481b clear_oam -01:4825 disable_lcd_safe -01:482b _wait_ly_0 -01:4831 _wait_ly_1 -01:483a reset_screen -01:484e process_results -01:4862 _wait_ly_2 -01:4868 _wait_ly_3 -01:487e _print_results_halt_0 -01:4881 _process_results_cb -01:488c _print_sl_data8 -01:4896 _print_sl_out8 -01:48b0 _print_sl_data9 -01:48bb _print_sl_out9 -01:48d3 _print_sl_data10 -01:48df _print_sl_out10 -01:48e0 dump_mem -01:48ff _dump_mem_line -01:4929 _check_asserts -01:4937 _print_sl_data11 -01:493a _print_sl_out11 -01:4946 _print_sl_data12 -01:4948 _print_sl_out12 -01:4950 _print_sl_data13 -01:4953 _print_sl_out13 -01:495d __check_assert_fail0 -01:4968 _print_sl_data14 -01:496b _print_sl_out14 -01:496e __check_assert_ok0 -01:4976 _print_sl_data15 -01:497b _print_sl_out15 -01:497d __check_assert_skip0 -01:4985 _print_sl_data16 -01:498d _print_sl_out16 -01:498d __check_assert_out0 -01:4999 _print_sl_data17 -01:499b _print_sl_out17 -01:49a3 _print_sl_data18 -01:49a6 _print_sl_out18 -01:49b0 __check_assert_fail1 -01:49bb _print_sl_data19 -01:49be _print_sl_out19 -01:49c1 __check_assert_ok1 -01:49c9 _print_sl_data20 -01:49ce _print_sl_out20 -01:49d0 __check_assert_skip1 -01:49d8 _print_sl_data21 -01:49e0 _print_sl_out21 -01:49e0 __check_assert_out1 -01:49eb _print_sl_data22 -01:49ee _print_sl_out22 -01:49fa _print_sl_data23 -01:49fc _print_sl_out23 -01:4a04 _print_sl_data24 -01:4a07 _print_sl_out24 -01:4a11 __check_assert_fail2 -01:4a1c _print_sl_data25 -01:4a1f _print_sl_out25 -01:4a22 __check_assert_ok2 -01:4a2a _print_sl_data26 -01:4a2f _print_sl_out26 -01:4a31 __check_assert_skip2 -01:4a39 _print_sl_data27 -01:4a41 _print_sl_out27 -01:4a41 __check_assert_out2 -01:4a4d _print_sl_data28 -01:4a4f _print_sl_out28 -01:4a57 _print_sl_data29 -01:4a5a _print_sl_out29 -01:4a64 __check_assert_fail3 -01:4a6f _print_sl_data30 -01:4a72 _print_sl_out30 -01:4a75 __check_assert_ok3 -01:4a7d _print_sl_data31 -01:4a82 _print_sl_out31 -01:4a84 __check_assert_skip3 -01:4a8c _print_sl_data32 -01:4a94 _print_sl_out32 -01:4a94 __check_assert_out3 -01:4a9f _print_sl_data33 -01:4aa2 _print_sl_out33 -01:4aae _print_sl_data34 -01:4ab0 _print_sl_out34 -01:4ab8 _print_sl_data35 -01:4abb _print_sl_out35 -01:4ac5 __check_assert_fail4 -01:4ad0 _print_sl_data36 -01:4ad3 _print_sl_out36 -01:4ad6 __check_assert_ok4 -01:4ade _print_sl_data37 -01:4ae3 _print_sl_out37 -01:4ae5 __check_assert_skip4 -01:4aed _print_sl_data38 -01:4af5 _print_sl_out38 -01:4af5 __check_assert_out4 -01:4b01 _print_sl_data39 -01:4b03 _print_sl_out39 -01:4b0b _print_sl_data40 -01:4b0e _print_sl_out40 -01:4b18 __check_assert_fail5 -01:4b23 _print_sl_data41 -01:4b26 _print_sl_out41 -01:4b29 __check_assert_ok5 -01:4b31 _print_sl_data42 -01:4b36 _print_sl_out42 -01:4b38 __check_assert_skip5 -01:4b40 _print_sl_data43 -01:4b48 _print_sl_out43 -01:4b48 __check_assert_out5 -01:4b53 _print_sl_data44 -01:4b56 _print_sl_out44 -01:4b62 _print_sl_data45 -01:4b64 _print_sl_out45 -01:4b6c _print_sl_data46 -01:4b6f _print_sl_out46 -01:4b79 __check_assert_fail6 -01:4b84 _print_sl_data47 -01:4b87 _print_sl_out47 -01:4b8a __check_assert_ok6 -01:4b92 _print_sl_data48 -01:4b97 _print_sl_out48 -01:4b99 __check_assert_skip6 -01:4ba1 _print_sl_data49 -01:4ba9 _print_sl_out49 -01:4ba9 __check_assert_out6 -01:4bb5 _print_sl_data50 -01:4bb7 _print_sl_out50 -01:4bbf _print_sl_data51 -01:4bc2 _print_sl_out51 -01:4bcc __check_assert_fail7 -01:4bd7 _print_sl_data52 -01:4bda _print_sl_out52 -01:4bdd __check_assert_ok7 -01:4be5 _print_sl_data53 -01:4bea _print_sl_out53 -01:4bec __check_assert_skip7 -01:4bf4 _print_sl_data54 -01:4bfc _print_sl_out54 -01:4bfc __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e _sizeof_run_test_suite +0000000e _sizeof_run_tests +0000000e _sizeof_run_test_cases +0000001d _sizeof_test_case +00000009 _sizeof_restore_mbc1 +00000011 _sizeof_switch_bank +0000001f _sizeof_fetch_expected_value diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.gb b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.gb index 8a9ce00e7d82b68930e1a62d98514942c6e14a37..4ff7eb0853a90e1a7208bc28f8cd2ec7172a1e1d 100644 GIT binary patch delta 597 zcmZ9IO=uHA6vt;a+Gv9|i!>}fw6h_o7ehrM3hA=hWRtOJQ?V)a=tX+)U{Mb>HD;33 z3SQKky?N0bJjB?G2a%PfAxjv@)!QIgXb)wBO08)0ZK^%^nE(6uyY-sd61sc)leVueR74gbsd0<3*n^49Lp%3r^Ihs>JpdqhWh-eOEd<@ibU`qj&wK zvq<0py78GWQ@%j?3;4Zfj;jA|_uN$PG5G=hN#7sjg&H|E;5&XebY%3{$>C^NU*eDG zT~GnE47vv@f|OxhGa&wVbfo;M3qvGDR!o*OS?JnNk+I)VZ|eQl{=oKoM_{cir1}H` zBYV!~P;c;p)buyU!;TtcGS;!{w>z}BIkqzve{i!Caa6=GB6a&C{nn20HQKe;=u)FK q5pJsMbHd!JnRP;rx;)5V1 zwa)C11)&cj2n9DC}q=MqHz8_t0sqU&*1g!?)`;AK_~JA-1g`f7(I(LodSO_Iy_g+s|x9^Iy*FEX&@p{i?M8G zzM{-8&SljFj2k=-dw5WN<%pWAt9b=4(p~m~Ssu*f>WdkThIATT;?c>h)!HO)bXJ|$ z%@p_}=ZpSrI4k_GZMeXkB5WI~6*5VzR%gX|$4sT!A0op!Zg%$?FZB#%%fj;4O? z&T_H4(%4C+u5NUe(7b&NXjLg_uU~2k!-u|0-yhPCf4ec2kfQQ~29BDEsQf2ot}BDm zuBf~}U_p5H`Z@eZ28#`|RsjMz)jdR62)KVke#Yt5a-?rM|8&mHuP7 z`oG#P5))3BXj?`W)MB|-R~KruiS&1XKHZ3UB{>ThSxz)ltEmh1a&fSO~z<}S{An$I&7Xr>tqBx%t#o==PZ01e(`P$&_2myUFq zISipg%y(GjGdzdS844V}W-xHDPoU;y#t9mMANW*SbQmSaeaTy#_ayH!#3b>n8G|i` z15K>jipLBQ($F2k&$l(wBguh8NPb`y?HOmUX3xk`d?S9J4wLHWu$3A=(;InFxG{8N zCSggC)#w(66(xgZ(AVe*SoEoaM@bTzNbsJfd%4*l*YI<5{kdyCpAS+m_>|h8+V=TU ekot>HX^*B_4=?Q-czpk|ams*GhH%aZ8UFx7+$u`| diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.sym b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.sym index e96b0029f..a42de7f05 100644 --- a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.sym +++ b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_2Mb/test.sym @@ -1,226 +1,69 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_2Mb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_2Mb.gb". [labels] -01:4c00 print_load_font -01:4c0d print_string -01:4c17 print_a -01:4c21 print_newline -01:4c2c print_digit -01:4c39 print_regs -01:4c42 _print_sl_data0 -01:4c48 _print_sl_out0 -01:4c55 _print_sl_data1 -01:4c5b _print_sl_out1 -01:4c6d _print_sl_data2 -01:4c73 _print_sl_out2 -01:4c80 _print_sl_data3 -01:4c86 _print_sl_out3 -01:4c98 _print_sl_data4 -01:4c9e _print_sl_out4 -01:4cab _print_sl_data5 -01:4cb1 _print_sl_out5 -01:4cc3 _print_sl_data6 -01:4cc9 _print_sl_out6 -01:4cd6 _print_sl_data7 -01:4cdc _print_sl_out7 +01:48bc clear_vram +01:487b disable_lcd_safe +01:4881 disable_lcd_safe@wait_ly_0 +01:48d0 memcpy +01:48d9 memset +01:4899 print_hex4 +01:48c6 print_hex8 +01:48e9 print_inline_string +01:48a5 print_load_font +01:48b1 print_newline +01:48e2 print_string +01:47f1 quit +01:4806 quit@cb_return +01:480b quit@wait_ly_1 +01:4811 quit@wait_ly_2 +01:4817 quit@wait_ly_3 +01:481d quit@wait_ly_4 +01:4827 quit@success +01:484e quit@failure +01:4863 quit@halt +01:4864 quit@halt_execution_0 +01:4867 reset_screen +01:488a serial_send_byte 01:4001 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f1 memcpy -01:47fa memset -01:4803 memcmp -01:4811 clear_vram -01:481b clear_oam -01:4825 disable_lcd_safe -01:482b _wait_ly_0 -01:4831 _wait_ly_1 -01:483a reset_screen -01:484e process_results -01:4862 _wait_ly_2 -01:4868 _wait_ly_3 -01:487e _print_results_halt_0 -01:4881 _process_results_cb -01:488c _print_sl_data8 -01:4896 _print_sl_out8 -01:48b0 _print_sl_data9 -01:48bb _print_sl_out9 -01:48d3 _print_sl_data10 -01:48df _print_sl_out10 -01:48e0 dump_mem -01:48ff _dump_mem_line -01:4929 _check_asserts -01:4937 _print_sl_data11 -01:493a _print_sl_out11 -01:4946 _print_sl_data12 -01:4948 _print_sl_out12 -01:4950 _print_sl_data13 -01:4953 _print_sl_out13 -01:495d __check_assert_fail0 -01:4968 _print_sl_data14 -01:496b _print_sl_out14 -01:496e __check_assert_ok0 -01:4976 _print_sl_data15 -01:497b _print_sl_out15 -01:497d __check_assert_skip0 -01:4985 _print_sl_data16 -01:498d _print_sl_out16 -01:498d __check_assert_out0 -01:4999 _print_sl_data17 -01:499b _print_sl_out17 -01:49a3 _print_sl_data18 -01:49a6 _print_sl_out18 -01:49b0 __check_assert_fail1 -01:49bb _print_sl_data19 -01:49be _print_sl_out19 -01:49c1 __check_assert_ok1 -01:49c9 _print_sl_data20 -01:49ce _print_sl_out20 -01:49d0 __check_assert_skip1 -01:49d8 _print_sl_data21 -01:49e0 _print_sl_out21 -01:49e0 __check_assert_out1 -01:49eb _print_sl_data22 -01:49ee _print_sl_out22 -01:49fa _print_sl_data23 -01:49fc _print_sl_out23 -01:4a04 _print_sl_data24 -01:4a07 _print_sl_out24 -01:4a11 __check_assert_fail2 -01:4a1c _print_sl_data25 -01:4a1f _print_sl_out25 -01:4a22 __check_assert_ok2 -01:4a2a _print_sl_data26 -01:4a2f _print_sl_out26 -01:4a31 __check_assert_skip2 -01:4a39 _print_sl_data27 -01:4a41 _print_sl_out27 -01:4a41 __check_assert_out2 -01:4a4d _print_sl_data28 -01:4a4f _print_sl_out28 -01:4a57 _print_sl_data29 -01:4a5a _print_sl_out29 -01:4a64 __check_assert_fail3 -01:4a6f _print_sl_data30 -01:4a72 _print_sl_out30 -01:4a75 __check_assert_ok3 -01:4a7d _print_sl_data31 -01:4a82 _print_sl_out31 -01:4a84 __check_assert_skip3 -01:4a8c _print_sl_data32 -01:4a94 _print_sl_out32 -01:4a94 __check_assert_out3 -01:4a9f _print_sl_data33 -01:4aa2 _print_sl_out33 -01:4aae _print_sl_data34 -01:4ab0 _print_sl_out34 -01:4ab8 _print_sl_data35 -01:4abb _print_sl_out35 -01:4ac5 __check_assert_fail4 -01:4ad0 _print_sl_data36 -01:4ad3 _print_sl_out36 -01:4ad6 __check_assert_ok4 -01:4ade _print_sl_data37 -01:4ae3 _print_sl_out37 -01:4ae5 __check_assert_skip4 -01:4aed _print_sl_data38 -01:4af5 _print_sl_out38 -01:4af5 __check_assert_out4 -01:4b01 _print_sl_data39 -01:4b03 _print_sl_out39 -01:4b0b _print_sl_data40 -01:4b0e _print_sl_out40 -01:4b18 __check_assert_fail5 -01:4b23 _print_sl_data41 -01:4b26 _print_sl_out41 -01:4b29 __check_assert_ok5 -01:4b31 _print_sl_data42 -01:4b36 _print_sl_out42 -01:4b38 __check_assert_skip5 -01:4b40 _print_sl_data43 -01:4b48 _print_sl_out43 -01:4b48 __check_assert_out5 -01:4b53 _print_sl_data44 -01:4b56 _print_sl_out44 -01:4b62 _print_sl_data45 -01:4b64 _print_sl_out45 -01:4b6c _print_sl_data46 -01:4b6f _print_sl_out46 -01:4b79 __check_assert_fail6 -01:4b84 _print_sl_data47 -01:4b87 _print_sl_out47 -01:4b8a __check_assert_ok6 -01:4b92 _print_sl_data48 -01:4b97 _print_sl_out48 -01:4b99 __check_assert_skip6 -01:4ba1 _print_sl_data49 -01:4ba9 _print_sl_out49 -01:4ba9 __check_assert_out6 -01:4bb5 _print_sl_data50 -01:4bb7 _print_sl_out50 -01:4bbf _print_sl_data51 -01:4bc2 _print_sl_out51 -01:4bcc __check_assert_fail7 -01:4bd7 _print_sl_data52 -01:4bda _print_sl_out52 -01:4bdd __check_assert_ok7 -01:4be5 _print_sl_data53 -01:4bea _print_sl_out53 -01:4bec __check_assert_skip7 -01:4bf4 _print_sl_data54 -01:4bfc _print_sl_out54 -01:4bfc __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e _sizeof_run_test_suite +0000000e _sizeof_run_tests +0000000e _sizeof_run_test_cases +0000001d _sizeof_test_case +00000009 _sizeof_restore_mbc1 +00000011 _sizeof_switch_bank +0000001f _sizeof_fetch_expected_value diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/test.gb b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_4Mb/test.gb index f51f7dbb0d7135e60518d524b7e231ea517b87ee..98d0276960ef0a9e1d29101d6cd5235b8937bd9f 100644 GIT binary patch delta 609 zcmZ9IO=uHA6vt;aZKDm^F4C~{(9VXSUJMn5cu1Gc$0lRbrlKkJ=tX+)U{Mb>ZOkO8 zd+?&(?9Gej;339dJcw*r8nT3eT)ho~g?f+;Rcb|}Z&U5T$Nb;N?+x=F!x&+Vyw2g$ z+LnqeIUwQZh!m+;5M9<{?|5K;7(z_4b=*nB<4nE#eU03rTHHsYM(H=`{@fks%)EB{LV+k7Z3jErgENGWuzMeFKG;6%DwdJ$wxgwit}m7TW4Zdj z+8!kaoG!7p3@@m~a;>f|)L0YQ?;v|RVdHXg7B2FfNTya(7wYBeyqEMuxp_Ici*@%$ zo-%NN%&n+#YHO$Q!B&hnLl=jVtT{2G;p{YyHL-&y@t(pv=0uId$uTzN*XiDbatB4_ z+k6#xJ~tXz$uXEMvs!)FeJhuI5eghi83IQ|;E+NbFsjb5@m(^CqVT5R;|iIOr*(Lr z!$7ry3i3F7#9^47D7=VOLCw!OClv^s6?2&;LCqmo^LxPyO)xp~ByVx(NwS@}Bl7Xo z603#|4#!fKfd2?z4s-CK!-(tfsNnk!Pjcir9OTe*uwFsQInGHr0u3>hNlGXgaV6hH zUdOHLYo6k1p5|!|Jxx~i7ea__%NywM6^Bxuz!ec-4gqx7;X2$DeBa!$IsIcWrDuD*I`x6=sSGMk>~Iwhn|CV5;ec&oTL%>K}=;u2T^j&mHb)oeaT-q;*$8)9EWX= zJx#3IjE~bOq@f$a&$l_;BT0Y4C*L!R){MPhvu5N7z7fAq2T65g$V`o$=?y. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_4Mb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_4Mb.gb". [labels] -01:4c00 print_load_font -01:4c0d print_string -01:4c17 print_a -01:4c21 print_newline -01:4c2c print_digit -01:4c39 print_regs -01:4c42 _print_sl_data0 -01:4c48 _print_sl_out0 -01:4c55 _print_sl_data1 -01:4c5b _print_sl_out1 -01:4c6d _print_sl_data2 -01:4c73 _print_sl_out2 -01:4c80 _print_sl_data3 -01:4c86 _print_sl_out3 -01:4c98 _print_sl_data4 -01:4c9e _print_sl_out4 -01:4cab _print_sl_data5 -01:4cb1 _print_sl_out5 -01:4cc3 _print_sl_data6 -01:4cc9 _print_sl_out6 -01:4cd6 _print_sl_data7 -01:4cdc _print_sl_out7 +01:48bc clear_vram +01:487b disable_lcd_safe +01:4881 disable_lcd_safe@wait_ly_0 +01:48d0 memcpy +01:48d9 memset +01:4899 print_hex4 +01:48c6 print_hex8 +01:48e9 print_inline_string +01:48a5 print_load_font +01:48b1 print_newline +01:48e2 print_string +01:47f1 quit +01:4806 quit@cb_return +01:480b quit@wait_ly_1 +01:4811 quit@wait_ly_2 +01:4817 quit@wait_ly_3 +01:481d quit@wait_ly_4 +01:4827 quit@success +01:484e quit@failure +01:4863 quit@halt +01:4864 quit@halt_execution_0 +01:4867 reset_screen +01:488a serial_send_byte 01:4001 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f1 memcpy -01:47fa memset -01:4803 memcmp -01:4811 clear_vram -01:481b clear_oam -01:4825 disable_lcd_safe -01:482b _wait_ly_0 -01:4831 _wait_ly_1 -01:483a reset_screen -01:484e process_results -01:4862 _wait_ly_2 -01:4868 _wait_ly_3 -01:487e _print_results_halt_0 -01:4881 _process_results_cb -01:488c _print_sl_data8 -01:4896 _print_sl_out8 -01:48b0 _print_sl_data9 -01:48bb _print_sl_out9 -01:48d3 _print_sl_data10 -01:48df _print_sl_out10 -01:48e0 dump_mem -01:48ff _dump_mem_line -01:4929 _check_asserts -01:4937 _print_sl_data11 -01:493a _print_sl_out11 -01:4946 _print_sl_data12 -01:4948 _print_sl_out12 -01:4950 _print_sl_data13 -01:4953 _print_sl_out13 -01:495d __check_assert_fail0 -01:4968 _print_sl_data14 -01:496b _print_sl_out14 -01:496e __check_assert_ok0 -01:4976 _print_sl_data15 -01:497b _print_sl_out15 -01:497d __check_assert_skip0 -01:4985 _print_sl_data16 -01:498d _print_sl_out16 -01:498d __check_assert_out0 -01:4999 _print_sl_data17 -01:499b _print_sl_out17 -01:49a3 _print_sl_data18 -01:49a6 _print_sl_out18 -01:49b0 __check_assert_fail1 -01:49bb _print_sl_data19 -01:49be _print_sl_out19 -01:49c1 __check_assert_ok1 -01:49c9 _print_sl_data20 -01:49ce _print_sl_out20 -01:49d0 __check_assert_skip1 -01:49d8 _print_sl_data21 -01:49e0 _print_sl_out21 -01:49e0 __check_assert_out1 -01:49eb _print_sl_data22 -01:49ee _print_sl_out22 -01:49fa _print_sl_data23 -01:49fc _print_sl_out23 -01:4a04 _print_sl_data24 -01:4a07 _print_sl_out24 -01:4a11 __check_assert_fail2 -01:4a1c _print_sl_data25 -01:4a1f _print_sl_out25 -01:4a22 __check_assert_ok2 -01:4a2a _print_sl_data26 -01:4a2f _print_sl_out26 -01:4a31 __check_assert_skip2 -01:4a39 _print_sl_data27 -01:4a41 _print_sl_out27 -01:4a41 __check_assert_out2 -01:4a4d _print_sl_data28 -01:4a4f _print_sl_out28 -01:4a57 _print_sl_data29 -01:4a5a _print_sl_out29 -01:4a64 __check_assert_fail3 -01:4a6f _print_sl_data30 -01:4a72 _print_sl_out30 -01:4a75 __check_assert_ok3 -01:4a7d _print_sl_data31 -01:4a82 _print_sl_out31 -01:4a84 __check_assert_skip3 -01:4a8c _print_sl_data32 -01:4a94 _print_sl_out32 -01:4a94 __check_assert_out3 -01:4a9f _print_sl_data33 -01:4aa2 _print_sl_out33 -01:4aae _print_sl_data34 -01:4ab0 _print_sl_out34 -01:4ab8 _print_sl_data35 -01:4abb _print_sl_out35 -01:4ac5 __check_assert_fail4 -01:4ad0 _print_sl_data36 -01:4ad3 _print_sl_out36 -01:4ad6 __check_assert_ok4 -01:4ade _print_sl_data37 -01:4ae3 _print_sl_out37 -01:4ae5 __check_assert_skip4 -01:4aed _print_sl_data38 -01:4af5 _print_sl_out38 -01:4af5 __check_assert_out4 -01:4b01 _print_sl_data39 -01:4b03 _print_sl_out39 -01:4b0b _print_sl_data40 -01:4b0e _print_sl_out40 -01:4b18 __check_assert_fail5 -01:4b23 _print_sl_data41 -01:4b26 _print_sl_out41 -01:4b29 __check_assert_ok5 -01:4b31 _print_sl_data42 -01:4b36 _print_sl_out42 -01:4b38 __check_assert_skip5 -01:4b40 _print_sl_data43 -01:4b48 _print_sl_out43 -01:4b48 __check_assert_out5 -01:4b53 _print_sl_data44 -01:4b56 _print_sl_out44 -01:4b62 _print_sl_data45 -01:4b64 _print_sl_out45 -01:4b6c _print_sl_data46 -01:4b6f _print_sl_out46 -01:4b79 __check_assert_fail6 -01:4b84 _print_sl_data47 -01:4b87 _print_sl_out47 -01:4b8a __check_assert_ok6 -01:4b92 _print_sl_data48 -01:4b97 _print_sl_out48 -01:4b99 __check_assert_skip6 -01:4ba1 _print_sl_data49 -01:4ba9 _print_sl_out49 -01:4ba9 __check_assert_out6 -01:4bb5 _print_sl_data50 -01:4bb7 _print_sl_out50 -01:4bbf _print_sl_data51 -01:4bc2 _print_sl_out51 -01:4bcc __check_assert_fail7 -01:4bd7 _print_sl_data52 -01:4bda _print_sl_out52 -01:4bdd __check_assert_ok7 -01:4be5 _print_sl_data53 -01:4bea _print_sl_out53 -01:4bec __check_assert_skip7 -01:4bf4 _print_sl_data54 -01:4bfc _print_sl_out54 -01:4bfc __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e _sizeof_run_test_suite +0000000e _sizeof_run_tests +0000000e _sizeof_run_test_cases +0000001d _sizeof_test_case +00000009 _sizeof_restore_mbc1 +00000011 _sizeof_switch_bank +0000001f _sizeof_fetch_expected_value diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/test.gb b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_512Kb/test.gb index 6ad98dafc8c739a461b75c4fd4bcd44c3c28d851..748726c8babf2793a442aba6b85210e4ae9dc612 100644 GIT binary patch delta 588 zcmZ9IO=uHA6vt<_vC#%?7im~}XlIw8UJMn5cu1Gc$0lRbrlKkJ=tX+)U{Mb>HD=P( ziRA--Z1YmjD;8ry(r@9 z`fC;0azw&U5bshIb>-(0W*Bk@*I{ugOMOgckA3B&WS^0*E^M&`1+Up+HSg6I#?jcTwy42#&UNh1(Xq3%xhox+dNfjbY4pO? zGf3b;y7iH-P`*g{Gx)v7u4?@5^u26mCew}S7^Rurwz5is6!V@hG9yfpnWRyq7NyyTL@GJ-Foi5GeZ}BaM+o> z-*?XazH{%nGrAtu_3*g`(B`fth#|fvz;$BZFD1wgF%<$GaNHq=y{Bx?m2ILX)k8|Yp%i4iNcV&n%<*70-&o43G^Ek!GLKH?%=RXE(^<9O zFw)?U>@WMb;k59-w&5&uin48}RmmhV+s=ypu942LKSa8H)adTjU+(GhmWk!B8~A7& z&WTcYrMZ(#UD|M#(Y$j6XjN(Gte5V_rPv7 z`&ZjVV!+8VZOibYQmWJ&%3_^1k^c76ryDgcre@(B%ZX*{b!D+psVxLaPghzOQ#)vP zZ?crW17vQB#_`SV#>bm+)(njwO0wq0ji$TZINZVx9>aSI@3<=(2U25n%J0*?3Hc6+ zO1If6@O-wLSjl0St_;TeVkhy4r&4%X`^InOvDPoT-CQb_?NW4`1E z$ZNQDp5}3u7HFPiFwmq`f6ayHw!DoF-!mu_2wdU;>M(!~+kA%`oc9cFGZYy7L7^rE z4%QLWgeqOWpb&_$QHW}WQFGMS+{JlM^Ld5>%?yKqBrUqm^J&o^qQP4X3S|QC(UB%G zhe320_Z?RG4A0>Uh60Cg7z`Y&W2kw7ae_+VXFin{9YM)4U-DPZdy>B~#3b>nISyM4 z2bx&5nHbka$Ut`xKi}qXkEFuMko3STSu^%t)tZrF_(t5Fj*!~OkeMDk)f;|ExHfog zCTYeYr_wEq$Z{6Tps&#ru;f!kkBZ09Bo6PZnwOgka&. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_512Kb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_512Kb.gb". [labels] -01:4c00 print_load_font -01:4c0d print_string -01:4c17 print_a -01:4c21 print_newline -01:4c2c print_digit -01:4c39 print_regs -01:4c42 _print_sl_data0 -01:4c48 _print_sl_out0 -01:4c55 _print_sl_data1 -01:4c5b _print_sl_out1 -01:4c6d _print_sl_data2 -01:4c73 _print_sl_out2 -01:4c80 _print_sl_data3 -01:4c86 _print_sl_out3 -01:4c98 _print_sl_data4 -01:4c9e _print_sl_out4 -01:4cab _print_sl_data5 -01:4cb1 _print_sl_out5 -01:4cc3 _print_sl_data6 -01:4cc9 _print_sl_out6 -01:4cd6 _print_sl_data7 -01:4cdc _print_sl_out7 +01:48bc clear_vram +01:487b disable_lcd_safe +01:4881 disable_lcd_safe@wait_ly_0 +01:48d0 memcpy +01:48d9 memset +01:4899 print_hex4 +01:48c6 print_hex8 +01:48e9 print_inline_string +01:48a5 print_load_font +01:48b1 print_newline +01:48e2 print_string +01:47f1 quit +01:4806 quit@cb_return +01:480b quit@wait_ly_1 +01:4811 quit@wait_ly_2 +01:4817 quit@wait_ly_3 +01:481d quit@wait_ly_4 +01:4827 quit@success +01:484e quit@failure +01:4863 quit@halt +01:4864 quit@halt_execution_0 +01:4867 reset_screen +01:488a serial_send_byte 01:4001 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f1 memcpy -01:47fa memset -01:4803 memcmp -01:4811 clear_vram -01:481b clear_oam -01:4825 disable_lcd_safe -01:482b _wait_ly_0 -01:4831 _wait_ly_1 -01:483a reset_screen -01:484e process_results -01:4862 _wait_ly_2 -01:4868 _wait_ly_3 -01:487e _print_results_halt_0 -01:4881 _process_results_cb -01:488c _print_sl_data8 -01:4896 _print_sl_out8 -01:48b0 _print_sl_data9 -01:48bb _print_sl_out9 -01:48d3 _print_sl_data10 -01:48df _print_sl_out10 -01:48e0 dump_mem -01:48ff _dump_mem_line -01:4929 _check_asserts -01:4937 _print_sl_data11 -01:493a _print_sl_out11 -01:4946 _print_sl_data12 -01:4948 _print_sl_out12 -01:4950 _print_sl_data13 -01:4953 _print_sl_out13 -01:495d __check_assert_fail0 -01:4968 _print_sl_data14 -01:496b _print_sl_out14 -01:496e __check_assert_ok0 -01:4976 _print_sl_data15 -01:497b _print_sl_out15 -01:497d __check_assert_skip0 -01:4985 _print_sl_data16 -01:498d _print_sl_out16 -01:498d __check_assert_out0 -01:4999 _print_sl_data17 -01:499b _print_sl_out17 -01:49a3 _print_sl_data18 -01:49a6 _print_sl_out18 -01:49b0 __check_assert_fail1 -01:49bb _print_sl_data19 -01:49be _print_sl_out19 -01:49c1 __check_assert_ok1 -01:49c9 _print_sl_data20 -01:49ce _print_sl_out20 -01:49d0 __check_assert_skip1 -01:49d8 _print_sl_data21 -01:49e0 _print_sl_out21 -01:49e0 __check_assert_out1 -01:49eb _print_sl_data22 -01:49ee _print_sl_out22 -01:49fa _print_sl_data23 -01:49fc _print_sl_out23 -01:4a04 _print_sl_data24 -01:4a07 _print_sl_out24 -01:4a11 __check_assert_fail2 -01:4a1c _print_sl_data25 -01:4a1f _print_sl_out25 -01:4a22 __check_assert_ok2 -01:4a2a _print_sl_data26 -01:4a2f _print_sl_out26 -01:4a31 __check_assert_skip2 -01:4a39 _print_sl_data27 -01:4a41 _print_sl_out27 -01:4a41 __check_assert_out2 -01:4a4d _print_sl_data28 -01:4a4f _print_sl_out28 -01:4a57 _print_sl_data29 -01:4a5a _print_sl_out29 -01:4a64 __check_assert_fail3 -01:4a6f _print_sl_data30 -01:4a72 _print_sl_out30 -01:4a75 __check_assert_ok3 -01:4a7d _print_sl_data31 -01:4a82 _print_sl_out31 -01:4a84 __check_assert_skip3 -01:4a8c _print_sl_data32 -01:4a94 _print_sl_out32 -01:4a94 __check_assert_out3 -01:4a9f _print_sl_data33 -01:4aa2 _print_sl_out33 -01:4aae _print_sl_data34 -01:4ab0 _print_sl_out34 -01:4ab8 _print_sl_data35 -01:4abb _print_sl_out35 -01:4ac5 __check_assert_fail4 -01:4ad0 _print_sl_data36 -01:4ad3 _print_sl_out36 -01:4ad6 __check_assert_ok4 -01:4ade _print_sl_data37 -01:4ae3 _print_sl_out37 -01:4ae5 __check_assert_skip4 -01:4aed _print_sl_data38 -01:4af5 _print_sl_out38 -01:4af5 __check_assert_out4 -01:4b01 _print_sl_data39 -01:4b03 _print_sl_out39 -01:4b0b _print_sl_data40 -01:4b0e _print_sl_out40 -01:4b18 __check_assert_fail5 -01:4b23 _print_sl_data41 -01:4b26 _print_sl_out41 -01:4b29 __check_assert_ok5 -01:4b31 _print_sl_data42 -01:4b36 _print_sl_out42 -01:4b38 __check_assert_skip5 -01:4b40 _print_sl_data43 -01:4b48 _print_sl_out43 -01:4b48 __check_assert_out5 -01:4b53 _print_sl_data44 -01:4b56 _print_sl_out44 -01:4b62 _print_sl_data45 -01:4b64 _print_sl_out45 -01:4b6c _print_sl_data46 -01:4b6f _print_sl_out46 -01:4b79 __check_assert_fail6 -01:4b84 _print_sl_data47 -01:4b87 _print_sl_out47 -01:4b8a __check_assert_ok6 -01:4b92 _print_sl_data48 -01:4b97 _print_sl_out48 -01:4b99 __check_assert_skip6 -01:4ba1 _print_sl_data49 -01:4ba9 _print_sl_out49 -01:4ba9 __check_assert_out6 -01:4bb5 _print_sl_data50 -01:4bb7 _print_sl_out50 -01:4bbf _print_sl_data51 -01:4bc2 _print_sl_out51 -01:4bcc __check_assert_fail7 -01:4bd7 _print_sl_data52 -01:4bda _print_sl_out52 -01:4bdd __check_assert_ok7 -01:4be5 _print_sl_data53 -01:4bea _print_sl_out53 -01:4bec __check_assert_skip7 -01:4bf4 _print_sl_data54 -01:4bfc _print_sl_out54 -01:4bfc __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e _sizeof_run_test_suite +0000000e _sizeof_run_tests +0000000e _sizeof_run_test_cases +0000001d _sizeof_test_case +00000009 _sizeof_restore_mbc1 +00000011 _sizeof_switch_bank +0000001f _sizeof_fetch_expected_value diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.gb b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.gb index a7a41958e3b5231fee5004ec061346591f6d8230..3cdacce6a91ed004ce01efcadb37bd568e93a8af 100644 GIT binary patch delta 637 zcmZ9IO-vI(6vt<_&_XMe#?UkzVB0k6#Rh{39?E9>vF%7dFj|5~FNT8$33|X{?Q4s3 z@S@)2=0$t(P=SjFW7ceFx@jhboG)eI5xvMXW=DsN;JfVZb6ckp3mOij8iX?URCbr68wb7qeOtu`OcN>atJZ@U*bA z;h9t_g#un1obQ8K8;E;?5w5yl2L_tf+ z!jM%x=CMR!F_yKd%_~RTA2%DH&^5lnBD#YAWo%ijeMYj^?$0V*zja$)$RIy58@$G% zx}x@jsDRB!bPJ+AkiVK@ixp9@iq5NPtF|kInXqT#_nw$R^>@2xC3_F$AHqNC`{TS=mrpw#ql5mT$&pjzk&wE^ z9*{diMWJ<}yFw+Qz__Z!Mf~rmDDbPn<2=DLe7>ysxT^f*Y2!7qr`~HF4Q#(LIaVrM zYRn;F@}ars?YS>VO;>X|WCq8;hgEF3j1DR7O?{q<-oM!in?VE^$qnN@`PQCgo1|-O zlC`bYMCha^aIhq@V#pKt?sn8$p}^r=_JQo0JKd~zW;-VhRDlAfAW?8o7@#mn!AZeI WVTi&o1vdo`g%cD;D2zS_FZ=-y+Z(+A delta 1780 zcma)6U5Fc16uxJ&$!7DjyJ^<#xN3K@Z6!*Tl?rQ%jrp7WG_#ws$r4eaqAy|<9|S3> zb?*K+AoM{5VSQOEh4!Ifszq86>d-*hAxtRKb` zyx;0|vb~R#E3?m*MegM1+fXi%Nn$nHtM;2_BFX;{QTwFXIY6K9QDw)%@;6L;G|cu& zzO!1}L#D27wwKYoc>-8f321Iyu1h0FzE0j9)=z%5IW-dv%J*tGs?P-FKN)jP@kaLs z<()YzMko-a(d=SJdvKQU5q9r`%?I1px`t(>+nIK$eKZkiCli0Q^UX+MpzF(p|5&d6 zueL{s31uHU>8pMy(0Czz^K)WvGCyx=B1QLJBy?`GZo zfu{@{AZt5fp5ESNzP}yi&Ctc6Bh-*8US2z)Q5vZ8$`Ip#?IB>2AM&m3_{{A!NF z4#%!0R&B+`X#|qc8OG1I73h)p(2PgEXXRV7_5rOmD+lq7_-)!p%ApY}F?O~Wcuu-8 zd}DUTib7grTj*1i6qdnWqeo!Lp>lmH8by;Ryshc|+_alZo!rb|?z+Qg-PDT?r4FVx z9lqeE{^(HJgQ?d2%YPIeKDa^+3I>%7>M`h$LA?g`8Fbj7euIt}G+@x6K|=-&8+7zM H9i#sMbm2Jc diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.sym b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.sym index 9217d7990..6f9af044c 100644 --- a/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.sym +++ b/cinema/gb/mooneye-gb/emulator-only/mbc1/rom_8Mb/test.sym @@ -1,226 +1,69 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_8Mb.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/rom_8Mb.gb". [labels] -01:4c00 print_load_font -01:4c0d print_string -01:4c17 print_a -01:4c21 print_newline -01:4c2c print_digit -01:4c39 print_regs -01:4c42 _print_sl_data0 -01:4c48 _print_sl_out0 -01:4c55 _print_sl_data1 -01:4c5b _print_sl_out1 -01:4c6d _print_sl_data2 -01:4c73 _print_sl_out2 -01:4c80 _print_sl_data3 -01:4c86 _print_sl_out3 -01:4c98 _print_sl_data4 -01:4c9e _print_sl_out4 -01:4cab _print_sl_data5 -01:4cb1 _print_sl_out5 -01:4cc3 _print_sl_data6 -01:4cc9 _print_sl_out6 -01:4cd6 _print_sl_data7 -01:4cdc _print_sl_out7 +01:48bc clear_vram +01:487b disable_lcd_safe +01:4881 disable_lcd_safe@wait_ly_0 +01:48d0 memcpy +01:48d9 memset +01:4899 print_hex4 +01:48c6 print_hex8 +01:48e9 print_inline_string +01:48a5 print_load_font +01:48b1 print_newline +01:48e2 print_string +01:47f1 quit +01:4806 quit@cb_return +01:480b quit@wait_ly_1 +01:4811 quit@wait_ly_2 +01:4817 quit@wait_ly_3 +01:481d quit@wait_ly_4 +01:4827 quit@success +01:484e quit@failure +01:4863 quit@halt +01:4864 quit@halt_execution_0 +01:4867 reset_screen +01:488a serial_send_byte 01:4001 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f1 memcpy -01:47fa memset -01:4803 memcmp -01:4811 clear_vram -01:481b clear_oam -01:4825 disable_lcd_safe -01:482b _wait_ly_0 -01:4831 _wait_ly_1 -01:483a reset_screen -01:484e process_results -01:4862 _wait_ly_2 -01:4868 _wait_ly_3 -01:487e _print_results_halt_0 -01:4881 _process_results_cb -01:488c _print_sl_data8 -01:4896 _print_sl_out8 -01:48b0 _print_sl_data9 -01:48bb _print_sl_out9 -01:48d3 _print_sl_data10 -01:48df _print_sl_out10 -01:48e0 dump_mem -01:48ff _dump_mem_line -01:4929 _check_asserts -01:4937 _print_sl_data11 -01:493a _print_sl_out11 -01:4946 _print_sl_data12 -01:4948 _print_sl_out12 -01:4950 _print_sl_data13 -01:4953 _print_sl_out13 -01:495d __check_assert_fail0 -01:4968 _print_sl_data14 -01:496b _print_sl_out14 -01:496e __check_assert_ok0 -01:4976 _print_sl_data15 -01:497b _print_sl_out15 -01:497d __check_assert_skip0 -01:4985 _print_sl_data16 -01:498d _print_sl_out16 -01:498d __check_assert_out0 -01:4999 _print_sl_data17 -01:499b _print_sl_out17 -01:49a3 _print_sl_data18 -01:49a6 _print_sl_out18 -01:49b0 __check_assert_fail1 -01:49bb _print_sl_data19 -01:49be _print_sl_out19 -01:49c1 __check_assert_ok1 -01:49c9 _print_sl_data20 -01:49ce _print_sl_out20 -01:49d0 __check_assert_skip1 -01:49d8 _print_sl_data21 -01:49e0 _print_sl_out21 -01:49e0 __check_assert_out1 -01:49eb _print_sl_data22 -01:49ee _print_sl_out22 -01:49fa _print_sl_data23 -01:49fc _print_sl_out23 -01:4a04 _print_sl_data24 -01:4a07 _print_sl_out24 -01:4a11 __check_assert_fail2 -01:4a1c _print_sl_data25 -01:4a1f _print_sl_out25 -01:4a22 __check_assert_ok2 -01:4a2a _print_sl_data26 -01:4a2f _print_sl_out26 -01:4a31 __check_assert_skip2 -01:4a39 _print_sl_data27 -01:4a41 _print_sl_out27 -01:4a41 __check_assert_out2 -01:4a4d _print_sl_data28 -01:4a4f _print_sl_out28 -01:4a57 _print_sl_data29 -01:4a5a _print_sl_out29 -01:4a64 __check_assert_fail3 -01:4a6f _print_sl_data30 -01:4a72 _print_sl_out30 -01:4a75 __check_assert_ok3 -01:4a7d _print_sl_data31 -01:4a82 _print_sl_out31 -01:4a84 __check_assert_skip3 -01:4a8c _print_sl_data32 -01:4a94 _print_sl_out32 -01:4a94 __check_assert_out3 -01:4a9f _print_sl_data33 -01:4aa2 _print_sl_out33 -01:4aae _print_sl_data34 -01:4ab0 _print_sl_out34 -01:4ab8 _print_sl_data35 -01:4abb _print_sl_out35 -01:4ac5 __check_assert_fail4 -01:4ad0 _print_sl_data36 -01:4ad3 _print_sl_out36 -01:4ad6 __check_assert_ok4 -01:4ade _print_sl_data37 -01:4ae3 _print_sl_out37 -01:4ae5 __check_assert_skip4 -01:4aed _print_sl_data38 -01:4af5 _print_sl_out38 -01:4af5 __check_assert_out4 -01:4b01 _print_sl_data39 -01:4b03 _print_sl_out39 -01:4b0b _print_sl_data40 -01:4b0e _print_sl_out40 -01:4b18 __check_assert_fail5 -01:4b23 _print_sl_data41 -01:4b26 _print_sl_out41 -01:4b29 __check_assert_ok5 -01:4b31 _print_sl_data42 -01:4b36 _print_sl_out42 -01:4b38 __check_assert_skip5 -01:4b40 _print_sl_data43 -01:4b48 _print_sl_out43 -01:4b48 __check_assert_out5 -01:4b53 _print_sl_data44 -01:4b56 _print_sl_out44 -01:4b62 _print_sl_data45 -01:4b64 _print_sl_out45 -01:4b6c _print_sl_data46 -01:4b6f _print_sl_out46 -01:4b79 __check_assert_fail6 -01:4b84 _print_sl_data47 -01:4b87 _print_sl_out47 -01:4b8a __check_assert_ok6 -01:4b92 _print_sl_data48 -01:4b97 _print_sl_out48 -01:4b99 __check_assert_skip6 -01:4ba1 _print_sl_data49 -01:4ba9 _print_sl_out49 -01:4ba9 __check_assert_out6 -01:4bb5 _print_sl_data50 -01:4bb7 _print_sl_out50 -01:4bbf _print_sl_data51 -01:4bc2 _print_sl_out51 -01:4bcc __check_assert_fail7 -01:4bd7 _print_sl_data52 -01:4bda _print_sl_out52 -01:4bdd __check_assert_ok7 -01:4be5 _print_sl_data53 -01:4bea _print_sl_out53 -01:4bec __check_assert_skip7 -01:4bf4 _print_sl_data54 -01:4bfc _print_sl_out54 -01:4bfc __check_assert_out7 +00:0150 main 00:016b fail -00:017f _wait_ly_4 -00:0185 _wait_ly_5 -00:019b _print_results_halt_1 -00:019e _fail_cb -00:01a6 _print_sl_data55 -00:01b2 _print_sl_out55 -00:01c2 _print_sl_data56 -00:01ce _print_sl_out56 -00:01d8 _print_sl_data57 -00:01e4 _print_sl_out57 -00:01ef _print_sl_data58 -00:01f5 _print_sl_out58 -00:0208 _print_sl_data59 -00:0215 _print_sl_out59 -00:0225 _print_sl_data60 -00:0232 _print_sl_out60 -00:0242 _print_sl_data61 -00:024f _print_sl_out61 -00:025a c000_functions_start -00:025a run_test_suite -00:0284 _wait_ly_6 -00:028a _wait_ly_7 -00:02a0 _print_results_halt_2 -00:02a3 _test_ok_cb_0 -00:02ab _print_sl_data62 -00:02b3 _print_sl_out62 -00:02b6 run_tests -00:02c4 run_test_cases -00:02d2 test_case -00:02ef restore_mbc1 -00:02f8 switch_bank -00:0309 fetch_expected_value -00:0328 c000_functions_end -00:0328 expected_banks +00:0172 fail@quit_inline_1 +00:020b c000_functions_start +00:020b run_test_suite +00:0228 run_test_suite@quit_inline_2 +00:0239 run_tests +00:0247 run_test_cases +00:0255 test_case +00:0272 restore_mbc1 +00:027b switch_bank +00:028c fetch_expected_value +00:02ab c000_functions_end +00:02ab expected_banks + +[definitions] +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000180 _sizeof_expected_banks +0000001b _sizeof_main +000000a0 _sizeof_fail +00000000 _sizeof_c000_functions_start +0000002e _sizeof_run_test_suite +0000000e _sizeof_run_tests +0000000e _sizeof_run_test_cases +0000001d _sizeof_test_case +00000009 _sizeof_restore_mbc1 +00000011 _sizeof_switch_bank +0000001f _sizeof_fetch_expected_value diff --git a/cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/baseline_0000.png b/cinema/gb/mooneye-gb/emulator-only/mbc1_rom_4banks/baseline_0000.png deleted file mode 100644 index 30590ffab18e5deb12be845930a52ab18642fc14..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 518 zcmeAS@N?(olHy`uVBq!ia0vp^3xIe62NRHFxc>b*0|Vn(PZ!6KiaBquU+ii&U|?{x z{qsNmo1B;Hnym>_oA=IKKFMK%PG{+y=amayKVL83P|Yc$UNGlCA=7aXVT-=? z!k=yOkD14xIsL}yU*6ou>NjH3zniQ39G*S5wqpCv-MoGwmU%1ReYcCb`1o>KP3^w? ztOf5>mpy*jtQ#kFe`4bIZO>aK*KeA(W&QeB-gmZts{j0uW&QSw+MxBj7WH4RJhN-X q{>0ypYS_V6!tEYqAjbqaH2yLz>&fNk@rld;#jmHUpUXO@geCx}Th!

. -; wla symbolic information for "/Users/jeffrey/Scratch/mooneye-gb/tests/build/emulator-only/mbc1_rom_4banks.gb". - -[labels] -0001:4bf3 print_load_font -0001:4c00 print_string -0001:4c0a print_a -0001:4c14 print_newline -0001:4c1f print_digit -0001:4c2c print_regs -0001:4c35 _print_sl_data0 -0001:4c3b _print_sl_out0 -0001:4c48 _print_sl_data1 -0001:4c4e _print_sl_out1 -0001:4c60 _print_sl_data2 -0001:4c66 _print_sl_out2 -0001:4c73 _print_sl_data3 -0001:4c79 _print_sl_out3 -0001:4c8b _print_sl_data4 -0001:4c91 _print_sl_out4 -0001:4c9e _print_sl_data5 -0001:4ca4 _print_sl_out5 -0001:4cb6 _print_sl_data6 -0001:4cbc _print_sl_out6 -0001:4cc9 _print_sl_data7 -0001:4ccf _print_sl_out7 -0001:4001 font -0000:c000 regs_save -0000:c000 regs_save.f -0000:c001 regs_save.a -0000:c002 regs_save.c -0000:c003 regs_save.b -0000:c004 regs_save.e -0000:c005 regs_save.d -0000:c006 regs_save.l -0000:c007 regs_save.h -0000:c008 regs_flags -0000:c009 regs_assert -0000:c009 regs_assert.f -0000:c00a regs_assert.a -0000:c00b regs_assert.c -0000:c00c regs_assert.b -0000:c00d regs_assert.e -0000:c00e regs_assert.d -0000:c00f regs_assert.l -0000:c010 regs_assert.h -0000:c011 memdump_len -0000:c012 memdump_addr -0001:47f1 memcpy -0001:47fa memset -0001:4803 clear_vram -0001:480e reset_screen -0001:481b process_results -0001:4820 _wait_ly_0 -0001:4826 _wait_ly_1 -0001:4842 _wait_ly_2 -0001:4848 _wait_ly_3 -0001:4861 _process_results_cb -0001:486c _print_sl_data8 -0001:4876 _print_sl_out8 -0001:4890 _print_sl_data9 -0001:489b _print_sl_out9 -0001:48b3 _print_sl_data10 -0001:48bf _print_sl_out10 -0001:48c0 dump_mem -0001:48d0 _wait_ly_4 -0001:48d6 _wait_ly_5 -0001:48f2 _dump_mem_line -0001:491c _check_asserts -0001:492a _print_sl_data11 -0001:492d _print_sl_out11 -0001:4939 _print_sl_data12 -0001:493b _print_sl_out12 -0001:4943 _print_sl_data13 -0001:4946 _print_sl_out13 -0001:4950 __check_assert_fail0 -0001:495b _print_sl_data14 -0001:495e _print_sl_out14 -0001:4961 __check_assert_ok0 -0001:4969 _print_sl_data15 -0001:496e _print_sl_out15 -0001:4970 __check_assert_skip0 -0001:4978 _print_sl_data16 -0001:4980 _print_sl_out16 -0001:4980 __check_assert_out0 -0001:498c _print_sl_data17 -0001:498e _print_sl_out17 -0001:4996 _print_sl_data18 -0001:4999 _print_sl_out18 -0001:49a3 __check_assert_fail1 -0001:49ae _print_sl_data19 -0001:49b1 _print_sl_out19 -0001:49b4 __check_assert_ok1 -0001:49bc _print_sl_data20 -0001:49c1 _print_sl_out20 -0001:49c3 __check_assert_skip1 -0001:49cb _print_sl_data21 -0001:49d3 _print_sl_out21 -0001:49d3 __check_assert_out1 -0001:49de _print_sl_data22 -0001:49e1 _print_sl_out22 -0001:49ed _print_sl_data23 -0001:49ef _print_sl_out23 -0001:49f7 _print_sl_data24 -0001:49fa _print_sl_out24 -0001:4a04 __check_assert_fail2 -0001:4a0f _print_sl_data25 -0001:4a12 _print_sl_out25 -0001:4a15 __check_assert_ok2 -0001:4a1d _print_sl_data26 -0001:4a22 _print_sl_out26 -0001:4a24 __check_assert_skip2 -0001:4a2c _print_sl_data27 -0001:4a34 _print_sl_out27 -0001:4a34 __check_assert_out2 -0001:4a40 _print_sl_data28 -0001:4a42 _print_sl_out28 -0001:4a4a _print_sl_data29 -0001:4a4d _print_sl_out29 -0001:4a57 __check_assert_fail3 -0001:4a62 _print_sl_data30 -0001:4a65 _print_sl_out30 -0001:4a68 __check_assert_ok3 -0001:4a70 _print_sl_data31 -0001:4a75 _print_sl_out31 -0001:4a77 __check_assert_skip3 -0001:4a7f _print_sl_data32 -0001:4a87 _print_sl_out32 -0001:4a87 __check_assert_out3 -0001:4a92 _print_sl_data33 -0001:4a95 _print_sl_out33 -0001:4aa1 _print_sl_data34 -0001:4aa3 _print_sl_out34 -0001:4aab _print_sl_data35 -0001:4aae _print_sl_out35 -0001:4ab8 __check_assert_fail4 -0001:4ac3 _print_sl_data36 -0001:4ac6 _print_sl_out36 -0001:4ac9 __check_assert_ok4 -0001:4ad1 _print_sl_data37 -0001:4ad6 _print_sl_out37 -0001:4ad8 __check_assert_skip4 -0001:4ae0 _print_sl_data38 -0001:4ae8 _print_sl_out38 -0001:4ae8 __check_assert_out4 -0001:4af4 _print_sl_data39 -0001:4af6 _print_sl_out39 -0001:4afe _print_sl_data40 -0001:4b01 _print_sl_out40 -0001:4b0b __check_assert_fail5 -0001:4b16 _print_sl_data41 -0001:4b19 _print_sl_out41 -0001:4b1c __check_assert_ok5 -0001:4b24 _print_sl_data42 -0001:4b29 _print_sl_out42 -0001:4b2b __check_assert_skip5 -0001:4b33 _print_sl_data43 -0001:4b3b _print_sl_out43 -0001:4b3b __check_assert_out5 -0001:4b46 _print_sl_data44 -0001:4b49 _print_sl_out44 -0001:4b55 _print_sl_data45 -0001:4b57 _print_sl_out45 -0001:4b5f _print_sl_data46 -0001:4b62 _print_sl_out46 -0001:4b6c __check_assert_fail6 -0001:4b77 _print_sl_data47 -0001:4b7a _print_sl_out47 -0001:4b7d __check_assert_ok6 -0001:4b85 _print_sl_data48 -0001:4b8a _print_sl_out48 -0001:4b8c __check_assert_skip6 -0001:4b94 _print_sl_data49 -0001:4b9c _print_sl_out49 -0001:4b9c __check_assert_out6 -0001:4ba8 _print_sl_data50 -0001:4baa _print_sl_out50 -0001:4bb2 _print_sl_data51 -0001:4bb5 _print_sl_out51 -0001:4bbf __check_assert_fail7 -0001:4bca _print_sl_data52 -0001:4bcd _print_sl_out52 -0001:4bd0 __check_assert_ok7 -0001:4bd8 _print_sl_data53 -0001:4bdd _print_sl_out53 -0001:4bdf __check_assert_skip7 -0001:4be7 _print_sl_data54 -0001:4bef _print_sl_out54 -0001:4bef __check_assert_out7 -0000:01c8 _wait_ly_6 -0000:01ce _wait_ly_7 -0000:01ea _wait_ly_8 -0000:01f0 _wait_ly_9 -0000:0209 _test_ok_cb_0 -0000:0211 _print_sl_data55 -0000:0219 _print_sl_out55 -0000:021c switch_bank -0000:0225 test_mbc -0000:0236 _wait_ly_10 -0000:023c _wait_ly_11 -0000:0258 _wait_ly_12 -0000:025e _wait_ly_13 -0000:0277 _test_failure_cb_0 -0000:027f _print_sl_data56 -0000:028b _print_sl_out56 diff --git a/cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.gb b/cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.gb index 05b502f2679fe959f5593400f6298c75dc42c4a4..e6393560ebadcda7fbfbc14e257185054f8e1047 100644 GIT binary patch delta 243 zcmZo@U}|V!+Th1npL*f*Sr(78AKcFhd)WPd+N|N0ev0m%spzZ4t(3vOX# zOaQ4k+yFG{ADafUyq&@WH-<6>hRtUgmEA(uKX7{B{J{Hxm!04P2fIHH+z)Gl&8<5D zG41relZpZjf(#CfAJ`8Atz`JexPW2(VUW8T7#S2mtcr~%q?ClYCBBCPSyf8h5f{DD;nM079%0If4>82|tP delta 1432 zcmZXUL1^1n9LE1oj-AwY6D#UckwWw2mf}(vIW5^>Zk)unT#FiF(;Rw8M-Mx+^fER^ zl1+l`u+htQT23SMG6;;cBoNv|5DkRAMkWGH~+fnGZh9gZ^Fxm)tai ztfi;t%GFx4Ri0}?KrQy2Wan_e-6~9wb)LzTn$7ZDtJb(ELxtMnR^d1X$rB#Qw#v;G zt(0n3c^15m>VDH1c9%Pv%cisW?&BVZnmZp3y9~m z2-RQmr@%qi=W&t+@==Y=nxGW?nZkKe=29sEX^0!2PzZ_J2-EJ}f{IY`x$q4N$Mi9q ze92|9QAdKFBj0m5K*b0AIx<(dr&NI45^EU~ka;9#-V?rHl3lJO@;R3h$#$kA@|4=( zH?iRz*UB`I#0CC1tRaC7*|_0^@OuqsxsnZ&T*?OjG9oSRDKkJWiKPswATkppZ=i4E z*7canJSLepxs*&c^{)cNw)!eI{LZB^3uH^&U=2xZ7>pYp3%^(Jf-70@50kbo8~kg? zggSeCr3@s^uM&*ehs>ifGcWuebDS&5JkO;>vZ3cho(=s47JSB~Vgk9wu56t*^kYLV zZum~D=r#Pzm26n$Qa1QY$lT=CaxwAxKiDi8V}jORU#lq|M| zDN0K?278T8kXCF}dX}bPiAJtlb}u_Evv!=FIh_3^_Ge{uEw;*sqxWOql+mZLWgU!q P(Z(N1I=Zo!4E6s2G1tW; diff --git a/cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.sym b/cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.sym index cfaa2ab88..a1b80f1ce 100644 --- a/cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.sym +++ b/cinema/gb/mooneye-gb/madness/mgb_oam_dma_halt_sprites/test.sym @@ -1,200 +1,38 @@ ; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/madness/mgb_oam_dma_halt_sprites.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/madness/mgb_oam_dma_halt_sprites.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:481f clear_oam +01:4829 clear_vram +01:4804 disable_lcd_safe +01:480a disable_lcd_safe@wait_ly_0 +01:4833 memcpy +01:483c memset +01:4813 print_load_font +01:47f0 reset_screen 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0199 _wait_ly_4 -00:019f _wait_ly_5 +00:0150 main +00:0199 main@wait_ly_5 +00:019f main@wait_ly_6 00:01b4 hiram_test -00:01b9 _wait_ly_6 -00:01bf _wait_ly_7 +00:01b9 hiram_test@wait_ly_7 +00:01bf hiram_test@wait_ly_8 00:01cc vram_checkerboard 00:05cc vram_checkerboard_end 00:05cc initial_data 00:05d4 initial_data_end + +[definitions] +0000000a _sizeof_clear_oam +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_load_font +00000014 _sizeof_reset_screen +000007f0 _sizeof_font +00000064 _sizeof_main +00000018 _sizeof_hiram_test +00000400 _sizeof_vram_checkerboard +00000000 _sizeof_vram_checkerboard_end +00000008 _sizeof_initial_data diff --git a/cinema/gb/mooneye-gb/manual-only/sprite_priority/test.gb b/cinema/gb/mooneye-gb/manual-only/sprite_priority/test.gb index 9df4d749dac105b324ce16c667aba189ff236fce..734b3f64a122133374a024f950c8f1d848bb7c65 100644 GIT binary patch delta 182 zcmZo@U}|V!+Th3N!BPMDEQ`n45AJ7$J?#F!^7wBT`pWbFS$PjdhJS)H85yTAoHh1P zbohVz9EkY$!R24S!Y?2>0ZhW#4x4Kkv+OoGd|(e<|G?>i^8@b(UUq^H9PIu)a6haG zHlXeVMBC|oClv)61Q{F{Kd>JLn$7T!aRI~n!!|%x10#b1h*h!igp`snx5W2wAgfA= MTjIxNMW)^60GX;(vj6}9 delta 1365 zcmY+EQAiVU9LN9vo71^X-8{2PA^%$uiy%gUTF~6oxtlv2Y%3pnkm#WYqn8LmtsB%! z_>vUlQ&=xS5LO0KkR1u)aa=)AJr#S19#({4V2;}Q{r~^nA04~nzTf-)Ki}W|*{xWV zibd(^81A)RZ`ub{`-E!OGO=1&t;J54(>1$G4WVkVi1A%yZ=^!;n)QyJsz~`qJlVjV z2ROX+1}9>3fql>88%_GvXX{;I*{5uc!_`#Sr~IML3USK^e9G@WGlYs5k;T>R6manZ zVpjmXzP>SBy+tZ;zD+9Din&-CEDe=1rO{Zh6p#HarB(x~7%)WU?V`#C*|}`$kxu-L zu2y%aXMf9~Jx9YZWe^#7R<-?_;>{&f>3kuX%Ojg;^xIF*6_2qT>BEaG<4ff8$y_0w z9TTBQdTKec7lQZ$i}(x4e1VK4(pqvDndP8yt=w+Rlx2fXr?dSFq4|nzj91!?i7C5N zn}(wc4!IIEPDR@2lJ7m$4)Oz_%2#JQ7sp|e3EZ2ev$_aD)=*>sCz+HI2xs|?lLS?; zk*#=*mysYq@dfUO2%Mm z%#(%?KEsz%qy$KxgS-U34qI1e&ajwZ&N3;Obn5#YM7R1pG(2Ha8b)}T-=Ga{XlQjB z-gCcR@P#Q+@RLei5e?QPFj0m+zLZ4R%dT9M*#OKIhZ*L6of&0HFb9|vNIGhw3a$+Td?)MhA945B#RXo5cx(_2N6hOkT7GE-L6KB8Gs#RqT1ubxJf^*5Wb zwuP#%. -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/manual-only/sprite_priority.gb". +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/manual-only/sprite_priority.gb". [labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:481f clear_oam +01:4829 clear_vram +01:4804 disable_lcd_safe +01:480a disable_lcd_safe@wait_ly_0 +01:4833 memcpy +01:483c memset +01:4813 print_load_font +01:47f0 reset_screen 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0180 data -00:0214 data_end +00:0150 main +00:017d main@wait_ly_5 +00:0183 main@wait_ly_6 +00:0189 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bb clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48cf memcpy +01:48d8 memset +01:4898 print_hex4 +01:48c5 print_hex8 +01:48e8 print_inline_string +01:48a4 print_load_font +01:48b0 print_newline +01:48e1 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c017 regs_save -00:c017 regs_save.f -00:c018 regs_save.a -00:c019 regs_save.c -00:c01a regs_save.b -00:c01b regs_save.e -00:c01c regs_save.d -00:c01d regs_save.l -00:c01e regs_save.h -00:c01f regs_flags -00:c020 regs_assert -00:c020 regs_assert.f -00:c021 regs_assert.a -00:c022 regs_assert.c -00:c023 regs_assert.b -00:c024 regs_assert.e -00:c025 regs_assert.d -00:c026 regs_assert.l -00:c027 regs_assert.h -00:c028 memdump_len -00:c029 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 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was created with wlalink by ville helin . +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/boot_div-A.gb". + +[labels] +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h diff --git a/cinema/gb/mooneye-gb/misc/boot_div-cgb0/manifest.yml b/cinema/gb/mooneye-gb/misc/boot_div-cgb0/manifest.yml new file mode 100644 index 000000000..a697ada66 --- /dev/null +++ b/cinema/gb/mooneye-gb/misc/boot_div-cgb0/manifest.yml @@ -0,0 +1 @@ +fail: true diff --git a/cinema/gb/mooneye-gb/misc/boot_div-cgb0/test.gb b/cinema/gb/mooneye-gb/misc/boot_div-cgb0/test.gb new file mode 100644 index 0000000000000000000000000000000000000000..c6e6a73082b47511ae45c703037a5502b63a7027 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check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 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index 000000000..a697ada66 --- /dev/null +++ b/cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/manifest.yml @@ -0,0 +1 @@ +fail: true diff --git a/cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/test.gb b/cinema/gb/mooneye-gb/misc/boot_div-cgbABCDE/test.gb new file mode 100644 index 0000000000000000000000000000000000000000..5f5271cd959d09a8888140b740309c0cedc528d0 GIT binary patch literal 32768 zcmeI4UrZE79LJaQiYuU9ikgLPbh%vcplA?DdLh@%vaEQpBu8wChLT7@K+_h8@PK%p zP-}~S;ejTakeEK%H`*s-Oqw(V^-5<`N#*#l@Ffq}i67Z-43OxwT%(Uo$A3lnSKvl3ciT{Is;;_N~78J9mD( zbp3j7SKo%8Z{4|l>GJh!yNnO}`}?|&c5ma`mbV9c%grxcj3UozJ=Jrp8Gq;7w>*Q_h6^w&bZ_58TYh%&OPg1aL>Dw z?u4<;Jy$xunEJs8xo6S&iFGcZGjEi;=h3-mRJfDq{AyIX6X-m;U+V3d{j%xhKK`_N zB0vO)01+SpM1Tko0U|&IhyW2F0z`la5CI}U1c(3;AOb{y2oM1xKm>>Y5g-CYfCvx) zB0vO)01+SpM1Tko0U|&IhyW2F0z`la5CI}U1c(3;AOb{y2oM1xKm=YO0*PgUe?woU zCP@GP@p$r81M-qck}Sg(VzSaF6pF|BgK=5jvLzJKw7k4X1Q8t_Q&WcyZQfj7o|_B1 zrs+(Ii_6N2i@86~i#|k_6$KuO!pHILXM%CqD=IY2Ff^^A0vZGpGz_#{7p;hZ9*Kz2 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check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h diff --git a/cinema/gb/mooneye-gb/misc/boot_hwio-C/baseline_0000.png b/cinema/gb/mooneye-gb/misc/boot_hwio-C/baseline_0000.png index 30590ffab18e5deb12be845930a52ab18642fc14..f9e5e47b50a4d548ddbc988a8e76364d30f505cf 100644 GIT binary patch delta 218 zcmV<0044v11ds%fB!AaQL_t(|obA`qYQiu8K+$CQ|G(Tl6vCKm=caCOJ?BAUf<|&_ zrE}Z1LD$=V{{Ws#;5dQf1dbCpPT)9!<1S;2Ip_7lpFJP1-PewD&M(LO!etzs?3!8Q zqowQl+moEPRQG&Sq{(#r&jbT1+as81;-49-wi_@% delta 210 zcmV;@04@KJ1cn5VB!A6GL_t(|obA`qii0o!06{(c|6leVN=2--V3mWtnWvIKkSvLH zoacF<>*uc@fO`oXCvcp=aRSE)94BzxGz`Nyj;|B*Ja5J~U(CzwGX8Fz<0sf%XZJTJ zOv9U3 zuj)(OxAK4U;RLU@czsf@x}uNQdCa<~zhV30dz>% diff --git a/cinema/gb/mooneye-gb/misc/boot_hwio-C/test.gb b/cinema/gb/mooneye-gb/misc/boot_hwio-C/test.gb index 214a87ab710db2a9756cc1a4d833b14e5ca281f8..429c65d2d1ba7f34a4644a973052da7be4dea6e3 100644 GIT binary patch delta 553 zcmZo@U}|V!+Th1nzkaDA!+${+CMkd6I``9+8mv+~4&7%IRt9nkkvW;joJ3?!Br+!u znd6DfafEYf|1}&6WBjamj`8q^diS#%JkGxG2uUq2QSkR>5Mwy`s_B2ltLFc;uNwZ> zylVXaS@A1SojXvCuV=8YV~Dedf@6q+3d66)|7VYS{AvJ^ATz+mxJCrHI)}KrC@}nL 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:48bb clear_vram +01:487a disable_lcd_safe +01:4880 disable_lcd_safe@wait_ly_0 +01:48cf memcpy +01:48d8 memset +01:4898 print_hex4 +01:48c5 print_hex8 +01:48e8 print_inline_string +01:48a4 print_load_font +01:48b0 print_newline +01:48e1 print_string +01:47f0 quit +01:4805 quit@cb_return +01:480a quit@wait_ly_1 +01:4810 quit@wait_ly_2 +01:4816 quit@wait_ly_3 +01:481c quit@wait_ly_4 +01:4826 quit@success +01:484d quit@failure +01:4862 quit@halt +01:4863 quit@halt_execution_0 +01:4866 reset_screen +01:4889 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01db _wait_ly_4 -00:01e1 _wait_ly_5 -00:01f7 _print_results_halt_1 -00:01fa _test_ok_cb_0 -00:0202 _print_sl_data55 -00:020a _print_sl_out55 -00:020d mismatch -00:0230 _wait_ly_6 -00:0236 _wait_ly_7 -00:024c _print_results_halt_2 -00:024f mismatch_cb -00:0257 _print_sl_data56 -00:0265 _print_sl_out56 -00:027f _print_sl_data57 -00:0289 _print_sl_out57 -00:029a _print_sl_data58 -00:02a4 _print_sl_out58 -00:02ad hwio_data -00:c014 mismatch_addr -00:c016 mismatch_data -00:c017 mismatch_mem +00:0150 main +00:01ce main@quit_inline_1 +00:01df mismatch +00:01f5 mismatch@quit_inline_2 +00:0244 hwio_data +00:ff80 mismatch_addr +00:ff82 mismatch_data +00:ff83 mismatch_mem + +[definitions] +0000000a _sizeof_clear_vram +0000000f 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e 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[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte 01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:01d2 invalid_sp -00:01e6 _wait_ly_4 -00:01ec _wait_ly_5 -00:0202 _print_results_halt_1 -00:0205 _test_failure_cb_0 -00:020d _print_sl_data55 -00:021e _print_sl_out55 -00:c014 sp_save +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e 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r5CI}U1c(3;AOb{y2oM1xKm>>Y5g-CYfCvx)B0vO)01+Spw~N3xZ%VH; diff --git a/cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.sym b/cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.sym deleted file mode 100644 index 7ebdacba7..000000000 --- a/cinema/gb/mooneye-gb/misc/gpu/vblank_stat_intr-C/test.sym +++ /dev/null @@ -1,216 +0,0 @@ -; this file was created with wlalink by ville helin . -; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/misc/gpu/vblank_stat_intr-C.gb". - -[labels] -01:4bff print_load_font -01:4c0c print_string -01:4c16 print_a -01:4c20 print_newline -01:4c2b print_digit -01:4c38 print_regs -01:4c41 _print_sl_data0 -01:4c47 _print_sl_out0 -01:4c54 _print_sl_data1 -01:4c5a _print_sl_out1 -01:4c6c _print_sl_data2 -01:4c72 _print_sl_out2 -01:4c7f _print_sl_data3 -01:4c85 _print_sl_out3 -01:4c97 _print_sl_data4 -01:4c9d _print_sl_out4 -01:4caa _print_sl_data5 -01:4cb0 _print_sl_out5 -01:4cc2 _print_sl_data6 -01:4cc8 _print_sl_out6 -01:4cd5 _print_sl_data7 -01:4cdb _print_sl_out7 -01:4000 font -00:c000 regs_save -00:c000 regs_save.f -00:c001 regs_save.a -00:c002 regs_save.c -00:c003 regs_save.b -00:c004 regs_save.e -00:c005 regs_save.d -00:c006 regs_save.l -00:c007 regs_save.h -00:c008 regs_flags -00:c009 regs_assert -00:c009 regs_assert.f -00:c00a regs_assert.a -00:c00b regs_assert.c -00:c00c regs_assert.b -00:c00d regs_assert.e -00:c00e regs_assert.d -00:c00f regs_assert.l -00:c010 regs_assert.h -00:c011 memdump_len -00:c012 memdump_addr -01:47f0 memcpy -01:47f9 memset -01:4802 memcmp -01:4810 clear_vram -01:481a clear_oam -01:4824 disable_lcd_safe -01:482a _wait_ly_0 -01:4830 _wait_ly_1 -01:4839 reset_screen -01:484d process_results -01:4861 _wait_ly_2 -01:4867 _wait_ly_3 -01:487d _print_results_halt_0 -01:4880 _process_results_cb -01:488b _print_sl_data8 -01:4895 _print_sl_out8 -01:48af _print_sl_data9 -01:48ba _print_sl_out9 -01:48d2 _print_sl_data10 -01:48de _print_sl_out10 -01:48df dump_mem -01:48fe _dump_mem_line -01:4928 _check_asserts -01:4936 _print_sl_data11 -01:4939 _print_sl_out11 -01:4945 _print_sl_data12 -01:4947 _print_sl_out12 -01:494f _print_sl_data13 -01:4952 _print_sl_out13 -01:495c __check_assert_fail0 -01:4967 _print_sl_data14 -01:496a _print_sl_out14 -01:496d __check_assert_ok0 -01:4975 _print_sl_data15 -01:497a _print_sl_out15 -01:497c __check_assert_skip0 -01:4984 _print_sl_data16 -01:498c _print_sl_out16 -01:498c __check_assert_out0 -01:4998 _print_sl_data17 -01:499a _print_sl_out17 -01:49a2 _print_sl_data18 -01:49a5 _print_sl_out18 -01:49af __check_assert_fail1 -01:49ba _print_sl_data19 -01:49bd _print_sl_out19 -01:49c0 __check_assert_ok1 -01:49c8 _print_sl_data20 -01:49cd _print_sl_out20 -01:49cf __check_assert_skip1 -01:49d7 _print_sl_data21 -01:49df _print_sl_out21 -01:49df __check_assert_out1 -01:49ea _print_sl_data22 -01:49ed _print_sl_out22 -01:49f9 _print_sl_data23 -01:49fb _print_sl_out23 -01:4a03 _print_sl_data24 -01:4a06 _print_sl_out24 -01:4a10 __check_assert_fail2 -01:4a1b _print_sl_data25 -01:4a1e _print_sl_out25 -01:4a21 __check_assert_ok2 -01:4a29 _print_sl_data26 -01:4a2e _print_sl_out26 -01:4a30 __check_assert_skip2 -01:4a38 _print_sl_data27 -01:4a40 _print_sl_out27 -01:4a40 __check_assert_out2 -01:4a4c _print_sl_data28 -01:4a4e _print_sl_out28 -01:4a56 _print_sl_data29 -01:4a59 _print_sl_out29 -01:4a63 __check_assert_fail3 -01:4a6e _print_sl_data30 -01:4a71 _print_sl_out30 -01:4a74 __check_assert_ok3 -01:4a7c _print_sl_data31 -01:4a81 _print_sl_out31 -01:4a83 __check_assert_skip3 -01:4a8b _print_sl_data32 -01:4a93 _print_sl_out32 -01:4a93 __check_assert_out3 -01:4a9e _print_sl_data33 -01:4aa1 _print_sl_out33 -01:4aad _print_sl_data34 -01:4aaf _print_sl_out34 -01:4ab7 _print_sl_data35 -01:4aba _print_sl_out35 -01:4ac4 __check_assert_fail4 -01:4acf _print_sl_data36 -01:4ad2 _print_sl_out36 -01:4ad5 __check_assert_ok4 -01:4add _print_sl_data37 -01:4ae2 _print_sl_out37 -01:4ae4 __check_assert_skip4 -01:4aec _print_sl_data38 -01:4af4 _print_sl_out38 -01:4af4 __check_assert_out4 -01:4b00 _print_sl_data39 -01:4b02 _print_sl_out39 -01:4b0a _print_sl_data40 -01:4b0d _print_sl_out40 -01:4b17 __check_assert_fail5 -01:4b22 _print_sl_data41 -01:4b25 _print_sl_out41 -01:4b28 __check_assert_ok5 -01:4b30 _print_sl_data42 -01:4b35 _print_sl_out42 -01:4b37 __check_assert_skip5 -01:4b3f _print_sl_data43 -01:4b47 _print_sl_out43 -01:4b47 __check_assert_out5 -01:4b52 _print_sl_data44 -01:4b55 _print_sl_out44 -01:4b61 _print_sl_data45 -01:4b63 _print_sl_out45 -01:4b6b _print_sl_data46 -01:4b6e _print_sl_out46 -01:4b78 __check_assert_fail6 -01:4b83 _print_sl_data47 -01:4b86 _print_sl_out47 -01:4b89 __check_assert_ok6 -01:4b91 _print_sl_data48 -01:4b96 _print_sl_out48 -01:4b98 __check_assert_skip6 -01:4ba0 _print_sl_data49 -01:4ba8 _print_sl_out49 -01:4ba8 __check_assert_out6 -01:4bb4 _print_sl_data50 -01:4bb6 _print_sl_out50 -01:4bbe _print_sl_data51 -01:4bc1 _print_sl_out51 -01:4bcb __check_assert_fail7 -01:4bd6 _print_sl_data52 -01:4bd9 _print_sl_out52 -01:4bdc __check_assert_ok7 -01:4be4 _print_sl_data53 -01:4be9 _print_sl_out53 -01:4beb __check_assert_skip7 -01:4bf3 _print_sl_data54 -01:4bfb _print_sl_out54 -01:4bfb __check_assert_out7 -00:0169 fail_halt -00:017d _wait_ly_4 -00:0183 _wait_ly_5 -00:0199 _print_results_halt_1 -00:019c _test_failure_cb_0 -00:01a4 _print_sl_data55 -00:01a9 _print_sl_out55 -00:01ac test_round1 -00:01b8 _wait_ly_6 -00:0203 finish_round1 -00:0221 test_round2 -00:022d _wait_ly_7 -00:0279 finish_round2 -00:029b test_round3 -00:02a7 _wait_ly_8 -00:02f1 finish_round3 -00:030f test_round4 -00:031b _wait_ly_9 -00:0366 finish_round4 -00:0368 test_finish -00:c014 intr_vec_vblank -00:c017 intr_vec_stat -00:c01a round1 -00:c01b round2 -00:c01c round3 diff --git a/cinema/gb/mooneye-gb/acceptance/hdma_lcdc/manifest.yml b/cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/manifest.yml similarity index 68% rename from cinema/gb/mooneye-gb/acceptance/hdma_lcdc/manifest.yml rename to cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/manifest.yml index 6cd567986..c9aa5eb1d 100644 --- a/cinema/gb/mooneye-gb/acceptance/hdma_lcdc/manifest.yml +++ b/cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/manifest.yml @@ -1,2 +1,3 @@ config: gb.model: CGB +fail: true diff --git a/cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/test.gb b/cinema/gb/mooneye-gb/misc/ppu/vblank_stat_intr-C/test.gb new file mode 100644 index 0000000000000000000000000000000000000000..ccd80619a977dac2c07421f7c670b569277b733a GIT binary patch literal 32768 zcmeI4Uq~EB7{KS&tJ$bY)*5BCOR{$y_F_#iM(82eWpCY>(-lr^B*6-?8cn2)N|e@^ z%SD@}HGfS&h=Nf1l)l+Mg%Bu|!;s^0r7tNIlCph>52X!TB($+@uJheEJ&k>^2o=ir zal1F)eE(*CGjrgBlTNQs;@4Sxd~$txHY%FLn_XZ3+|zS^3(3zJB6Odd}?a+#Gc_uS(D4%szW_1Nl zmd0V;b+T->``+|Mh zzGPpuuh`e@3Azg|d&bkrZ#80Hg2wl>=PESjY0njCJX!EK2k8FTsB?gIkpL1v0!RP} zAOR$R1dsp{Kmter2_OL^fCP{L5oPHilR~}EiErE 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zU-;-m{&Utg>^j@B8?{1P*Z!~%#7|pLGBcR8El6V{peolkZK&-Z`hOL)kri>R~lDeGzS_0(bOm-u08_=|gG-lBZ@ z*F&^5;?0+T%gecW&nrLsD)p%~m)Q8f7jOhf00|%gB!C2v01`j~NB{{S0VIF~kN^@u z0!RP}AOR$R1dsp{Kmter2_OL^fCP{L5. +; wla symbolic information for "/home/vicki/Scratch/mooneye-gb/tests/build/misc/ppu/vblank_stat_intr-C.gb". + +[labels] +01:47f0 check_asserts_cb +01:4842 check_asserts_cb@check_asserts +01:4864 check_asserts_cb@fail0 +01:4870 check_asserts_cb@ok0 +01:487a check_asserts_cb@skip0 +01:4885 check_asserts_cb@out0 +01:489c check_asserts_cb@fail1 +01:48a8 check_asserts_cb@ok1 +01:48b2 check_asserts_cb@skip1 +01:48bd check_asserts_cb@out1 +01:48dd check_asserts_cb@fail2 +01:48e9 check_asserts_cb@ok2 +01:48f3 check_asserts_cb@skip2 +01:48fe check_asserts_cb@out2 +01:4915 check_asserts_cb@fail3 +01:4921 check_asserts_cb@ok3 +01:492b check_asserts_cb@skip3 +01:4936 check_asserts_cb@out3 +01:4956 check_asserts_cb@fail4 +01:4962 check_asserts_cb@ok4 +01:496c check_asserts_cb@skip4 +01:4977 check_asserts_cb@out4 +01:498e check_asserts_cb@fail5 +01:499a check_asserts_cb@ok5 +01:49a4 check_asserts_cb@skip5 +01:49af check_asserts_cb@out5 +01:49cf check_asserts_cb@fail6 +01:49db check_asserts_cb@ok6 +01:49e5 check_asserts_cb@skip6 +01:49f0 check_asserts_cb@out6 +01:4a07 check_asserts_cb@fail7 +01:4a13 check_asserts_cb@ok7 +01:4a1d check_asserts_cb@skip7 +01:4a28 check_asserts_cb@out7 +01:4b7b clear_vram +01:4b3a disable_lcd_safe +01:4b40 disable_lcd_safe@wait_ly_0 +01:4b8f memcpy +01:4b98 memset +01:4b58 print_hex4 +01:4b85 print_hex8 +01:4ba8 print_inline_string +01:4b64 print_load_font +01:4b70 print_newline +01:4a2b print_reg_dump +01:4ba1 print_string +01:4ab0 quit +01:4ac5 quit@cb_return +01:4aca quit@wait_ly_1 +01:4ad0 quit@wait_ly_2 +01:4ad6 quit@wait_ly_3 +01:4adc quit@wait_ly_4 +01:4ae6 quit@success +01:4b0d quit@failure +01:4b22 quit@halt +01:4b23 quit@halt_execution_0 +01:4b26 reset_screen +01:4b49 serial_send_byte +01:4000 font +00:ff80 v_regs_save +00:ff80 v_regs_save.reg_f +00:ff81 v_regs_save.reg_a +00:ff82 v_regs_save.reg_c +00:ff83 v_regs_save.reg_b +00:ff84 v_regs_save.reg_e +00:ff85 v_regs_save.reg_d +00:ff86 v_regs_save.reg_l +00:ff87 v_regs_save.reg_h +00:ff88 v_regs_flags +00:ff89 v_regs_assert +00:ff89 v_regs_assert.reg_f +00:ff8a v_regs_assert.reg_a +00:ff8b v_regs_assert.reg_c +00:ff8c v_regs_assert.reg_b +00:ff8d v_regs_assert.reg_e +00:ff8e v_regs_assert.reg_d +00:ff8f v_regs_assert.reg_l +00:ff90 v_regs_assert.reg_h +00:0150 main +00:0169 fail_halt +00:0170 fail_halt@quit_inline_1 +00:017e test_round1 +00:018a test_round1@wait_ly_5 +00:01d5 finish_round1 +00:01f3 test_round2 +00:01ff test_round2@wait_ly_6 +00:024b finish_round2 +00:026d test_round3 +00:0279 test_round3@wait_ly_7 +00:02c3 finish_round3 +00:02e1 test_round4 +00:02ed test_round4@wait_ly_8 +00:0338 finish_round4 +00:033a test_finish +00:ff91 intr_vec_vblank +00:ff94 intr_vec_stat +00:ff97 round1 +00:ff98 round2 +00:ff99 round3 + +[definitions] +0000023b _sizeof_check_asserts_cb +0000000a _sizeof_clear_vram +0000000f _sizeof_disable_lcd_safe +00000009 _sizeof_memcpy +00000009 _sizeof_memset +0000000c _sizeof_print_hex4 +0000000a _sizeof_print_hex8 +00000006 _sizeof_print_inline_string +0000000c _sizeof_print_load_font +0000000b _sizeof_print_newline +00000085 _sizeof_print_reg_dump +00000007 _sizeof_print_string +00000076 _sizeof_quit +00000014 _sizeof_reset_screen +0000000f _sizeof_serial_send_byte +000007f0 _sizeof_font +00000008 _sizeof_v_regs_save +00000001 _sizeof_v_regs_save.reg_f +00000001 _sizeof_v_regs_save.reg_a +00000001 _sizeof_v_regs_save.reg_c +00000001 _sizeof_v_regs_save.reg_b +00000001 _sizeof_v_regs_save.reg_e +00000001 _sizeof_v_regs_save.reg_d +00000001 _sizeof_v_regs_save.reg_l +00000001 _sizeof_v_regs_save.reg_h +00000001 _sizeof_v_regs_flags +00000008 _sizeof_v_regs_assert +00000001 _sizeof_v_regs_assert.reg_f +00000001 _sizeof_v_regs_assert.reg_a +00000001 _sizeof_v_regs_assert.reg_c +00000001 _sizeof_v_regs_assert.reg_b +00000001 _sizeof_v_regs_assert.reg_e +00000001 _sizeof_v_regs_assert.reg_d +00000001 _sizeof_v_regs_assert.reg_l +00000001 _sizeof_v_regs_assert.reg_h +00000003 _sizeof_intr_vec_vblank +00000003 _sizeof_intr_vec_stat +00000001 _sizeof_round1 +00000001 _sizeof_round2 +00000001 _sizeof_round3 +00000019 _sizeof_main +00000015 _sizeof_fail_halt +00000057 _sizeof_test_round1 +0000001e _sizeof_finish_round1 +00000058 _sizeof_test_round2 +00000022 _sizeof_finish_round2 +00000056 _sizeof_test_round3 +0000001e _sizeof_finish_round3 +00000057 _sizeof_test_round4 +00000002 _sizeof_finish_round4 diff --git a/cinema/gb/mooneye-gb/update.py b/cinema/gb/mooneye-gb/update.py index 6f126b349..f561ea38f 100644 --- a/cinema/gb/mooneye-gb/update.py +++ b/cinema/gb/mooneye-gb/update.py @@ -3,7 +3,7 @@ import os import os.path import shutil import yaml -from cinema.util import dictMerge +from cinema.util import dict_merge suffixes = { 'C': 'CGB', @@ -43,7 +43,7 @@ def ingestDirectory(path, dest): manifest = yaml.safe_load(f) or {} except IOError: pass - dictMerge(manifest, { + dict_merge(manifest, { 'config': { 'gb.model': model } From c471d03c7dfcd5048599aa5ab37b1e6e9fefae4b Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sat, 6 Jul 2019 16:10:20 -0700 Subject: [PATCH 07/20] Python: Play nice with venvs --- src/platform/python/CMakeLists.txt | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/platform/python/CMakeLists.txt b/src/platform/python/CMakeLists.txt index d743e9924..742ec69ca 100644 --- a/src/platform/python/CMakeLists.txt +++ b/src/platform/python/CMakeLists.txt @@ -1,5 +1,8 @@ -find_package(PythonLibs ${USE_PYTHON_VERSION}) +if(DEFINED ENV{VIRTUAL_ENV}) + find_program(PYTHON_EXECUTABLE NAMES python PATHS "$ENV{VIRTUAL_ENV}/bin") +endif() find_package(PythonInterp ${USE_PYTHON_VERSION}) +find_package(PythonLibs ${USE_PYTHON_VERSION}) list(APPEND DEPENDENCY_LIB ${PYTHON_LIBRARIES}) include_directories(AFTER ${PYTHON_INCLUDE_DIRS}) From 773e0d26ffd5e15c99d50bc6e5cb66fe167d85f4 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sat, 6 Jul 2019 16:13:39 -0700 Subject: [PATCH 08/20] GB Memory: Better emulate 0xFEA0 region on DMG, MGB and AGB --- CHANGES | 1 + src/gb/memory.c | 13 ++++++++++++- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/CHANGES b/CHANGES index a8304684e..b0e021ceb 100644 --- a/CHANGES +++ b/CHANGES @@ -34,6 +34,7 @@ Emulation fixes: - GB Audio: Deschedule channel 1 when disabled by sweep (fixes mgba.io/i/1467) - GBA Memory: Fix STM/LDM to invalid VRAM - GB: Fix savedata initialization (fixes mgba.io/i/1473, mgba.io/i/1478) + - GB Memory: Better emulate 0xFEA0 region on DMG, MGB and AGB Other fixes: - Qt: Fix some Qt display driver race conditions - Core: Improved lockstep driver reliability (Le Hoang Quyen) diff --git a/src/gb/memory.c b/src/gb/memory.c index 15ef917ad..b3b9b8bcf 100644 --- a/src/gb/memory.c +++ b/src/gb/memory.c @@ -234,7 +234,7 @@ uint8_t GBLoad8(struct LR35902Core* cpu, uint16_t address) { if (dmaBus != GB_BUS_CPU && dmaBus == accessBus) { return 0xFF; } - if (address >= GB_BASE_OAM && address < GB_BASE_UNUSABLE) { + if (address >= GB_BASE_OAM && address < GB_BASE_IO) { return 0xFF; } } @@ -471,6 +471,17 @@ uint8_t GBView8(struct LR35902Core* cpu, uint16_t address, int segment) { } if (address < GB_BASE_IO) { mLOG(GB_MEM, GAME_ERROR, "Attempt to read from unusable memory: %04X", address); + if (gb->video.mode < 2) { + switch (gb->model) { + case GB_MODEL_AGB: + return (address & 0xF0) | ((address >> 4) & 0xF); + case GB_MODEL_CGB: + // TODO: R/W behavior + return 0x00; + default: + return 0x00; + } + } return 0xFF; } if (address < GB_BASE_HRAM) { From 9fa7767ed9ea34ec8932c880d47eaebfccc844e6 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sun, 28 Jul 2019 10:15:31 -0700 Subject: [PATCH 09/20] GB MBC: Improve Wisdom Tree heuristic --- src/gb/mbc.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/src/gb/mbc.c b/src/gb/mbc.c index f499f5d18..5ba2d5f42 100644 --- a/src/gb/mbc.c +++ b/src/gb/mbc.c @@ -120,8 +120,8 @@ static bool _isMulticart(const uint8_t* mem) { return success; } -static bool _isWisdomTree(const uint8_t* mem) { - int i; +static bool _isWisdomTree(const uint8_t* mem, size_t size) { + size_t i; for (i = 0x134; i < 0x14C; i += 4) { if (*(uint32_t*) &mem[i] != 0) { return false; @@ -135,7 +135,12 @@ static bool _isWisdomTree(const uint8_t* mem) { if (mem[0x14D] != 0xE7) { return false; } - return true; + for (i = 0x300; i < size - 11; ++i) { + if (memcmp(&mem[i], "WISDOM", 6) == 0 && memcmp(&mem[i + 7], "TREE", 4) == 0) { + return true; + } + } + return false; } void GBMBCSwitchSramBank(struct GB* gb, int bank) { @@ -199,7 +204,7 @@ void GBMBCInit(struct GB* gb) { if (gb->memory.mbcType == GB_MBC_AUTODETECT) { switch (cart->type) { case 0: - if (_isWisdomTree(gb->memory.rom)) { + if (_isWisdomTree(gb->memory.rom, gb->memory.romSize)) { gb->memory.mbcType = GB_UNL_WISDOM_TREE; break; } From 2d737ff367cc7a0a4f5bd9bfe50e71f65059337d Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Thu, 1 Aug 2019 20:11:12 -0700 Subject: [PATCH 10/20] GB Printer: Reset printer buffer index after printing --- CHANGES | 1 + src/gb/sio/printer.c | 1 + 2 files changed, 2 insertions(+) diff --git a/CHANGES b/CHANGES index b0e021ceb..fecb64d6e 100644 --- a/CHANGES +++ b/CHANGES @@ -35,6 +35,7 @@ Emulation fixes: - GBA Memory: Fix STM/LDM to invalid VRAM - GB: Fix savedata initialization (fixes mgba.io/i/1473, mgba.io/i/1478) - GB Memory: Better emulate 0xFEA0 region on DMG, MGB and AGB + - GB Printer: Reset printer buffer index after printing Other fixes: - Qt: Fix some Qt display driver race conditions - Core: Improved lockstep driver reliability (Le Hoang Quyen) diff --git a/src/gb/sio/printer.c b/src/gb/sio/printer.c index dd2f4ecc9..b4f57b6a9 100644 --- a/src/gb/sio/printer.c +++ b/src/gb/sio/printer.c @@ -222,6 +222,7 @@ static uint8_t GBPrinterWriteSC(struct GBSIODriver* driver, uint8_t value) { printer->print(printer, printer->currentIndex * 4 / GB_VIDEO_HORIZONTAL_PIXELS, printer->buffer); } printer->printWait = -1; + printer->currentIndex = 0; } else if (printer->printWait > 0) { --printer->printWait; } From aba3ef017cbed199f901b885a8cacbd7f3c776b9 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Fri, 2 Aug 2019 18:33:16 -0700 Subject: [PATCH 11/20] GBA Cheats: Fix value incrementing in CB slide codes (fixes #1501) --- CHANGES | 1 + src/gba/cheats/codebreaker.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/CHANGES b/CHANGES index fecb64d6e..d4ab00f62 100644 --- a/CHANGES +++ b/CHANGES @@ -50,6 +50,7 @@ Other fixes: - Libretro: Fix crash changing allowing opposing directions (hhromic) - Qt: Fix race conditions initializing GDB stub - GBA: Set up GPIO mapping on null and ELF ROM regions (fixes mgba.io/i/1481) + - GBA Cheats: Fix value incrementing in CB slide codes (fixes mgba.io/i/1501) Misc: - GBA Savedata: EEPROM performance fixes - GBA Savedata: Automatically map 1Mbit Flash files as 1Mbit Flash diff --git a/src/gba/cheats/codebreaker.c b/src/gba/cheats/codebreaker.c index bca859b68..0ba5c80ea 100644 --- a/src/gba/cheats/codebreaker.c +++ b/src/gba/cheats/codebreaker.c @@ -201,7 +201,7 @@ bool GBACheatAddCodeBreaker(struct GBACheatSet* cheats, uint32_t op1, uint16_t o struct mCheat* incompleteCheat = mCheatListGetPointer(&cheats->d.list, cheats->incompleteCheat); incompleteCheat->repeat = op1 & 0xFFFF; incompleteCheat->addressOffset = op2; - incompleteCheat->operandOffset = 0; + incompleteCheat->operandOffset = op1 >> 16; cheats->incompleteCheat = COMPLETE; return true; } From ea573db6c584018432cecd1fbae875369afcf624 Mon Sep 17 00:00:00 2001 From: Roger Date: Tue, 13 Aug 2019 21:24:54 -0400 Subject: [PATCH 12/20] Create FUNDING.yml --- .github/FUNDING.yml | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 .github/FUNDING.yml diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 000000000..21d60d0ac --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1,2 @@ +patreon: mgba +custom: https://mgba.io/donate.html From e8fe5684f7c751b0963a55a9382eb9710da838fb Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sun, 25 Aug 2019 19:08:46 -0700 Subject: [PATCH 13/20] Qt: Add export button for tile view (closes #1507) --- CHANGES | 1 + src/platform/qt/TilePainter.h | 2 + src/platform/qt/TileView.cpp | 11 +++ src/platform/qt/TileView.h | 1 + src/platform/qt/TileView.ui | 169 ++++++++++++++++++---------------- 5 files changed, 103 insertions(+), 81 deletions(-) diff --git a/CHANGES b/CHANGES index d4ab00f62..e4c9342cc 100644 --- a/CHANGES +++ b/CHANGES @@ -18,6 +18,7 @@ Features: - Cheats: Add support for loading Libretro-style cht files - GBA Cheats: Add support for loading EZ Flash-style cht files - Support for unlicensed Wisdom Tree Game Boy mapper + - Qt: Add export button for tile view (closes mgba.io/i/1507) Emulation fixes: - GBA: All IRQs have 7 cycle delay (fixes mgba.io/i/539, mgba.io/i/1208) - GBA: Reset now reloads multiboot ROMs diff --git a/src/platform/qt/TilePainter.h b/src/platform/qt/TilePainter.h index 6adc45419..f4a6bdc96 100644 --- a/src/platform/qt/TilePainter.h +++ b/src/platform/qt/TilePainter.h @@ -19,6 +19,8 @@ Q_OBJECT public: TilePainter(QWidget* parent = nullptr); + QPixmap backing() const { return m_backing; } + public slots: void setTile(int index, const color_t*); void setTileCount(int tiles); diff --git a/src/platform/qt/TileView.cpp b/src/platform/qt/TileView.cpp index 01673c9df..972d5f419 100644 --- a/src/platform/qt/TileView.cpp +++ b/src/platform/qt/TileView.cpp @@ -86,6 +86,8 @@ TileView::TileView(std::shared_ptr controller, QWidget* parent) } updateTiles(true); }); + + connect(m_ui.exportButton, &QAbstractButton::clicked, this, &TileView::exportTiles); } #ifdef M_CORE_GBA @@ -156,3 +158,12 @@ void TileView::updatePalette(int palette) { m_ui.tile->setPalette(palette); updateTiles(true); } + +void TileView::exportTiles() { + QString filename = GBAApp::app()->getSaveFileName(this, tr("Export tiles"), + tr("Portable Network Graphics (*.png)")); + CoreController::Interrupter interrupter(m_controller); + updateTiles(false); + QPixmap pixmap(m_ui.tiles->backing()); + pixmap.save(filename, "PNG"); +} diff --git a/src/platform/qt/TileView.h b/src/platform/qt/TileView.h index cedb11d6c..bf89f5645 100644 --- a/src/platform/qt/TileView.h +++ b/src/platform/qt/TileView.h @@ -23,6 +23,7 @@ public: public slots: void updatePalette(int); + void exportTiles(); private: #ifdef M_CORE_GBA diff --git a/src/platform/qt/TileView.ui b/src/platform/qt/TileView.ui index 4f027a493..521ad27b0 100644 --- a/src/platform/qt/TileView.ui +++ b/src/platform/qt/TileView.ui @@ -14,87 +14,6 @@ Tiles - - - - - 0 - 0 - - - - true - - - Qt::AlignLeading|Qt::AlignLeft|Qt::AlignTop - - - - - 0 - 0 - 405 - 768 - - - - - 0 - 0 - - - - - 0 - - - 0 - - - 0 - - - 0 - - - 0 - - - - - - 0 - 0 - - - - - 256 - 768 - - - - - - - - - - - - Qt::Vertical - - - - 0 - 0 - - - - - - - @@ -172,6 +91,94 @@ + + + + Qt::Vertical + + + + 0 + 0 + + + + + + + + + + + Export + + + + + + + + 0 + 0 + + + + true + + + Qt::AlignLeading|Qt::AlignLeft|Qt::AlignTop + + + + + 0 + 0 + 405 + 768 + + + + + 0 + 0 + + + + + 0 + + + 0 + + + 0 + + + 0 + + + 0 + + + + + + 0 + 0 + + + + + 256 + 768 + + + + + + + + From 4cf401c3910f8a9cce6de621f555d29f5b20cb57 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sun, 25 Aug 2019 19:22:03 -0700 Subject: [PATCH 14/20] Qt: Only show emulator restart warning once per settings saving --- CHANGES | 1 + src/platform/qt/Window.cpp | 6 ++++++ src/platform/qt/Window.h | 2 ++ 3 files changed, 9 insertions(+) diff --git a/CHANGES b/CHANGES index e4c9342cc..d29c03f5f 100644 --- a/CHANGES +++ b/CHANGES @@ -52,6 +52,7 @@ Other fixes: - Qt: Fix race conditions initializing GDB stub - GBA: Set up GPIO mapping on null and ELF ROM regions (fixes mgba.io/i/1481) - GBA Cheats: Fix value incrementing in CB slide codes (fixes mgba.io/i/1501) + - Qt: Only show emulator restart warning once per settings saving Misc: - GBA Savedata: EEPROM performance fixes - GBA Savedata: Automatically map 1Mbit Flash files as 1Mbit Flash diff --git a/src/platform/qt/Window.cpp b/src/platform/qt/Window.cpp index b1eea01d5..da1e79c30 100644 --- a/src/platform/qt/Window.cpp +++ b/src/platform/qt/Window.cpp @@ -152,6 +152,8 @@ Window::Window(CoreManager* manager, ConfigController* config, int playerId, QWi m_log.load(m_config); m_fpsTimer.setInterval(FPS_TIMER_INTERVAL); m_focusCheck.setInterval(200); + m_mustRestart.setInterval(MUST_RESTART_TIMEOUT); + m_mustRestart.setSingleShot(true); m_shortcutController->setConfigController(m_config); m_shortcutController->setActionMapper(&m_actions); @@ -970,6 +972,10 @@ void Window::tryMakePortable() { } void Window::mustRestart() { + if (m_mustRestart.isActive()) { + return; + } + m_mustRestart.start(); QMessageBox* dialog = new QMessageBox(QMessageBox::Warning, tr("Restart needed"), tr("Some changes will not take effect until the emulator is restarted."), QMessageBox::Ok, this, Qt::Sheet); diff --git a/src/platform/qt/Window.h b/src/platform/qt/Window.h index b49185740..97fb744f1 100644 --- a/src/platform/qt/Window.h +++ b/src/platform/qt/Window.h @@ -145,6 +145,7 @@ private slots: private: static const int FPS_TIMER_INTERVAL = 2000; + static const int MUST_RESTART_TIMEOUT = 10000; void setupMenu(QMenuBar*); void openStateWindow(LoadSave); @@ -199,6 +200,7 @@ private: QList m_frameList; QElapsedTimer m_frameTimer; QTimer m_fpsTimer; + QTimer m_mustRestart; QList m_mruFiles; ShortcutController* m_shortcutController; #if defined(BUILD_GL) || defined(BUILD_GLES2) From 3976f8f2739019237269b03e5fdc3c6ef9ae0f63 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sun, 25 Aug 2019 19:29:18 -0700 Subject: [PATCH 15/20] Qt: Add recent game list clearing (closes #1380) --- CHANGES | 1 + src/platform/qt/Window.cpp | 8 ++++++++ src/platform/qt/Window.h | 1 + 3 files changed, 10 insertions(+) diff --git a/CHANGES b/CHANGES index d29c03f5f..b020c6aed 100644 --- a/CHANGES +++ b/CHANGES @@ -19,6 +19,7 @@ Features: - GBA Cheats: Add support for loading EZ Flash-style cht files - Support for unlicensed Wisdom Tree Game Boy mapper - Qt: Add export button for tile view (closes mgba.io/i/1507) + - Qt: Add recent game list clearing (closes mgba.io/i/1380) Emulation fixes: - GBA: All IRQs have 7 cycle delay (fixes mgba.io/i/539, mgba.io/i/1208) - GBA: Reset now reloads multiboot ROMs diff --git a/src/platform/qt/Window.cpp b/src/platform/qt/Window.cpp index da1e79c30..4e4007a12 100644 --- a/src/platform/qt/Window.cpp +++ b/src/platform/qt/Window.cpp @@ -1702,6 +1702,11 @@ void Window::appendMRU(const QString& fname) { updateMRU(); } +void Window::clearMRU() { + m_mruFiles.clear(); + updateMRU(); +} + void Window::updateMRU() { m_actions.clearMenu("mru"); int i = 0; @@ -1714,6 +1719,9 @@ void Window::updateMRU() { } m_config->setMRU(m_mruFiles); m_config->write(); + m_actions.addSeparator("mru"); + m_actions.addAction(tr("Clear"), "resetMru", this, &Window::clearMRU, "mru"); + m_actions.rebuildMenu(menuBar(), this, *m_shortcutController); } diff --git a/src/platform/qt/Window.h b/src/platform/qt/Window.h index 97fb744f1..251550c6d 100644 --- a/src/platform/qt/Window.h +++ b/src/platform/qt/Window.h @@ -154,6 +154,7 @@ private: void detachWidget(QWidget* widget); void appendMRU(const QString& fname); + void clearMRU(); void updateMRU(); void openView(QWidget* widget); From c8872a83ab987e663aa2f64f960460172a21f41b Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sun, 25 Aug 2019 19:43:46 -0700 Subject: [PATCH 16/20] Qt: Improve cheat view UX --- CHANGES | 1 + src/platform/qt/CheatsView.ui | 48 +++++++++++++++++------------------ 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/CHANGES b/CHANGES index b020c6aed..adba1858b 100644 --- a/CHANGES +++ b/CHANGES @@ -54,6 +54,7 @@ Other fixes: - GBA: Set up GPIO mapping on null and ELF ROM regions (fixes mgba.io/i/1481) - GBA Cheats: Fix value incrementing in CB slide codes (fixes mgba.io/i/1501) - Qt: Only show emulator restart warning once per settings saving + - Qt: Improve cheat view UX Misc: - GBA Savedata: EEPROM performance fixes - GBA Savedata: Automatically map 1Mbit Flash files as 1Mbit Flash diff --git a/src/platform/qt/CheatsView.ui b/src/platform/qt/CheatsView.ui index 93c76c33c..e712f281c 100644 --- a/src/platform/qt/CheatsView.ui +++ b/src/platform/qt/CheatsView.ui @@ -6,14 +6,14 @@ 0 0 - 422 - 389 + 629 + 428 Cheats - + @@ -42,27 +42,6 @@ - - - - - 0 - 0 - - - - - 180 - 16777215 - - - - - Courier New - - - - @@ -96,6 +75,27 @@ + + + + + 1 + 0 + + + + + Courier New + + + + QPlainTextEdit::NoWrap + + + Enter codes here... + + + From e7e28459d099f6ad8d326a9438d4227928fb067f Mon Sep 17 00:00:00 2001 From: Lothar Serra Mari Date: Wed, 28 Aug 2019 18:00:56 +0200 Subject: [PATCH 17/20] Qt: Update German GUI translation --- src/platform/qt/ts/mgba-de.ts | 516 +++++++++++++++++++--------------- 1 file changed, 283 insertions(+), 233 deletions(-) diff --git a/src/platform/qt/ts/mgba-de.ts b/src/platform/qt/ts/mgba-de.ts index fcbc84ca3..4f96ef93f 100644 --- a/src/platform/qt/ts/mgba-de.ts +++ b/src/platform/qt/ts/mgba-de.ts @@ -226,15 +226,20 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd.Laden - + Add New Set Neues Set hinzufügen - + Add Hinzufügen + + + Enter codes here... + Codes hier eingeben... + DebuggerConsole @@ -1337,22 +1342,22 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd. QGBA::CoreController - + Failed to open save file: %1 Fehler beim Öffnen der Speicherdatei: %1 - + Failed to open game file: %1 Fehler beim Öffnen der Spieldatei: %1 - + Failed to open snapshot file for reading: %1 Konnte Snapshot-Datei %1 nicht zum Lesen öffnen - + Failed to open snapshot file for writing: %1 Konnte Snapshot-Datei %1 nicht zum Schreiben öffnen @@ -3343,6 +3348,11 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd.Select BIOS BIOS auswählen + + + (%1×%2) + (%1×%2) + QGBA::ShaderSelector @@ -3395,6 +3405,19 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd.Gamepad + + QGBA::TileView + + + Export tiles + Tiles exportieren + + + + Portable Network Graphics (*.png) + Portable Network Graphics (*.png) + + QGBA::VideoView @@ -3416,103 +3439,103 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd. QGBA::Window - + Game Boy Advance ROMs (%1) Game Boy Advance-ROMs (%1) - + Game Boy ROMs (%1) Game Boy-ROMs (%1) - + All ROMs (%1) Alle ROMs (%1) - + %1 Video Logs (*.mvl) %1 Video-Logs (*.mvl) - + Archives (%1) Archive (%1) - - - + + + Select ROM ROM auswählen - + Game Boy Advance save files (%1) Game Boy Advance-Speicherdateien (%1) - - - + + + Select save Speicherdatei wählen - + mGBA savestate files (%1) mGBA Savestate-Dateien (%1) - - + + Select savestate Savestate auswählen - + Select patch Patch wählen - + Patches (*.ips *.ups *.bps) Patches (*.ips *.ups *.bps) - + Select image Bild auswählen - + Image file (*.png *.gif *.jpg *.jpeg);;All files (*) Bild-Datei (*.png *.gif *.jpg *.jpeg);;Alle Dateien (*) - - + + GameShark saves (*.sps *.xps) GameShark-Speicherdaten (*.sps *.xps) - + Select video log Video-Log auswählen - + Video logs (*.mvl) Video-Logs (*.mvl) - + Crash Absturz - + The game has crashed with the following error: %1 @@ -3521,583 +3544,588 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd. - + Couldn't Load Konnte nicht geladen werden - + Could not load game. Are you sure it's in the correct format? Konnte das Spiel nicht laden. Sind Sie sicher, dass es im korrekten Format vorliegt? - + Unimplemented BIOS call Nicht implementierter BIOS-Aufruf - + This game uses a BIOS call that is not implemented. Please use the official BIOS for best experience. Dieses Spiel verwendet einen BIOS-Aufruf, der nicht implementiert ist. Bitte verwenden Sie für die beste Spielerfahrung das offizielle BIOS. - + Really make portable? Portablen Modus wirklich aktivieren? - + This will make the emulator load its configuration from the same directory as the executable. Do you want to continue? Diese Einstellung wird den Emulator so konfigurieren, dass er seine Konfiguration aus dem gleichen Verzeichnis wie die Programmdatei lädt. Möchten Sie fortfahren? - + Restart needed Neustart benötigt - + Some changes will not take effect until the emulator is restarted. Einige Änderungen werden erst übernommen, wenn der Emulator neu gestartet wurde. - + - Player %1 of %2 - Spieler %1 von %2 - + %1 - %2 %1 - %2 - + %1 - %2 - %3 %1 - %2 - %3 - + %1 - %2 (%3 fps) - %4 %1 - %2 (%3 Bilder/Sekunde) - %4 - + &File &Datei - + Load &ROM... &ROM laden... - + Load ROM in archive... ROM aus Archiv laden... - + Load alternate save... Alternative Speicherdatei laden... - + Load temporary save... Temporäre Speicherdatei laden... - + Load &patch... &Patch laden... - + Boot BIOS BIOS booten - + Replace ROM... ROM ersetzen... - + ROM &info... ROM-&Informationen... - + Recent Zuletzt verwendet - + Make portable Portablen Modus aktivieren - + &Load state Savestate (aktueller Zustand) &laden - + Load state file... Ssavestate-Datei laden... - + &Save state Savestate (aktueller Zustand) &speichern - + Save state file... Savestate-Datei speichern... - + Quick load Schnell laden - + Quick save Schnell speichern - + Load recent Lade zuletzt gespeicherten Savestate - + Save recent Speichere aktuellen Zustand - + Undo load state Laden des Savestate rückgängig machen - + Undo save state Speichern des Savestate rückgängig machen - - + + State &%1 Savestate &%1 - + Load camera image... Lade Kamerabild... - + Import GameShark Save Importiere GameShark-Speicherstand - + Export GameShark Save Exportiere GameShark-Speicherstand - + New multiplayer window Neues Multiplayer-Fenster - + E&xit &Beenden - + &Emulation &Emulation - + &Reset Zu&rücksetzen - + Sh&utdown Schli&eßen - + Yank game pak Spielmodul herausziehen - + &Pause &Pause - + &Next frame &Nächstes Bild - + Fast forward (held) Schneller Vorlauf (gehalten) - + &Fast forward Schneller &Vorlauf - + Fast forward speed Vorlauf-Geschwindigkeit - + Unbounded Unbegrenzt - + %0x %0x - + Rewind (held) Zurückspulen (gehalten) - + Re&wind Zur&ückspulen - + Step backwards Schrittweiser Rücklauf - + Sync to &video Mit &Video synchronisieren - + Sync to &audio Mit &Audio synchronisieren - + Solar sensor Sonnen-Sensor - + Increase solar level Sonnen-Level erhöhen - + Decrease solar level Sonnen-Level verringern - + Brightest solar level Hellster Sonnen-Level - + Darkest solar level Dunkelster Sonnen-Level - + Brightness %1 Helligkeit %1 - + BattleChip Gate... BattleChip Gate... - + Audio/&Video Audio/&Video - + Frame size Bildgröße - + Toggle fullscreen Vollbildmodus umschalten - + Lock aspect ratio Seitenverhältnis korrigieren - + Force integer scaling Pixelgenaue Skalierung (Integer scaling) - + Interframe blending Interframe-Überblendung - + Frame&skip Frame&skip - + Mute Stummschalten - + FPS target Bildwiederholrate - + Take &screenshot &Screenshot erstellen - + F12 F12 - + Record GIF... GIF aufzeichen... - + + Clear + Leeren + + + Game Boy Printer... Game Boy Printer... - + Video layers Video-Ebenen - + Audio channels Audio-Kanäle - + Adjust layer placement... Lage der Bildebenen anpassen... - + &Tools &Werkzeuge - + View &logs... &Logs ansehen... - + Game &overrides... Spiel-&Überschreibungen... - + &Cheats... &Cheats... - + Open debugger console... Debugger-Konsole öffnen... - + Start &GDB server... &GDB-Server starten... - + Settings... Einstellungen... - + Select folder Ordner auswählen - + Add folder to library... Ordner zur Bibliothek hinzufügen... - + About... Über... - + %1× %1x - + Bilinear filtering Bilineare Filterung - + Native (59.7275) Nativ (59.7275) - + Record A/V... Audio/Video aufzeichnen... - + Game Pak sensors... Spielmodul-Sensoren... - + View &palette... &Palette betrachten... - + View &sprites... &Sprites betrachten... - + View &tiles... &Tiles betrachten... - + View &map... &Map betrachten... - + &Frame inspector... &Bildbetrachter... - + View memory... Speicher betrachten... - + Search memory... Speicher durchsuchen... - + View &I/O registers... &I/O-Register betrachten... - + Record debug video log... Video-Protokoll aufzeichnen... - + Stop debug video log Aufzeichnen des Video-Protokolls beenden - + Exit fullscreen Vollbildmodus beenden - + GameShark Button (held) GameShark-Taste (gehalten) - + Autofire Autofeuer - + Autofire A Autofeuer A - + Autofire B Autofeuer B - + Autofire L Autofeuer L - + Autofire R Autofeuer R - + Autofire Start Autofeuer Start - + Autofire Select Autofeuer Select - + Autofire Up Autofeuer nach oben - + Autofire Right Autofeuer rechts - + Autofire Down Autofeuer nach unten - + Autofire Left Autofeuer links @@ -4410,7 +4438,7 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd. - + frames Bild(er) @@ -4511,137 +4539,152 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd.Discord-Integration aktivieren - + + Pause when minimized + Pause, wenn minimiert + + + + Fast forward (held) speed: + Vorlauf-Geschwindigkeit (halten): + + + Video renderer: Video-Renderer: - + Software Software - + OpenGL OpenGL - + OpenGL enhancements OpenGL-Verbesserungen - + High-resolution scale: Hochauflösende Skalierung: - + + {size} + {size} + + + XQ GBA audio (experimental) XQ GBA-Audio (experimentell) - + Cheats Cheats - + Log to file In Datei protokollieren - + Log to console Auf die Konsole protokollieren - + Select Log File Protokoll-Datei auswählen - + Camera: Kamera: - - - + + + Autodetect Automatisch erkennen - - - + + + Game Boy (DMG) Game Boy (DMG) - - - + + + Super Game Boy (SGB) Super Game Boy (SGB) - - - + + + Game Boy Color (CGB) Game Boy Color (CGB) - - - + + + Game Boy Advance (AGB) Game Boy Advance (AGB) - + Default BG colors: Standard-Hintergrundfarben: - + Default sprite colors 1: Standard-Sprite-Farben 1: - + Default sprite colors 2: Standard-Sprite-Farben 2: - + Use GBC colors in GB games Verwende GBC-Farben in GB-Spielen - + Super Game Boy borders Super Game Boy-Rahmen - + Game Boy model: Game Boy-Modell: - + Super Game Boy model: Super Game Boy-Modell: - + Game Boy Color model: Game Boy Color-Modell: - + Camera driver: Kamera-Treiber: @@ -4661,48 +4704,50 @@ Game Boy Advance ist ein eingetragenes Warenzeichen von Nintendo Co., Ltd.Cache leeren - + Fast forward speed: Vorlauf-Geschwindigkeit: - + Preload entire ROM into memory ROM-Datei vollständig in Arbeitsspeicher vorladen - - - - - - - - - + + + + + + + + + Browse Durchsuchen - + Use BIOS file if found BIOS-Datei verwenden, wenn vorhanden - + Skip BIOS intro BIOS-Intro überspringen - - + + + × × - + + Unbounded unbegrenzt @@ -4722,17 +4767,17 @@ wenn vorhanden Pause, wenn inaktiv - + Run all Alle ausführen - + Remove known Bekannte entfernen - + Detect and remove Erkennen und entfernen @@ -4742,25 +4787,25 @@ wenn vorhanden Gegensätzliche Eingaberichtungen erlauben - - + + Screenshot Screenshot - - + + Save data Speicherdaten - - + + Cheat codes Cheat-Codes - + Enable rewind Rücklauf aktivieren @@ -4770,76 +4815,76 @@ wenn vorhanden Bilineare Filterung - + Rewind history: Rücklauf-Verlauf: - + Idle loops: Leerlaufprozesse: - + Savestate extra data: Zusätzliche Savestate-Daten: - + Load extra data: Lade zusätzliche Daten: - + Autofire interval: Autofeuer-Intervall: - + GB BIOS file: Datei mit GB-BIOS: - + GBA BIOS file: Datei mit GBA-BIOS: - + GBC BIOS file: Datei mit GBC-BIOS: - + SGB BIOS file: Datei mit SGB-BIOS: - + Save games Spielstände - - - - - + + + + + Same directory as the ROM Verzeichnis der ROM-Datei - + Save states Savestates - + Screenshots Screenshots - + Patches Patches @@ -4913,30 +4958,35 @@ wenn vorhanden Tiles - + 256 colors 256 Farben - + × × - + Magnification Vergrößerung - + Tiles per row Tiles pro Zeile - + Fit to window An Fenster anpassen + + + Export + Exportieren + VideoView From 11fcc89f793db3fe74b1ef950d6c4af1e69d09e1 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Wed, 28 Aug 2019 20:49:54 -0700 Subject: [PATCH 18/20] Qt: Set default value for scale size (fixes #1513) --- src/platform/qt/SettingsView.ui | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/platform/qt/SettingsView.ui b/src/platform/qt/SettingsView.ui index bc95d5416..e4050da5c 100644 --- a/src/platform/qt/SettingsView.ui +++ b/src/platform/qt/SettingsView.ui @@ -983,7 +983,7 @@ false - {size} + (240×160) From 178348d44588f6454908e360c874119ee73d79e1 Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Wed, 28 Aug 2019 20:55:11 -0700 Subject: [PATCH 19/20] Qt: Scale pixel color values to full range (fixes #1511) --- CHANGES | 1 + src/platform/qt/AssetTile.cpp | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGES b/CHANGES index adba1858b..505d35896 100644 --- a/CHANGES +++ b/CHANGES @@ -81,6 +81,7 @@ Misc: - Qt: Add option to pause on minimizing window (closes mgba.io/i/1379) - Switch: Support file associations - Qt: Show error message if file failed to load + - Qt: Scale pixel color values to full range (fixes mgba.io/i/1511) 0.7.2: (2019-05-25) Emulation fixes: diff --git a/src/platform/qt/AssetTile.cpp b/src/platform/qt/AssetTile.cpp index ea3bcb28c..0f87f7654 100644 --- a/src/platform/qt/AssetTile.cpp +++ b/src/platform/qt/AssetTile.cpp @@ -134,9 +134,9 @@ void AssetTile::selectColor(int index) { m_ui.color->setColor(0, color); m_ui.color->update(); - uint32_t r = color & 0xF8; - uint32_t g = (color >> 8) & 0xF8; - uint32_t b = (color >> 16) & 0xF8; + uint32_t r = M_R8(color); + uint32_t g = M_G8(color); + uint32_t b = M_B8(color); m_ui.r->setText(tr("0x%0 (%1)").arg(r, 2, 16, QChar('0')).arg(r, 2, 10, QChar('0'))); m_ui.g->setText(tr("0x%0 (%1)").arg(g, 2, 16, QChar('0')).arg(g, 2, 10, QChar('0'))); m_ui.b->setText(tr("0x%0 (%1)").arg(b, 2, 16, QChar('0')).arg(b, 2, 10, QChar('0'))); From 74e09675ce2792d6a4fc79c9f4fe1f893513efac Mon Sep 17 00:00:00 2001 From: Vicki Pfau Date: Sun, 1 Sep 2019 21:30:31 -0700 Subject: [PATCH 20/20] GB: Fix SGB controller selection initialization (fixes #1104) --- CHANGES | 1 + src/gb/gb.c | 2 +- src/gb/io.c | 4 ++-- src/gb/video.c | 2 +- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/CHANGES b/CHANGES index 505d35896..f25fd61b6 100644 --- a/CHANGES +++ b/CHANGES @@ -55,6 +55,7 @@ Other fixes: - GBA Cheats: Fix value incrementing in CB slide codes (fixes mgba.io/i/1501) - Qt: Only show emulator restart warning once per settings saving - Qt: Improve cheat view UX + - GB: Fix SGB controller selection initialization (fixes mgba.io/i/1104) Misc: - GBA Savedata: EEPROM performance fixes - GBA Savedata: Automatically map 1Mbit Flash files as 1Mbit Flash diff --git a/src/gb/gb.c b/src/gb/gb.c index 06ceddc64..4cff00c9a 100644 --- a/src/gb/gb.c +++ b/src/gb/gb.c @@ -435,7 +435,7 @@ void GBReset(struct LR35902Core* cpu) { gb->sgbBit = -1; gb->sgbControllers = 0; - gb->sgbCurrentController = 0; + gb->sgbCurrentController = 3; gb->currentSgbBits = 0; memset(gb->sgbPacket, 0, sizeof(gb->sgbPacket)); diff --git a/src/gb/io.c b/src/gb/io.c index 2c4b9b4b3..f75e5b83b 100644 --- a/src/gb/io.c +++ b/src/gb/io.c @@ -535,13 +535,13 @@ void GBIOWrite(struct GB* gb, unsigned address, uint8_t value) { static uint8_t _readKeys(struct GB* gb) { uint8_t keys = *gb->keySource; - if (gb->sgbCurrentController != 0) { + if (gb->sgbCurrentController & gb->sgbControllers) { keys = 0; } uint8_t joyp = gb->memory.io[REG_JOYP]; switch (joyp & 0x30) { case 0x30: - keys = gb->sgbCurrentController; + keys = gb->sgbCurrentController & gb->sgbControllers; break; case 0x20: keys >>= 4; diff --git a/src/gb/video.c b/src/gb/video.c index 020889ca9..329174e02 100644 --- a/src/gb/video.c +++ b/src/gb/video.c @@ -702,7 +702,7 @@ void GBVideoWriteSGBPacket(struct GBVideo* video, uint8_t* data) { break; case SGB_MLT_REQ: video->p->sgbControllers = video->sgbPacketBuffer[1] & 0x3; - video->p->sgbCurrentController = 0; + video->p->sgbCurrentController &= video->p->sgbControllers; return; case SGB_MASK_EN: video->renderer->sgbRenderMode = video->sgbPacketBuffer[1] & 0x3;