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Fix CPSR C being written

This commit is contained in:
Jeffrey Pfau 2013-04-28 00:06:13 -07:00
parent 682684cb6d
commit 19f9b72c33
2 changed files with 8 additions and 8 deletions
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2
src/arm/isa-arm.c
View File

@ -234,7 +234,7 @@ void ARMStep(struct ARMCore* cpu) {
} else { \ } else { \
cpu->cpsr.n = ARM_SIGN(D); \ cpu->cpsr.n = ARM_SIGN(D); \
cpu->cpsr.z = !(D); \ cpu->cpsr.z = !(D); \
cpu->cpsr.c = cpu->shifterCarryOut; \ cpu->cpsr.c = !!cpu->shifterCarryOut; \
} }
#define ARM_NEUTRAL_HI_S(DLO, DHI) \ #define ARM_NEUTRAL_HI_S(DLO, DHI) \

14
src/arm/isa-thumb.c
View File

@ -112,7 +112,7 @@ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1,
if (!immediate) { if (!immediate) {
cpu->gprs[rd] = cpu->gprs[rm]; cpu->gprs[rd] = cpu->gprs[rm];
} else { } else {
cpu->cpsr.c = cpu->gprs[rm] & (1 << (32 - immediate)); cpu->cpsr.c = (cpu->gprs[rm] >> (32 - immediate)) & 1;
cpu->gprs[rd] = cpu->gprs[rm] << immediate; cpu->gprs[rd] = cpu->gprs[rm] << immediate;
} }
THUMB_NEUTRAL_S( , , cpu->gprs[rd]);) THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
@ -122,7 +122,7 @@ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1,
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]); cpu->cpsr.c = ARM_SIGN(cpu->gprs[rm]);
cpu->gprs[rd] = 0; cpu->gprs[rd] = 0;
} else { } else {
cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate; cpu->gprs[rd] = ((uint32_t) cpu->gprs[rm]) >> immediate;
} }
THUMB_NEUTRAL_S( , , cpu->gprs[rd]);) THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
@ -136,7 +136,7 @@ DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1,
cpu->gprs[rd] = 0; cpu->gprs[rd] = 0;
} }
} else { } else {
cpu->cpsr.c = cpu->gprs[rm] & (1 << (immediate - 1)); cpu->cpsr.c = (cpu->gprs[rm] >> (immediate - 1)) & 1;
cpu->gprs[rd] = cpu->gprs[rm] >> immediate; cpu->gprs[rd] = cpu->gprs[rm] >> immediate;
} }
THUMB_NEUTRAL_S( , , cpu->gprs[rd]);) THUMB_NEUTRAL_S( , , cpu->gprs[rd]);)
@ -200,7 +200,7 @@ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2,
int rs = cpu->gprs[rn] & 0xFF; int rs = cpu->gprs[rn] & 0xFF;
if (rs) { if (rs) {
if (rs < 32) { if (rs < 32) {
cpu->cpsr.c = cpu->gprs[rd] & (1 << (32 - rs)); cpu->cpsr.c = (cpu->gprs[rd] >> (32 - rs)) & 1;
cpu->gprs[rd] <<= rs; cpu->gprs[rd] <<= rs;
} else { } else {
if (rs > 32) { if (rs > 32) {
@ -217,7 +217,7 @@ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2,
int rs = cpu->gprs[rn] & 0xFF; int rs = cpu->gprs[rn] & 0xFF;
if (rs) { if (rs) {
if (rs < 32) { if (rs < 32) {
cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs; cpu->gprs[rd] = (uint32_t) cpu->gprs[rd] >> rs;
} else { } else {
if (rs > 32) { if (rs > 32) {
@ -234,7 +234,7 @@ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2,
int rs = cpu->gprs[rn] & 0xFF; int rs = cpu->gprs[rn] & 0xFF;
if (rs) { if (rs) {
if (rs < 32) { if (rs < 32) {
cpu->cpsr.c = cpu->gprs[rd] & (1 << (rs - 1)); cpu->cpsr.c = (cpu->gprs[rd] >> (rs - 1)) & 1;
cpu->gprs[rd] >>= rs; cpu->gprs[rd] >>= rs;
} else { } else {
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);
@ -263,7 +263,7 @@ DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR,
if (rs) { if (rs) {
int r4 = rs & 0x1F; int r4 = rs & 0x1F;
if (r4 > 0) { if (r4 > 0) {
cpu->cpsr.c = cpu->gprs[rd] & (1 << (r4 - 1)); cpu->cpsr.c = (cpu->gprs[rd] >> (r4 - 1)) & 1;
cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4); cpu->gprs[rd] = ARM_ROR(cpu->gprs[rd], r4);
} else { } else {
cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]); cpu->cpsr.c = ARM_SIGN(cpu->gprs[rd]);