mirror of https://github.com/mgba-emu/mgba.git
ARM7: Fix MLA/*MULL/*MLAL timing
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@ -11,6 +11,7 @@ Bugfixes:
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- GB Timer: Improve DIV reset behavior
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- GBA Memory: Improve initial skipped BIOS state
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- GBA BIOS: Implement BitUnPack
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- ARM7: Fix MLA/*MULL/*MLAL timing
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Misc:
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- SDL: Remove scancode key input
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- GBA Video: Clean up unused timers
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@ -316,11 +316,10 @@ static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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#define DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, S_BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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int rd = (opcode >> 12) & 0xF; \
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int rdHi = (opcode >> 16) & 0xF; \
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int rd = (opcode >> 16) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rm = opcode & 0xF; \
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if (rdHi == ARM_PC || rd == ARM_PC) { \
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if (rd == ARM_PC) { \
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return; \
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} \
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ARM_WAIT_MUL(cpu->gprs[rs]); \
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@ -328,10 +327,28 @@ static inline void _immediate(struct ARMCore* cpu, uint32_t opcode) {
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S_BODY; \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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#define DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, S_BODY, WAIT) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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int rd = (opcode >> 12) & 0xF; \
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int rdHi = (opcode >> 16) & 0xF; \
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int rs = (opcode >> 8) & 0xF; \
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int rm = opcode & 0xF; \
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if (rdHi == ARM_PC || rd == ARM_PC) { \
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return; \
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} \
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currentCycles += cpu->memory.stall(cpu, WAIT); \
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BODY; \
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S_BODY; \
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currentCycles += cpu->memory.activeNonseqCycles32 - cpu->memory.activeSeqCycles32)
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#define DEFINE_MULTIPLY_INSTRUCTION_ARM(NAME, BODY, S_BODY) \
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DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME, BODY, ) \
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DEFINE_MULTIPLY_INSTRUCTION_EX_ARM(NAME ## S, BODY, S_BODY)
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#define DEFINE_MULTIPLY_INSTRUCTION_2_ARM(NAME, BODY, S_BODY, WAIT) \
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DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME, BODY, , WAIT) \
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DEFINE_MULTIPLY_INSTRUCTION_2_EX_ARM(NAME ## S, BODY, S_BODY, WAIT)
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#define DEFINE_LOAD_STORE_INSTRUCTION_EX_ARM(NAME, ADDRESS, WRITEBACK, BODY) \
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DEFINE_INSTRUCTION_ARM(NAME, \
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uint32_t address; \
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@ -485,36 +502,36 @@ DEFINE_ALU_INSTRUCTION_S_ONLY_ARM(TST, ARM_NEUTRAL_S(cpu->gprs[rn], cpu->shifter
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// Begin multiply definitions
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]))
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rdHi]))
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(MLA, cpu->gprs[rdHi] = cpu->gprs[rm] * cpu->gprs[rs] + cpu->gprs[rd], ARM_NEUTRAL_S(, , cpu->gprs[rdHi]), 2)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(MUL, cpu->gprs[rd] = cpu->gprs[rm] * cpu->gprs[rs], ARM_NEUTRAL_S(cpu->gprs[rm], cpu->gprs[rs], cpu->gprs[rd]))
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DEFINE_MULTIPLY_INSTRUCTION_ARM(SMLAL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMLAL,
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int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
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int32_t dm = cpu->gprs[rd];
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int32_t dn = d;
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cpu->gprs[rd] = dm + dn;
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cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(SMULL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(SMULL,
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int64_t d = ((int64_t) cpu->gprs[rm]) * ((int64_t) cpu->gprs[rs]);
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cpu->gprs[rd] = d;
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cpu->gprs[rdHi] = d >> 32;,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(UMLAL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMLAL,
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uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
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int32_t dm = cpu->gprs[rd];
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int32_t dn = d;
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cpu->gprs[rd] = dm + dn;
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cpu->gprs[rdHi] = cpu->gprs[rdHi] + (d >> 32) + ARM_CARRY_FROM(dm, dn, cpu->gprs[rd]);,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 3)
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DEFINE_MULTIPLY_INSTRUCTION_ARM(UMULL,
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DEFINE_MULTIPLY_INSTRUCTION_2_ARM(UMULL,
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uint64_t d = ARM_UXT_64(cpu->gprs[rm]) * ARM_UXT_64(cpu->gprs[rs]);
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cpu->gprs[rd] = d;
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cpu->gprs[rdHi] = d >> 32;,
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]))
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ARM_NEUTRAL_HI_S(cpu->gprs[rd], cpu->gprs[rdHi]), 2)
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// End multiply definitions
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