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DS DMA: Ignore, not block, ITCM DMAs

This commit is contained in:
Vicki Pfau 2017-03-23 10:51:32 -07:00
parent 2e4597c0e8
commit 12b44599ad
1 changed files with 11 additions and 15 deletions
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26
src/ds/dma.c
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@ -37,11 +37,6 @@ void DSDMAReset(struct DSCommon* dscore) {
dscore->memory.activeDMA = -1;
}
static bool _isValidDMADAD(int dma, uint32_t address) {
UNUSED(dma);
return address >= DS_BASE_RAM;
}
uint32_t DSDMAWriteSAD(struct DSCommon* dscore, int dma, uint32_t address) {
address &= 0x0FFFFFFE;
dscore->memory.dma[dma].source = address;
@ -50,9 +45,7 @@ uint32_t DSDMAWriteSAD(struct DSCommon* dscore, int dma, uint32_t address) {
uint32_t DSDMAWriteDAD(struct DSCommon* dscore, int dma, uint32_t address) {
address &= 0x0FFFFFFE;
if (_isValidDMADAD(dma, address)) {
dscore->memory.dma[dma].dest = address;
}
dscore->memory.dma[dma].dest = address;
return dscore->memory.dma[dma].dest;
}
@ -217,6 +210,7 @@ void DSDMAService(struct DSCommon* dscore, int number, struct GBADMA* info) {
int32_t cycles = 2;
if (info->count == info->nextCount) {
// TODO: This probably uses bus timings instead of TCM timings for inaccessible TCM
if (width == 4) {
cycles += dscore->memory.waitstatesNonseq32[sourceRegion] + dscore->memory.waitstatesNonseq32[destRegion];
} else {
@ -233,13 +227,15 @@ void DSDMAService(struct DSCommon* dscore, int number, struct GBADMA* info) {
}
info->when += cycles;
uint32_t word;
if (width == 4) {
word = cpu->memory.load32(cpu, source, 0);
cpu->memory.store32(cpu, dest, word, 0);
} else {
word = cpu->memory.load16(cpu, source, 0);
cpu->memory.store16(cpu, dest, word, 0);
if (source >= DS_BASE_RAM) {
uint32_t word;
if (width == 4) {
word = cpu->memory.load32(cpu, source, 0);
cpu->memory.store32(cpu, dest, word, 0);
} else {
word = cpu->memory.load16(cpu, source, 0);
cpu->memory.store16(cpu, dest, word, 0);
}
}
int sourceOffset = DMA_OFFSET[GBADMARegisterGetSrcControl(info->reg)] * width;
int destOffset = DMA_OFFSET[GBADMARegisterGetDestControl(info->reg)] * width;