mirror of https://github.com/mgba-emu/mgba.git
GB: Optimize cpuLoad8
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3b24e94018
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05ef05317c
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@ -33,8 +33,40 @@ static void _GBMBC7(struct GBMemory*, uint16_t address, uint8_t value);
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static uint8_t _GBMBC7Read(struct GBMemory*, uint16_t address);
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static void _GBMBC7Write(struct GBMemory*, uint16_t address, uint8_t value);
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static uint8_t GBFastLoad8(struct LR35902Core* cpu, uint16_t address) {
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if (UNLIKELY(address > cpu->memory.activeRegionEnd)) {
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cpu->memory.setActiveRegion(cpu, address);
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return cpu->memory.cpuLoad8(cpu, address);
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}
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return cpu->memory.activeRegion[address & cpu->memory.activeMask];
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}
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static void GBSetActiveRegion(struct LR35902Core* cpu, uint16_t address) {
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// TODO
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struct GB* gb = (struct GB*) cpu->master;
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struct GBMemory* memory = &gb->memory;
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switch (address >> 12) {
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case GB_REGION_CART_BANK0:
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case GB_REGION_CART_BANK0 + 1:
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case GB_REGION_CART_BANK0 + 2:
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case GB_REGION_CART_BANK0 + 3:
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cpu->memory.cpuLoad8 = GBFastLoad8;
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cpu->memory.activeRegion = memory->rom;
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cpu->memory.activeRegionEnd = GB_BASE_CART_BANK1;
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cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
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break;
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case GB_REGION_CART_BANK1:
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case GB_REGION_CART_BANK1 + 1:
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case GB_REGION_CART_BANK1 + 2:
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case GB_REGION_CART_BANK1 + 3:
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cpu->memory.cpuLoad8 = GBFastLoad8;
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cpu->memory.activeRegion = memory->romBank;
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cpu->memory.activeRegionEnd = GB_BASE_VRAM;
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cpu->memory.activeMask = GB_SIZE_CART_BANK0 - 1;
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break;
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default:
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cpu->memory.cpuLoad8 = GBLoad8;
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break;
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}
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}
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static void _GBMemoryDMAService(struct GB* gb);
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@ -235,6 +267,7 @@ void GBStore8(struct LR35902Core* cpu, uint16_t address, int8_t value) {
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case GB_REGION_CART_BANK1 + 2:
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case GB_REGION_CART_BANK1 + 3:
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memory->mbc(memory, address, value);
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cpu->memory.setActiveRegion(cpu, cpu->pc);
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return;
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case GB_REGION_VRAM:
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case GB_REGION_VRAM + 1:
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@ -304,6 +337,7 @@ void GBMemoryDMA(struct GB* gb, uint16_t base) {
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}
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gb->cpu->memory.store8 = GBDMAStore8;
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gb->cpu->memory.load8 = GBDMALoad8;
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gb->cpu->memory.cpuLoad8 = GBDMALoad8;
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gb->memory.dmaNext = gb->cpu->cycles + 8;
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if (gb->memory.dmaNext < gb->cpu->nextEvent) {
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gb->cpu->nextEvent = gb->memory.dmaNext;
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@ -129,7 +129,7 @@ static void _LR35902Step(struct LR35902Core* cpu) {
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cpu->memory.store8(cpu, cpu->index, cpu->bus);
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break;
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case LR35902_CORE_READ_PC:
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cpu->bus = cpu->memory.load8(cpu, cpu->pc);
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cpu->bus = cpu->memory.cpuLoad8(cpu, cpu->pc);
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++cpu->pc;
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break;
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case LR35902_CORE_STALL:
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@ -47,7 +47,6 @@ enum LR35902ExecutionState {
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LR35902_CORE_STALL = 19,
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LR35902_CORE_OP2 = 23
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};
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struct LR35902Memory {
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uint8_t (*cpuLoad8)(struct LR35902Core*, uint16_t address);
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uint8_t (*load8)(struct LR35902Core*, uint16_t address);
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@ -55,6 +54,7 @@ struct LR35902Memory {
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uint8_t* activeRegion;
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uint16_t activeMask;
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uint16_t activeRegionEnd;
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void (*setActiveRegion)(struct LR35902Core*, uint16_t address);
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};
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