2013-04-17 07:46:32 +00:00
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#define nop andeq r0, r0
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.text
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b resetBase
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b undefBase
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b swiBase
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b pabtBase
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b dabtBase
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nop
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b irqBase
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b fiqBase
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resetBase:
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mov pc, #0x8000000
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swiBase:
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cmp sp, #0
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moveq sp, #0x04000000
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subeq sp, #0x20
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2014-07-03 10:51:53 +00:00
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stmfd sp!, {r4-r5, lr}
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ldrb r4, [lr, #-2]
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mov r5, #swiTable
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ldr r4, [r5, r4, lsl #2]
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cmp r4, #0
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mov lr, pc
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bxne r4
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ldmfd sp!, {r4-r5, lr}
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2013-04-17 07:46:32 +00:00
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movs pc, lr
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2014-07-03 10:51:53 +00:00
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swiTable:
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.word SoftReset
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.word RegisterRamReset
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.word Halt
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.word Stop
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.word IntrWait
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.word VBlankIntrWait
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.word Div
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.word DivArm
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.word Sqrt
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.word ArcTan
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.word ArcTan2
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.word CpuSet
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.word CpuFastSet
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# ... The rest of this table isn't needed if the rest aren't implemented
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2013-04-17 07:46:32 +00:00
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irqBase:
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stmfd sp!, {r0-r3, r12, lr}
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mov r0, #0x04000000
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add lr, pc, #0
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ldr pc, [r0, #-4]
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ldmfd sp!, {r0-r3, r12, lr}
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subs pc, lr, #4
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2014-07-03 10:51:53 +00:00
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VBlankIntrWait:
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mov r0, #1
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mov r1, #1
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2013-04-17 07:46:32 +00:00
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IntrWait:
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2014-07-03 10:51:53 +00:00
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stmfd sp!, {lr}
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mrs r5, spsr
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msr cpsr, #0x1F
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2013-10-15 07:50:07 +00:00
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# Pull current interrupts enabled and add the ones we need
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2013-07-18 09:14:22 +00:00
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mov r4, #0x04000000
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2013-10-15 07:50:07 +00:00
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# See if we want to return immediately
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cmp r0, #0
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2013-07-18 09:14:22 +00:00
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mov r0, #0
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2013-10-15 07:50:07 +00:00
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mov r2, #1
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2014-07-03 10:51:53 +00:00
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beq 1f
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2013-10-15 07:50:07 +00:00
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# Halt
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2014-07-03 10:51:53 +00:00
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0:
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2013-07-18 09:14:22 +00:00
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strb r0, [r4, #0x301]
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2014-07-03 10:51:53 +00:00
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1:
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2013-10-15 07:50:07 +00:00
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# Check which interrupts were acknowledged
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2014-07-03 10:51:53 +00:00
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strb r0, [r4, #0x208]
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2013-10-15 07:50:07 +00:00
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ldrh r3, [r4, #-8]
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ands r3, r1
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eorne r3, r1
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strneh r3, [r4, #-8]
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2014-07-03 10:51:53 +00:00
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strb r2, [r4, #0x208]
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beq 0b
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msr cpsr, #0x93
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msr spsr, r5
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ldmfd sp!, {pc}
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CpuSet:
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2014-07-05 00:48:38 +00:00
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msr cpsr, #0x1F
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2014-07-03 10:51:53 +00:00
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mov r3, r2, lsl #12
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mov r3, r3, lsr #12
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tst r2, #0x01000000
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beq 0f
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# Fill
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tst r2, #0x04000000
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beq 1f
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# Word
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ldmia r0!, {r2}
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2:
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stmia r1!, {r2}
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subs r3, #1
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bne 2b
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b 3f
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# Halfword
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1:
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bic r0, #1
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bic r1, #1
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ldrh r2, [r0]
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2:
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strh r2, [r1], #2
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subs r3, #1
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bne 2b
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b 3f
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# Copy
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0:
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tst r2, #0x04000000
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beq 1f
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# Word
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2:
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ldmia r0!, {r2}
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stmia r1!, {r2}
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subs r3, #1
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bne 2b
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b 3f
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# Halfword
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1:
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bic r0, #1
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bic r1, #1
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2:
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ldrh r2, [r0], #2
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strh r2, [r1], #2
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subs r3, #1
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bne 2b
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3:
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msr cpsr, #0x93
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bx lr
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CpuFastSet:
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2014-07-05 00:48:38 +00:00
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msr cpsr, #0x1F
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2014-07-03 10:51:53 +00:00
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stmfd sp!, {r4-r10}
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tst r2, #0x01000000
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2014-07-05 00:48:38 +00:00
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mov r3, r2, lsl #12
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mov r2, r3, lsr #12
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2014-07-03 10:51:53 +00:00
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beq 0f
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# Fill
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ldmia r0!, {r4}
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mov r5, r4
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mov r3, r4
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mov r6, r4
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mov r7, r4
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mov r8, r4
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mov r9, r4
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mov r10, r4
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1:
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stmia r1!, {r3-r10}
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subs r2, #8
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bgt 1b
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b 2f
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# Copy
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0:
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ldmia r0!, {r3-r10}
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stmia r1!, {r3-r10}
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subs r2, #8
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2014-07-05 00:48:38 +00:00
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bgt 0b
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2014-07-03 10:51:53 +00:00
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2:
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ldmfd sp!, {r4-r10}
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msr cpsr, #0x93
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bx lr
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