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mgba/src/isa-thumb.c

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Start filling in THUMB table with insane preprocessor tricks
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#include "isa-thumb.h"
Stub out POP/PUSH
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#include "isa-inlines.h"
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static const ThumbInstruction _thumbTable[0x400];
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void ThumbStep(struct ARMCore* cpu) {
uint32_t address = cpu->gprs[ARM_PC];
cpu->gprs[ARM_PC] = address + WORD_SIZE_THUMB;
address -= WORD_SIZE_THUMB;
uint16_t opcode = ((uint16_t*) cpu->memory->activeRegion)[(address & cpu->memory->activeMask) >> 1];
ThumbInstruction instruction = _thumbTable[opcode >> 6];
instruction(cpu, opcode);
}
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// Instruction definitions
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// Beware pre-processor insanity
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Implement MOV(1)
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#define THUMB_NEUTRAL_S(M, N, D) \
cpu->cpsr.n = ARM_SIGN(D); \
cpu->cpsr.z = !(D);
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#define APPLY(F, ...) F(__VA_ARGS__)
#define COUNT_1(EMITTER, PREFIX, ...) \
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EMITTER(PREFIX ## 0, 0, __VA_ARGS__) \
EMITTER(PREFIX ## 1, 1, __VA_ARGS__)
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#define COUNT_2(EMITTER, PREFIX, ...) \
COUNT_1(EMITTER, PREFIX, __VA_ARGS__) \
Macro-insanity for Thumb
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EMITTER(PREFIX ## 2, 2, __VA_ARGS__) \
EMITTER(PREFIX ## 3, 3, __VA_ARGS__)
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#define COUNT_3(EMITTER, PREFIX, ...) \
COUNT_2(EMITTER, PREFIX, __VA_ARGS__) \
Macro-insanity for Thumb
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EMITTER(PREFIX ## 4, 4, __VA_ARGS__) \
EMITTER(PREFIX ## 5, 5, __VA_ARGS__) \
EMITTER(PREFIX ## 6, 6, __VA_ARGS__) \
EMITTER(PREFIX ## 7, 7, __VA_ARGS__)
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#define COUNT_4(EMITTER, PREFIX, ...) \
COUNT_3(EMITTER, PREFIX, __VA_ARGS__) \
Macro-insanity for Thumb
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EMITTER(PREFIX ## 8, 8, __VA_ARGS__) \
EMITTER(PREFIX ## 9, 9, __VA_ARGS__) \
EMITTER(PREFIX ## A, 10, __VA_ARGS__) \
EMITTER(PREFIX ## B, 11, __VA_ARGS__) \
EMITTER(PREFIX ## C, 12, __VA_ARGS__) \
EMITTER(PREFIX ## D, 13, __VA_ARGS__) \
EMITTER(PREFIX ## E, 14, __VA_ARGS__) \
EMITTER(PREFIX ## F, 15, __VA_ARGS__)
Start filling in THUMB table with insane preprocessor tricks
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#define COUNT_5(EMITTER, PREFIX, ...) \
COUNT_4(EMITTER, PREFIX ## 0, __VA_ARGS__) \
Macro-insanity for Thumb
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EMITTER(PREFIX ## 10, 16, __VA_ARGS__) \
EMITTER(PREFIX ## 11, 17, __VA_ARGS__) \
EMITTER(PREFIX ## 12, 18, __VA_ARGS__) \
EMITTER(PREFIX ## 13, 19, __VA_ARGS__) \
EMITTER(PREFIX ## 14, 20, __VA_ARGS__) \
EMITTER(PREFIX ## 15, 21, __VA_ARGS__) \
EMITTER(PREFIX ## 16, 22, __VA_ARGS__) \
EMITTER(PREFIX ## 17, 23, __VA_ARGS__) \
EMITTER(PREFIX ## 18, 24, __VA_ARGS__) \
EMITTER(PREFIX ## 19, 25, __VA_ARGS__) \
EMITTER(PREFIX ## 1A, 26, __VA_ARGS__) \
EMITTER(PREFIX ## 1B, 27, __VA_ARGS__) \
EMITTER(PREFIX ## 1C, 28, __VA_ARGS__) \
EMITTER(PREFIX ## 1D, 29, __VA_ARGS__) \
EMITTER(PREFIX ## 1E, 30, __VA_ARGS__) \
EMITTER(PREFIX ## 1F, 31, __VA_ARGS__) \
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#define DEFINE_INSTRUCTION_THUMB(NAME, BODY) \
static void _ThumbInstruction ## NAME (struct ARMCore* cpu, uint16_t opcode) { \
BODY; \
}
Stub out more load/stores with immediates
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#define DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
Macro-insanity for Thumb
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DEFINE_INSTRUCTION_THUMB(NAME, \
int immediate = IMMEDIATE; \
BODY;)
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#define DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(NAME, BODY) \
COUNT_5(DEFINE_IMMEDIATE_5_INSTRUCTION_EX_THUMB, NAME ## _, BODY)
Macro-insanity for Thumb
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Put stub definitions in all of Thumb
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSL1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LSR1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(ASR1, ARM_STUB)
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DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDR1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRB1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(LDRH1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STR1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRB1, ARM_STUB)
DEFINE_IMMEDIATE_5_INSTRUCTION_THUMB(STRH1, ARM_STUB)
Macro-insanity for Thumb
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Add data form 3
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#define DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB(NAME, RM, BODY) \
ADD/SUB 1 stubs
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DEFINE_INSTRUCTION_THUMB(NAME, \
Add data form 3
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int rm = RM; \
ADD/SUB 1 stubs
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BODY;)
Add data form 3
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#define DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(NAME, BODY) \
COUNT_3(DEFINE_DATA_FORM_1_INSTRUCTION_EX_THUMB, NAME ## 3_R, BODY)
ADD/SUB 1 stubs
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Put stub definitions in all of Thumb
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DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(ADD, ARM_STUB)
DEFINE_DATA_FORM_1_INSTRUCTION_THUMB(SUB, ARM_STUB)
ADD/SUB 1 stubs
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Add data form 3
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#define DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB(NAME, IMMEDIATE, BODY) \
Macro-insanity for Thumb
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DEFINE_INSTRUCTION_THUMB(NAME, \
Add data form 3
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int immediate = IMMEDIATE; \
Macro-insanity for Thumb
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BODY;)
Add data form 3
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#define DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(NAME, BODY) \
COUNT_3(DEFINE_DATA_FORM_2_INSTRUCTION_EX_THUMB, NAME ## 1_, BODY)
Macro-insanity for Thumb
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Put stub definitions in all of Thumb
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DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(ADD, ARM_STUB)
DEFINE_DATA_FORM_2_INSTRUCTION_THUMB(SUB, ARM_STUB)
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Fix data format 3
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#define DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB(NAME, RD, BODY) \
Add data form 3
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DEFINE_INSTRUCTION_THUMB(NAME, \
int rd = RD; \
Implement MOV(1)
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int immediate = opcode & 0x00FF; \
Add data form 3
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BODY;)
#define DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(NAME, BODY) \
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COUNT_3(DEFINE_DATA_FORM_3_INSTRUCTION_EX_THUMB, NAME ## _R, BODY)
Add data form 3
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Put stub definitions in all of Thumb
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DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(ADD2, ARM_STUB)
DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(CMP1, ARM_STUB)
Implement MOV(1)
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DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(MOV1, cpu->gprs[rd] = immediate; THUMB_NEUTRAL_S(, , cpu->gprs[rd]))
Put stub definitions in all of Thumb
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DEFINE_DATA_FORM_3_INSTRUCTION_THUMB(SUB2, ARM_STUB)
Start filling in THUMB table with insane preprocessor tricks
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Define data format 5
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#define DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NAME, BODY) \
DEFINE_INSTRUCTION_THUMB(NAME, \
int rd = opcode & 0x0007; \
int rn = (opcode >> 3) & 0x0007; \
BODY;)
Put stub definitions in all of Thumb
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DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(AND, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(EOR, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSL2, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(LSR2, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ASR2, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ADC, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(SBC, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ROR, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(TST, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(NEG, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMP2, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(CMN, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(ORR, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MUL, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(BIC, ARM_STUB)
DEFINE_DATA_FORM_5_INSTRUCTION_THUMB(MVN, ARM_STUB)
Define data format 5
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Stub out format 8
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#define DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME, H1, H2, BODY) \
DEFINE_INSTRUCTION_THUMB(NAME, \
int rd = opcode & 0x0007 | H1; \
int rm = (opcode >> 3) & 0x0007 | H2; \
BODY;)
#define DEFINE_INSTRUCTION_WITH_HIGH_THUMB(NAME, BODY) \
DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 00, 0, 0, BODY) \
DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 01, 0, 8, BODY) \
DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 10, 8, 0, BODY) \
DEFINE_INSTRUCTION_WITH_HIGH_EX_THUMB(NAME ## 11, 8, 8, BODY)
Put stub definitions in all of Thumb
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DEFINE_INSTRUCTION_WITH_HIGH_THUMB(ADD4, ARM_STUB)
DEFINE_INSTRUCTION_WITH_HIGH_THUMB(CMP3, ARM_STUB)
Implement MOV(3)
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DEFINE_INSTRUCTION_WITH_HIGH_THUMB(MOV3, cpu->gprs[rd] = cpu->gprs[rm])
Stub out format 8
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Stub out ADD from PC and SP
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#define DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB(NAME, RD, BODY) \
Stub out LDR3
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DEFINE_INSTRUCTION_THUMB(NAME, \
int rd = RD; \
BODY;)
Stub out ADD from PC and SP
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#define DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(NAME, BODY) \
COUNT_3(DEFINE_IMMEDIATE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
Stub out LDR3
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Put stub definitions in all of Thumb
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR3, ARM_STUB)
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(LDR4, ARM_STUB)
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(STR3, ARM_STUB)
Stub out ADD from PC and SP
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Put stub definitions in all of Thumb
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DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD5, ARM_STUB)
DEFINE_IMMEDIATE_WITH_REGISTER_THUMB(ADD6, ARM_STUB)
Stub out LDR3
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Stub out more load/store format 2
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#define DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB(NAME, RM, BODY) \
Stub out STR2
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DEFINE_INSTRUCTION_THUMB(NAME, \
Stub out more load/store format 2
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int rm = RM; \
Stub out STR2
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BODY;)
Stub out more load/store format 2
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#define DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(NAME, BODY) \
COUNT_3(DEFINE_LOAD_STORE_WITH_REGISTER_EX_THUMB, NAME ## _R, BODY)
Stub out STR2
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Put stub definitions in all of Thumb
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DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDR2, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRB2, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRH2, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSB, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(LDRSH, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STR2, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRB2, ARM_STUB)
DEFINE_LOAD_STORE_WITH_REGISTER_THUMB(STRH2, ARM_STUB)
Stub out STR2
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Implement LDMIA/STMIA/PUSH/POP
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#define DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(NAME, RS, ADDRESS, LOOP, BODY, OP, PRE_BODY, POST_BODY, WRITEBACK) \
Stub out LDMIA/STMIA
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DEFINE_INSTRUCTION_THUMB(NAME, \
Implement LDMIA/STMIA/PUSH/POP
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int rn = (opcode >> 8) & 0x000F; \
Stub out LDMIA/STMIA
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int rs = RS; \
Implement LDMIA/STMIA/PUSH/POP
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int32_t address = ADDRESS; \
int m; \
int i; \
PRE_BODY; \
for LOOP { \
if (rs & m) { \
BODY; \
address OP 4; \
} \
} \
POST_BODY; \
WRITEBACK;)
#define DEFINE_LOAD_STORE_MULTIPLE_THUMB(NAME, BODY, WRITEBACK) \
COUNT_3(DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB, NAME ## _R, cpu->gprs[rn], (m = 0x01, i = 0; i < 8; m <<= 1, ++i), BODY, +=, , , WRITEBACK)
DEFINE_LOAD_STORE_MULTIPLE_THUMB(LDMIA,\
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
if (!((1 << rn) & rs)) { \
cpu->gprs[rn] = address; \
})
DEFINE_LOAD_STORE_MULTIPLE_THUMB(STMIA, \
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
cpu->gprs[rn] = address)
Stub out LDMIA/STMIA
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Stub out conditional branches
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#define DEFINE_CONDITIONAL_BRANCH_THUMB(COND) \
DEFINE_INSTRUCTION_THUMB(B ## COND, \
if (ARM_COND_ ## COND) { \
Put stub definitions in all of Thumb
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ARM_STUB; \
Stub out conditional branches
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})
DEFINE_CONDITIONAL_BRANCH_THUMB(EQ)
DEFINE_CONDITIONAL_BRANCH_THUMB(NE)
DEFINE_CONDITIONAL_BRANCH_THUMB(CS)
DEFINE_CONDITIONAL_BRANCH_THUMB(CC)
DEFINE_CONDITIONAL_BRANCH_THUMB(MI)
DEFINE_CONDITIONAL_BRANCH_THUMB(PL)
DEFINE_CONDITIONAL_BRANCH_THUMB(VS)
DEFINE_CONDITIONAL_BRANCH_THUMB(VC)
DEFINE_CONDITIONAL_BRANCH_THUMB(LS)
DEFINE_CONDITIONAL_BRANCH_THUMB(HI)
DEFINE_CONDITIONAL_BRANCH_THUMB(GE)
DEFINE_CONDITIONAL_BRANCH_THUMB(LT)
DEFINE_CONDITIONAL_BRANCH_THUMB(GT)
DEFINE_CONDITIONAL_BRANCH_THUMB(LE)
Implement ADD(7)/SUB(4)
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DEFINE_INSTRUCTION_THUMB(ADD7, cpu->gprs[ARM_SP] += (opcode & 0x7F) << 2)
DEFINE_INSTRUCTION_THUMB(SUB4, cpu->gprs[ARM_SP] -= (opcode & 0x7F) << 2)
Put stub definitions in all of Thumb
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Implement LDMIA/STMIA/PUSH/POP
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DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POP, \
opcode & 0x00FF, \
cpu->gprs[ARM_SP], \
(m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
+=, \
, , \
cpu->gprs[ARM_SP] = address)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(POPR, \
opcode & 0x00FF, \
cpu->gprs[ARM_SP], \
(m = 0x01, i = 0; i < 8; m <<= 1, ++i), \
cpu->gprs[i] = cpu->memory->load32(cpu->memory, address), \
+=, \
, \
cpu->gprs[ARM_PC] = cpu->memory->load32(cpu->memory, address) & 0xFFFFFFFE; \
address += 4;, \
cpu->gprs[ARM_SP] = address)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSH, \
opcode & 0x00FF, \
cpu->gprs[ARM_SP] - 4, \
(m = 0x80, i = 7; m; m >>= 1, --i), \
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
-=, \
, , \
cpu->gprs[ARM_SP] = address + 4)
DEFINE_LOAD_STORE_MULTIPLE_EX_THUMB(PUSHR, \
opcode & 0x00FF, \
cpu->gprs[ARM_SP] - 4, \
(m = 0x80, i = 7; m; m >>= 1, --i), \
cpu->memory->store32(cpu->memory, address, cpu->gprs[i]), \
-=, \
cpu->memory->store32(cpu->memory, address, cpu->gprs[ARM_LR]); \
address -= 4;, \
, \
cpu->gprs[ARM_SP] = address + 4)
Put stub definitions in all of Thumb
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DEFINE_INSTRUCTION_THUMB(ILL, ARM_STUB)
DEFINE_INSTRUCTION_THUMB(BKPT, ARM_STUB)
DEFINE_INSTRUCTION_THUMB(B, ARM_STUB)
Implement BL
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DEFINE_INSTRUCTION_THUMB(BL1, \
int16_t immediate = (opcode & 0x07FF) << 7; \
cpu->gprs[ARM_LR] = cpu->gprs[ARM_PC] + (((int32_t) immediate) << 4);)
DEFINE_INSTRUCTION_THUMB(BL2, \
uint16_t immediate = (opcode & 0x07FF) << 1; \
uint32_t pc = cpu->gprs[ARM_PC]; \
cpu->gprs[ARM_PC] = cpu->gprs[ARM_LR] + immediate; \
cpu->gprs[ARM_LR] = pc - 1; \
THUMB_WRITE_PC;)
Put stub definitions in all of Thumb
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DEFINE_INSTRUCTION_THUMB(BX, ARM_STUB)
DEFINE_INSTRUCTION_THUMB(SWI, ARM_STUB)
Stub out format 8
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#define DECLARE_INSTRUCTION_THUMB(EMITTER, NAME) \
EMITTER ## NAME
#define DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, NAME) \
DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 00), \
DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 01), \
DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 10), \
DECLARE_INSTRUCTION_THUMB(EMITTER, NAME ## 11)
Macro-insanity for Thumb
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#define DUMMY(X, ...) X,
Add data form 3
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#define DUMMY_4(...) \
DUMMY(__VA_ARGS__) \
DUMMY(__VA_ARGS__) \
DUMMY(__VA_ARGS__) \
DUMMY(__VA_ARGS__)
Start filling in THUMB table with insane preprocessor tricks
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#define DECLARE_THUMB_EMITTER_BLOCK(EMITTER) \
Macro-insanity for Thumb
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APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSL1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LSR1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ASR1_)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD3_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB3_R)) \
ADD/SUB 1 stubs
2013-04-09 10:20:32 +00:00
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD1_)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB1_)) \
Add data form 3
2013-04-09 11:20:14 +00:00
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, MOV1_R)) \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, CMP1_R)) \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD2_R)) \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, SUB2_R)) \
Define data format 5
2013-04-10 05:35:51 +00:00
DECLARE_INSTRUCTION_THUMB(EMITTER, AND), \
DECLARE_INSTRUCTION_THUMB(EMITTER, EOR), \
DECLARE_INSTRUCTION_THUMB(EMITTER, LSL2), \
DECLARE_INSTRUCTION_THUMB(EMITTER, LSR2), \
DECLARE_INSTRUCTION_THUMB(EMITTER, ASR2), \
DECLARE_INSTRUCTION_THUMB(EMITTER, ADC), \
DECLARE_INSTRUCTION_THUMB(EMITTER, SBC), \
DECLARE_INSTRUCTION_THUMB(EMITTER, ROR), \
DECLARE_INSTRUCTION_THUMB(EMITTER, TST), \
DECLARE_INSTRUCTION_THUMB(EMITTER, NEG), \
DECLARE_INSTRUCTION_THUMB(EMITTER, CMP2), \
DECLARE_INSTRUCTION_THUMB(EMITTER, CMN), \
DECLARE_INSTRUCTION_THUMB(EMITTER, ORR), \
DECLARE_INSTRUCTION_THUMB(EMITTER, MUL), \
DECLARE_INSTRUCTION_THUMB(EMITTER, BIC), \
DECLARE_INSTRUCTION_THUMB(EMITTER, MVN), \
Stub out format 8
2013-04-10 05:51:21 +00:00
DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, ADD4), \
DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, CMP3), \
DECLARE_INSTRUCTION_WITH_HIGH_THUMB(EMITTER, MOV3), \
Put in missing BX
2013-04-10 06:16:30 +00:00
DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
DECLARE_INSTRUCTION_THUMB(EMITTER, BX), \
Stub out format 8
2013-04-10 05:51:21 +00:00
DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
DECLARE_INSTRUCTION_THUMB(EMITTER, ILL), \
Stub out STR2
2013-04-10 06:00:31 +00:00
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR3_R)) \
Stub out more load/store format 2
2013-04-10 06:27:37 +00:00
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR2_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH2_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB2_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSB_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR2_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH2_R)) \
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB2_R)) \
Stub out more load/stores with immediates
2013-04-10 06:34:25 +00:00
APPLY(COUNT_3, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRSH_R)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STR1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRB1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRB1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, STRH1_)) \
APPLY(COUNT_5, DUMMY, DECLARE_INSTRUCTION_THUMB(EMITTER, LDRH1_)) \
Stub out LDR/STR from SP
2013-04-10 06:37:28 +00:00
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STR3_R)) \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDR4_R)) \
Stub out ADD from PC and SP
2013-04-10 06:45:08 +00:00
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD5_R)) \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, ADD6_R)) \
Stub out ADD7 and SUB4
2013-04-10 06:47:37 +00:00
DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
DECLARE_INSTRUCTION_THUMB(EMITTER, ADD7), \
DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
DECLARE_INSTRUCTION_THUMB(EMITTER, SUB4), \
Stub out POP/PUSH
2013-04-10 07:00:24 +00:00
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSH)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, PUSHR)), \
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
DO_8(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POP)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, POPR)), \
Stub out BKPT (not in ARMv4T, but still useful)
2013-04-11 03:50:56 +00:00
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BKPT)), \
Stub out LDMIA/STMIA
2013-04-11 03:58:05 +00:00
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, STMIA_R)) \
APPLY(COUNT_3, DUMMY_4, DECLARE_INSTRUCTION_THUMB(EMITTER, LDMIA_R)) \
Stub out conditional branches
2013-04-11 04:04:41 +00:00
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BEQ)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BNE)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCS)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BCC)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BMI)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BPL)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVS)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BVC)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BHI)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLS)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGE)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLT)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BGT)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BLE)), \
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL)), \
Stub out SWI
2013-04-11 04:05:19 +00:00
DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, SWI)), \
Stub out B
2013-04-11 04:09:22 +00:00
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, B))), \
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, ILL))), \
Stub out BL, finishing Thumb table
2013-04-11 04:11:05 +00:00
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL1))), \
DO_8(DO_4(DECLARE_INSTRUCTION_THUMB(EMITTER, BL2))) \
Start filling in THUMB table with insane preprocessor tricks
2013-04-09 09:57:24 +00:00
static const ThumbInstruction _thumbTable[0x400] = {
DECLARE_THUMB_EMITTER_BLOCK(_ThumbInstruction)
};