; this file was created with wlalink by ville helin <vhelin@iki.fi>.
; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/acceptance/boot_regs-mgb.gb".

[labels]
01:4bff print_load_font
01:4c0c print_string
01:4c16 print_a
01:4c20 print_newline
01:4c2b print_digit
01:4c38 print_regs
01:4c41 _print_sl_data0
01:4c47 _print_sl_out0
01:4c54 _print_sl_data1
01:4c5a _print_sl_out1
01:4c6c _print_sl_data2
01:4c72 _print_sl_out2
01:4c7f _print_sl_data3
01:4c85 _print_sl_out3
01:4c97 _print_sl_data4
01:4c9d _print_sl_out4
01:4caa _print_sl_data5
01:4cb0 _print_sl_out5
01:4cc2 _print_sl_data6
01:4cc8 _print_sl_out6
01:4cd5 _print_sl_data7
01:4cdb _print_sl_out7
01:4000 font
00:c000 regs_save
00:c000 regs_save.f
00:c001 regs_save.a
00:c002 regs_save.c
00:c003 regs_save.b
00:c004 regs_save.e
00:c005 regs_save.d
00:c006 regs_save.l
00:c007 regs_save.h
00:c008 regs_flags
00:c009 regs_assert
00:c009 regs_assert.f
00:c00a regs_assert.a
00:c00b regs_assert.c
00:c00c regs_assert.b
00:c00d regs_assert.e
00:c00e regs_assert.d
00:c00f regs_assert.l
00:c010 regs_assert.h
00:c011 memdump_len
00:c012 memdump_addr
01:47f0 memcpy
01:47f9 memset
01:4802 memcmp
01:4810 clear_vram
01:481a clear_oam
01:4824 disable_lcd_safe
01:482a _wait_ly_0
01:4830 _wait_ly_1
01:4839 reset_screen
01:484d process_results
01:4861 _wait_ly_2
01:4867 _wait_ly_3
01:487d _print_results_halt_0
01:4880 _process_results_cb
01:488b _print_sl_data8
01:4895 _print_sl_out8
01:48af _print_sl_data9
01:48ba _print_sl_out9
01:48d2 _print_sl_data10
01:48de _print_sl_out10
01:48df dump_mem
01:48fe _dump_mem_line
01:4928 _check_asserts
01:4936 _print_sl_data11
01:4939 _print_sl_out11
01:4945 _print_sl_data12
01:4947 _print_sl_out12
01:494f _print_sl_data13
01:4952 _print_sl_out13
01:495c __check_assert_fail0
01:4967 _print_sl_data14
01:496a _print_sl_out14
01:496d __check_assert_ok0
01:4975 _print_sl_data15
01:497a _print_sl_out15
01:497c __check_assert_skip0
01:4984 _print_sl_data16
01:498c _print_sl_out16
01:498c __check_assert_out0
01:4998 _print_sl_data17
01:499a _print_sl_out17
01:49a2 _print_sl_data18
01:49a5 _print_sl_out18
01:49af __check_assert_fail1
01:49ba _print_sl_data19
01:49bd _print_sl_out19
01:49c0 __check_assert_ok1
01:49c8 _print_sl_data20
01:49cd _print_sl_out20
01:49cf __check_assert_skip1
01:49d7 _print_sl_data21
01:49df _print_sl_out21
01:49df __check_assert_out1
01:49ea _print_sl_data22
01:49ed _print_sl_out22
01:49f9 _print_sl_data23
01:49fb _print_sl_out23
01:4a03 _print_sl_data24
01:4a06 _print_sl_out24
01:4a10 __check_assert_fail2
01:4a1b _print_sl_data25
01:4a1e _print_sl_out25
01:4a21 __check_assert_ok2
01:4a29 _print_sl_data26
01:4a2e _print_sl_out26
01:4a30 __check_assert_skip2
01:4a38 _print_sl_data27
01:4a40 _print_sl_out27
01:4a40 __check_assert_out2
01:4a4c _print_sl_data28
01:4a4e _print_sl_out28
01:4a56 _print_sl_data29
01:4a59 _print_sl_out29
01:4a63 __check_assert_fail3
01:4a6e _print_sl_data30
01:4a71 _print_sl_out30
01:4a74 __check_assert_ok3
01:4a7c _print_sl_data31
01:4a81 _print_sl_out31
01:4a83 __check_assert_skip3
01:4a8b _print_sl_data32
01:4a93 _print_sl_out32
01:4a93 __check_assert_out3
01:4a9e _print_sl_data33
01:4aa1 _print_sl_out33
01:4aad _print_sl_data34
01:4aaf _print_sl_out34
01:4ab7 _print_sl_data35
01:4aba _print_sl_out35
01:4ac4 __check_assert_fail4
01:4acf _print_sl_data36
01:4ad2 _print_sl_out36
01:4ad5 __check_assert_ok4
01:4add _print_sl_data37
01:4ae2 _print_sl_out37
01:4ae4 __check_assert_skip4
01:4aec _print_sl_data38
01:4af4 _print_sl_out38
01:4af4 __check_assert_out4
01:4b00 _print_sl_data39
01:4b02 _print_sl_out39
01:4b0a _print_sl_data40
01:4b0d _print_sl_out40
01:4b17 __check_assert_fail5
01:4b22 _print_sl_data41
01:4b25 _print_sl_out41
01:4b28 __check_assert_ok5
01:4b30 _print_sl_data42
01:4b35 _print_sl_out42
01:4b37 __check_assert_skip5
01:4b3f _print_sl_data43
01:4b47 _print_sl_out43
01:4b47 __check_assert_out5
01:4b52 _print_sl_data44
01:4b55 _print_sl_out44
01:4b61 _print_sl_data45
01:4b63 _print_sl_out45
01:4b6b _print_sl_data46
01:4b6e _print_sl_out46
01:4b78 __check_assert_fail6
01:4b83 _print_sl_data47
01:4b86 _print_sl_out47
01:4b89 __check_assert_ok6
01:4b91 _print_sl_data48
01:4b96 _print_sl_out48
01:4b98 __check_assert_skip6
01:4ba0 _print_sl_data49
01:4ba8 _print_sl_out49
01:4ba8 __check_assert_out6
01:4bb4 _print_sl_data50
01:4bb6 _print_sl_out50
01:4bbe _print_sl_data51
01:4bc1 _print_sl_out51
01:4bcb __check_assert_fail7
01:4bd6 _print_sl_data52
01:4bd9 _print_sl_out52
01:4bdc __check_assert_ok7
01:4be4 _print_sl_data53
01:4be9 _print_sl_out53
01:4beb __check_assert_skip7
01:4bf3 _print_sl_data54
01:4bfb _print_sl_out54
01:4bfb __check_assert_out7
00:01d2 invalid_sp
00:01e6 _wait_ly_4
00:01ec _wait_ly_5
00:0202 _print_results_halt_1
00:0205 _test_failure_cb_0
00:020d _print_sl_data55
00:021e _print_sl_out55
00:c014 sp_save
