; this file was created with wlalink by ville helin <vhelin@iki.fi>.
; wla symbolic information for "/Users/vicki/Scratch/mooneye-gb/tests/build/emulator-only/mbc1/multicart_rom_8Mb.gb".

[labels]
01:4001 print_load_font
01:400e print_string
01:4018 print_a
01:4022 print_newline
01:402d print_digit
01:403a print_regs
01:4043 _print_sl_data0
01:4049 _print_sl_out0
01:4056 _print_sl_data1
01:405c _print_sl_out1
01:406e _print_sl_data2
01:4074 _print_sl_out2
01:4081 _print_sl_data3
01:4087 _print_sl_out3
01:4099 _print_sl_data4
01:409f _print_sl_out4
01:40ac _print_sl_data5
01:40b2 _print_sl_out5
01:40c4 _print_sl_data6
01:40ca _print_sl_out6
01:40d7 _print_sl_data7
01:40dd _print_sl_out7
01:4134 font
00:c000 regs_save
00:c000 regs_save.f
00:c001 regs_save.a
00:c002 regs_save.c
00:c003 regs_save.b
00:c004 regs_save.e
00:c005 regs_save.d
00:c006 regs_save.l
00:c007 regs_save.h
00:c008 regs_flags
00:c009 regs_assert
00:c009 regs_assert.f
00:c00a regs_assert.a
00:c00b regs_assert.c
00:c00c regs_assert.b
00:c00d regs_assert.e
00:c00e regs_assert.d
00:c00f regs_assert.l
00:c010 regs_assert.h
00:c011 memdump_len
00:c012 memdump_addr
01:4924 memcpy
01:492d memset
01:4936 memcmp
01:4944 clear_vram
01:494e clear_oam
01:4958 disable_lcd_safe
01:495e _wait_ly_0
01:4964 _wait_ly_1
01:496d reset_screen
01:4981 process_results
01:4995 _wait_ly_2
01:499b _wait_ly_3
01:49b1 _print_results_halt_0
01:49b4 _process_results_cb
01:49bf _print_sl_data8
01:49c9 _print_sl_out8
01:49e3 _print_sl_data9
01:49ee _print_sl_out9
01:4a06 _print_sl_data10
01:4a12 _print_sl_out10
01:4a13 dump_mem
01:4a32 _dump_mem_line
01:4a5c _check_asserts
01:4a6a _print_sl_data11
01:4a6d _print_sl_out11
01:4a79 _print_sl_data12
01:4a7b _print_sl_out12
01:4a83 _print_sl_data13
01:4a86 _print_sl_out13
01:4a90 __check_assert_fail0
01:4a9b _print_sl_data14
01:4a9e _print_sl_out14
01:4aa1 __check_assert_ok0
01:4aa9 _print_sl_data15
01:4aae _print_sl_out15
01:4ab0 __check_assert_skip0
01:4ab8 _print_sl_data16
01:4ac0 _print_sl_out16
01:4ac0 __check_assert_out0
01:4acc _print_sl_data17
01:4ace _print_sl_out17
01:4ad6 _print_sl_data18
01:4ad9 _print_sl_out18
01:4ae3 __check_assert_fail1
01:4aee _print_sl_data19
01:4af1 _print_sl_out19
01:4af4 __check_assert_ok1
01:4afc _print_sl_data20
01:4b01 _print_sl_out20
01:4b03 __check_assert_skip1
01:4b0b _print_sl_data21
01:4b13 _print_sl_out21
01:4b13 __check_assert_out1
01:4b1e _print_sl_data22
01:4b21 _print_sl_out22
01:4b2d _print_sl_data23
01:4b2f _print_sl_out23
01:4b37 _print_sl_data24
01:4b3a _print_sl_out24
01:4b44 __check_assert_fail2
01:4b4f _print_sl_data25
01:4b52 _print_sl_out25
01:4b55 __check_assert_ok2
01:4b5d _print_sl_data26
01:4b62 _print_sl_out26
01:4b64 __check_assert_skip2
01:4b6c _print_sl_data27
01:4b74 _print_sl_out27
01:4b74 __check_assert_out2
01:4b80 _print_sl_data28
01:4b82 _print_sl_out28
01:4b8a _print_sl_data29
01:4b8d _print_sl_out29
01:4b97 __check_assert_fail3
01:4ba2 _print_sl_data30
01:4ba5 _print_sl_out30
01:4ba8 __check_assert_ok3
01:4bb0 _print_sl_data31
01:4bb5 _print_sl_out31
01:4bb7 __check_assert_skip3
01:4bbf _print_sl_data32
01:4bc7 _print_sl_out32
01:4bc7 __check_assert_out3
01:4bd2 _print_sl_data33
01:4bd5 _print_sl_out33
01:4be1 _print_sl_data34
01:4be3 _print_sl_out34
01:4beb _print_sl_data35
01:4bee _print_sl_out35
01:4bf8 __check_assert_fail4
01:4c03 _print_sl_data36
01:4c06 _print_sl_out36
01:4c09 __check_assert_ok4
01:4c11 _print_sl_data37
01:4c16 _print_sl_out37
01:4c18 __check_assert_skip4
01:4c20 _print_sl_data38
01:4c28 _print_sl_out38
01:4c28 __check_assert_out4
01:4c34 _print_sl_data39
01:4c36 _print_sl_out39
01:4c3e _print_sl_data40
01:4c41 _print_sl_out40
01:4c4b __check_assert_fail5
01:4c56 _print_sl_data41
01:4c59 _print_sl_out41
01:4c5c __check_assert_ok5
01:4c64 _print_sl_data42
01:4c69 _print_sl_out42
01:4c6b __check_assert_skip5
01:4c73 _print_sl_data43
01:4c7b _print_sl_out43
01:4c7b __check_assert_out5
01:4c86 _print_sl_data44
01:4c89 _print_sl_out44
01:4c95 _print_sl_data45
01:4c97 _print_sl_out45
01:4c9f _print_sl_data46
01:4ca2 _print_sl_out46
01:4cac __check_assert_fail6
01:4cb7 _print_sl_data47
01:4cba _print_sl_out47
01:4cbd __check_assert_ok6
01:4cc5 _print_sl_data48
01:4cca _print_sl_out48
01:4ccc __check_assert_skip6
01:4cd4 _print_sl_data49
01:4cdc _print_sl_out49
01:4cdc __check_assert_out6
01:4ce8 _print_sl_data50
01:4cea _print_sl_out50
01:4cf2 _print_sl_data51
01:4cf5 _print_sl_out51
01:4cff __check_assert_fail7
01:4d0a _print_sl_data52
01:4d0d _print_sl_out52
01:4d10 __check_assert_ok7
01:4d18 _print_sl_data53
01:4d1d _print_sl_out53
01:4d1f __check_assert_skip7
01:4d27 _print_sl_data54
01:4d2f _print_sl_out54
01:4d2f __check_assert_out7
00:016b fail
00:017f _wait_ly_4
00:0185 _wait_ly_5
00:019b _print_results_halt_1
00:019e _fail_cb
00:01a6 _print_sl_data55
00:01b2 _print_sl_out55
00:01c2 _print_sl_data56
00:01ce _print_sl_out56
00:01d8 _print_sl_data57
00:01e4 _print_sl_out57
00:01ef _print_sl_data58
00:01f5 _print_sl_out58
00:0208 _print_sl_data59
00:0215 _print_sl_out59
00:0225 _print_sl_data60
00:0232 _print_sl_out60
00:0242 _print_sl_data61
00:024f _print_sl_out61
00:025a c000_functions_start
00:025a run_test_suite
00:0284 _wait_ly_6
00:028a _wait_ly_7
00:02a0 _print_results_halt_2
00:02a3 _test_ok_cb_0
00:02ab _print_sl_data62
00:02b3 _print_sl_out62
00:02b6 run_tests
00:02c4 run_test_cases
00:02d2 test_case
00:02ef restore_mbc1
00:02f8 switch_bank
00:0309 fetch_expected_value
00:0328 c000_functions_end
00:0328 expected_banks
