282 lines
6.6 KiB
C++
282 lines
6.6 KiB
C++
/*
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Copyright 2016-2022 melonDS team
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#ifndef ARMJIT_X64_COMPILER_H
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#define ARMJIT_X64_COMPILER_H
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#include "../dolphin/x64Emitter.h"
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#include "../ARMJIT.h"
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#include "../ARMJIT_Internal.h"
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#include "../ARMJIT_RegisterCache.h"
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#ifdef JIT_PROFILING_ENABLED
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#include <jitprofiling.h>
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#endif
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#include <unordered_map>
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namespace ARMJIT
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{
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const Gen::X64Reg RCPU = Gen::RBP;
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const Gen::X64Reg RCPSR = Gen::R15;
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const Gen::X64Reg RSCRATCH = Gen::EAX;
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const Gen::X64Reg RSCRATCH2 = Gen::EDX;
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const Gen::X64Reg RSCRATCH3 = Gen::ECX;
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const Gen::X64Reg RSCRATCH4 = Gen::R8;
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struct LoadStorePatch
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{
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void* PatchFunc;
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s16 Offset;
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u16 Size;
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};
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struct Op2
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{
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Op2()
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{}
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Op2(u32 imm)
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: IsImm(true), Imm(imm)
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{}
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Op2(int reg, int op, int amount)
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: IsImm(false)
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{
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Reg.Reg = reg;
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Reg.Op = op;
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Reg.Amount = amount;
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}
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bool IsImm;
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union
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{
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struct
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{
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int Reg, Op, Amount;
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} Reg;
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u32 Imm;
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};
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};
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class Compiler : public Gen::XEmitter
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{
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public:
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Compiler();
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void Reset();
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JitBlockEntry CompileBlock(ARM* cpu, bool thumb, FetchedInstr instrs[], int instrsCount, bool hasMemoryInstr);
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void LoadReg(int reg, Gen::X64Reg nativeReg);
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void SaveReg(int reg, Gen::X64Reg nativeReg);
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bool CanCompile(bool thumb, u16 kind);
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typedef void (Compiler::*CompileFunc)();
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void Comp_JumpTo(Gen::X64Reg addr, bool restoreCPSR = false);
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void Comp_JumpTo(u32 addr, bool forceNonConstantCycles = false);
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void Comp_AddCycles_C(bool forceNonConstant = false);
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void Comp_AddCycles_CI(u32 i);
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void Comp_AddCycles_CI(Gen::X64Reg i, int add);
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void Comp_AddCycles_CDI();
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void Comp_AddCycles_CD();
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enum
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{
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opSetsFlags = 1 << 0,
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opSymmetric = 1 << 1,
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opRetriveCV = 1 << 2,
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opInvertCarry = 1 << 3,
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opSyncCarry = 1 << 4,
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opInvertOp2 = 1 << 5,
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};
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void Nop() {}
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void A_Comp_Arith();
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void A_Comp_MovOp();
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void A_Comp_CmpOp();
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void A_Comp_MUL_MLA();
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void A_Comp_Mul_Long();
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void A_Comp_CLZ();
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void A_Comp_MemWB();
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void A_Comp_MemHalf();
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void A_Comp_LDM_STM();
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void A_Comp_BranchImm();
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void A_Comp_BranchXchangeReg();
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void A_Comp_MRS();
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void A_Comp_MSR();
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void T_Comp_ShiftImm();
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void T_Comp_AddSub_();
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void T_Comp_ALU_Imm8();
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void T_Comp_ALU();
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void T_Comp_ALU_HiReg();
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void T_Comp_MUL();
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void T_Comp_RelAddr();
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void T_Comp_AddSP();
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void T_Comp_MemReg();
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void T_Comp_MemImm();
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void T_Comp_MemRegHalf();
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void T_Comp_MemImmHalf();
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void T_Comp_LoadPCRel();
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void T_Comp_MemSPRel();
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void T_Comp_PUSH_POP();
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void T_Comp_LDMIA_STMIA();
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void T_Comp_BCOND();
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void T_Comp_B();
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void T_Comp_BranchXchangeReg();
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void T_Comp_BL_LONG_1();
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void T_Comp_BL_LONG_2();
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void T_Comp_BL_Merged();
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enum
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{
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memop_Writeback = 1 << 0,
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memop_Post = 1 << 1,
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memop_SignExtend = 1 << 2,
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memop_Store = 1 << 3,
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memop_SubtractOffset = 1 << 4
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};
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void Comp_MemAccess(int rd, int rn, const Op2& op2, int size, int flags);
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s32 Comp_MemAccessBlock(int rn, BitSet16 regs, bool store, bool preinc, bool decrement, bool usermode, bool skipLoadingRn);
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bool Comp_MemLoadLiteral(int size, bool signExtend, int rd, u32 addr);
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void Comp_ArithTriOp(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
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Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
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void Comp_ArithTriOpReverse(void (Compiler::*op)(int, const Gen::OpArg&, const Gen::OpArg&),
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Gen::OpArg rd, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed, int opFlags);
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void Comp_CmpOp(int op, Gen::OpArg rn, Gen::OpArg op2, bool carryUsed);
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void Comp_MulOp(bool S, bool add, Gen::OpArg rd, Gen::OpArg rm, Gen::OpArg rs, Gen::OpArg rn);
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void Comp_RetriveFlags(bool sign, bool retriveCV, bool carryUsed);
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void Comp_SpecialBranchBehaviour(bool taken);
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Gen::OpArg Comp_RegShiftImm(int op, int amount, Gen::OpArg rm, bool S, bool& carryUsed);
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Gen::OpArg Comp_RegShiftReg(int op, Gen::OpArg rs, Gen::OpArg rm, bool S, bool& carryUsed);
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Gen::OpArg A_Comp_GetALUOp2(bool S, bool& carryUsed);
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void LoadCPSR();
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void SaveCPSR(bool flagClean = true);
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bool FlagsNZRequired()
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{ return CurInstr.SetFlags & 0xC; }
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Gen::FixupBranch CheckCondition(u32 cond);
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void PushRegs(bool saveHiRegs, bool saveRegsToBeChanged, bool allowUnload = true);
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void PopRegs(bool saveHiRegs, bool saveRegsToBeChanged);
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Gen::OpArg MapReg(int reg)
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{
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if (reg == 15 && !(RegCache.LoadedRegs & (1 << 15)))
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return Gen::Imm32(R15);
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assert(RegCache.Mapping[reg] != Gen::INVALID_REG);
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return Gen::R(RegCache.Mapping[reg]);
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}
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JitBlockEntry AddEntryOffset(u32 offset)
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{
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return (JitBlockEntry)(ResetStart + offset);
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}
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u32 SubEntryOffset(JitBlockEntry entry)
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{
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return (u8*)entry - ResetStart;
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}
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void SwitchToNearCode()
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{
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FarCode = GetWritableCodePtr();
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SetCodePtr(NearCode);
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}
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void SwitchToFarCode()
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{
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NearCode = GetWritableCodePtr();
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SetCodePtr(FarCode);
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}
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bool IsJITFault(u8* addr);
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u8* RewriteMemAccess(u8* pc);
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#ifdef JIT_PROFILING_ENABLED
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void CreateMethod(const char* namefmt, void* start, ...);
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#endif
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u8* FarCode;
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u8* NearCode;
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u32 FarSize;
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u32 NearSize;
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u8* NearStart;
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u8* FarStart;
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void* PatchedStoreFuncs[2][2][3][16];
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void* PatchedLoadFuncs[2][2][3][2][16];
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std::unordered_map<u8*, LoadStorePatch> LoadStorePatches;
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u8* ResetStart;
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u32 CodeMemSize;
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bool Exit;
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bool IrregularCycles;
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void* ReadBanked;
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void* WriteBanked;
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bool CPSRDirty = false;
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FetchedInstr CurInstr;
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RegisterCache<Compiler, Gen::X64Reg> RegCache;
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bool Thumb;
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u32 Num;
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u32 R15;
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u32 CodeRegion;
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u32 ConstantCycles;
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ARM* CurCPU;
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};
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}
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#endif
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