397 lines
8.4 KiB
C++
397 lines
8.4 KiB
C++
/*
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Copyright 2016-2017 StapleButter
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This file is part of melonDS.
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melonDS is free software: you can redistribute it and/or modify it under
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the terms of the GNU General Public License as published by the Free
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Software Foundation, either version 3 of the License, or (at your option)
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any later version.
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melonDS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with melonDS. If not, see http://www.gnu.org/licenses/.
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*/
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#include <stdio.h>
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#include "NDS.h"
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#include "ARM.h"
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#include "ARMInterpreter.h"
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u32 ARM::ConditionTable[16] =
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{
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0xF0F0, // EQ
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0x0F0F, // NE
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0xCCCC, // CS
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0x3333, // CC
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0xFF00, // MI
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0x00FF, // PL
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0xAAAA, // VS
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0x5555, // VC
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0x0C0C, // HI
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0xF3F3, // LS
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0xAA55, // GE
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0x55AA, // LT
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0x0A05, // GT
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0xF5FA, // LE
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0xFFFF, // AL
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0x0000 // NE
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};
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ARM::ARM(u32 num)
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{
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// well uh
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Num = num;
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for (int i = 0; i < 16; i++)
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{
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Waitstates[0][i] = 1;
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Waitstates[1][i] = 1;
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Waitstates[2][i] = 1;
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Waitstates[3][i] = 1;
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}
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if (!num)
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{
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// ARM9
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Waitstates[0][0x2] = 1; // main RAM timing, assuming cache hit
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Waitstates[0][0x3] = 4;
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Waitstates[0][0x4] = 4;
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Waitstates[0][0x5] = 5;
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Waitstates[0][0x6] = 5;
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Waitstates[0][0x7] = 4;
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Waitstates[0][0x8] = 19;
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Waitstates[0][0x9] = 19;
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Waitstates[0][0xF] = 4;
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Waitstates[1][0x2] = 1;
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Waitstates[1][0x3] = 8;
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Waitstates[1][0x4] = 8;
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Waitstates[1][0x5] = 10;
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Waitstates[1][0x6] = 10;
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Waitstates[1][0x7] = 8;
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Waitstates[1][0x8] = 38;
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Waitstates[1][0x9] = 38;
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Waitstates[1][0xF] = 8;
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Waitstates[2][0x2] = 1;
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Waitstates[2][0x3] = 2;
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Waitstates[2][0x4] = 2;
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Waitstates[2][0x5] = 2;
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Waitstates[2][0x6] = 2;
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Waitstates[2][0x7] = 2;
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Waitstates[2][0x8] = 12;
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Waitstates[2][0x9] = 12;
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Waitstates[2][0xA] = 20;
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Waitstates[2][0xF] = 2;
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Waitstates[3][0x2] = 1;
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Waitstates[3][0x3] = 2;
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Waitstates[3][0x4] = 2;
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Waitstates[3][0x5] = 4;
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Waitstates[3][0x6] = 4;
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Waitstates[3][0x7] = 2;
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Waitstates[3][0x8] = 24;
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Waitstates[3][0x9] = 24;
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Waitstates[3][0xA] = 20;
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Waitstates[3][0xF] = 2;
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}
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else
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{
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// ARM7
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Waitstates[0][0x0] = 1;
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Waitstates[0][0x2] = 1;
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Waitstates[0][0x3] = 1;
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Waitstates[0][0x4] = 1;
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Waitstates[0][0x6] = 1;
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Waitstates[0][0x8] = 6;
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Waitstates[0][0x9] = 6;
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Waitstates[1][0x0] = 1;
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Waitstates[1][0x2] = 2;
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Waitstates[1][0x3] = 1;
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Waitstates[1][0x4] = 1;
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Waitstates[1][0x6] = 2;
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Waitstates[1][0x8] = 12;
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Waitstates[1][0x9] = 12;
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Waitstates[2][0x0] = 1;
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Waitstates[2][0x2] = 1;
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Waitstates[2][0x3] = 1;
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Waitstates[2][0x4] = 1;
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Waitstates[2][0x6] = 1;
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Waitstates[2][0x8] = 6;
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Waitstates[2][0x9] = 6;
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Waitstates[2][0xA] = 10;
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Waitstates[3][0x0] = 1;
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Waitstates[3][0x2] = 2;
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Waitstates[3][0x3] = 1;
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Waitstates[3][0x4] = 1;
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Waitstates[3][0x6] = 2;
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Waitstates[3][0x8] = 12;
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Waitstates[3][0x9] = 12;
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Waitstates[3][0xA] = 10;
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}
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}
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ARM::~ARM()
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{
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// dorp
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}
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void ARM::Reset()
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{
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Cycles = 0;
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Halted = 0;
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for (int i = 0; i < 16; i++)
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R[i] = 0;
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CPSR = 0x000000D3;
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ExceptionBase = Num ? 0x00000000 : 0xFFFF0000;
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// zorp
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JumpTo(ExceptionBase);
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}
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void ARM::JumpTo(u32 addr, bool restorecpsr)
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{
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if (restorecpsr)
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{
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RestoreCPSR();
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if (CPSR & 0x20) addr |= 0x1;
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else addr &= ~0x1;
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}
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if (addr & 0x1)
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{
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addr &= ~0x1;
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R[15] = addr+2;
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NextInstr[0] = CodeRead16(addr);
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NextInstr[1] = CodeRead16(addr+2);
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CPSR |= 0x20;
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}
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else
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{
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addr &= ~0x3;
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R[15] = addr+4;
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NextInstr[0] = CodeRead32(addr);
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NextInstr[1] = CodeRead32(addr+4);
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CPSR &= ~0x20;
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}
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}
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void ARM::RestoreCPSR()
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{
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u32 oldcpsr = CPSR;
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switch (CPSR & 0x1F)
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{
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case 0x11:
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CPSR = R_FIQ[8];
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break;
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case 0x12:
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CPSR = R_IRQ[2];
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break;
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case 0x13:
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CPSR = R_SVC[2];
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break;
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case 0x17:
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CPSR = R_ABT[2];
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break;
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case 0x1B:
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CPSR = R_UND[2];
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break;
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default:
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printf("!! attempt to restore CPSR under bad mode %02X\n", CPSR&0x1F);
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break;
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}
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UpdateMode(oldcpsr, CPSR);
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}
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void ARM::UpdateMode(u32 oldmode, u32 newmode)
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{
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u32 temp;
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#define SWAP(a, b) temp = a; a = b; b = temp;
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if ((oldmode & 0x1F) == (newmode & 0x1F)) return;
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switch (oldmode & 0x1F)
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{
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case 0x11:
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SWAP(R[8], R_FIQ[0]);
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SWAP(R[9], R_FIQ[1]);
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SWAP(R[10], R_FIQ[2]);
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SWAP(R[11], R_FIQ[3]);
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SWAP(R[12], R_FIQ[4]);
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SWAP(R[13], R_FIQ[5]);
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SWAP(R[14], R_FIQ[6]);
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break;
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case 0x12:
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SWAP(R[13], R_IRQ[0]);
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SWAP(R[14], R_IRQ[1]);
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break;
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case 0x13:
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SWAP(R[13], R_SVC[0]);
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SWAP(R[14], R_SVC[1]);
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break;
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case 0x17:
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SWAP(R[13], R_ABT[0]);
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SWAP(R[14], R_ABT[1]);
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break;
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case 0x1B:
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SWAP(R[13], R_UND[0]);
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SWAP(R[14], R_UND[1]);
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break;
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}
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switch (newmode & 0x1F)
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{
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case 0x11:
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SWAP(R[8], R_FIQ[0]);
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SWAP(R[9], R_FIQ[1]);
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SWAP(R[10], R_FIQ[2]);
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SWAP(R[11], R_FIQ[3]);
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SWAP(R[12], R_FIQ[4]);
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SWAP(R[13], R_FIQ[5]);
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SWAP(R[14], R_FIQ[6]);
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break;
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case 0x12:
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SWAP(R[13], R_IRQ[0]);
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SWAP(R[14], R_IRQ[1]);
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break;
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case 0x13:
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SWAP(R[13], R_SVC[0]);
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SWAP(R[14], R_SVC[1]);
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break;
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case 0x17:
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SWAP(R[13], R_ABT[0]);
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SWAP(R[14], R_ABT[1]);
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break;
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case 0x1B:
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SWAP(R[13], R_UND[0]);
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SWAP(R[14], R_UND[1]);
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break;
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}
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#undef SWAP
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}
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void ARM::TriggerIRQ()
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{
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if (CPSR & 0x80)
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return;
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u32 oldcpsr = CPSR;
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CPSR &= ~0xFF;
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CPSR |= 0xD2;
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UpdateMode(oldcpsr, CPSR);
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R_IRQ[2] = oldcpsr;
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R[14] = R[15] + (oldcpsr & 0x20 ? 2 : 0);
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JumpTo(ExceptionBase + 0x18);
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}
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s32 ARM::Execute()
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{
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if (Halted)
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{
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if (NDS::HaltInterrupted(Num))
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{
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Halted = 0;
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if (NDS::IME[Num]&1)
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TriggerIRQ();
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}
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else
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{
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Cycles = CyclesToRun;
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return Cycles;
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}
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}
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Cycles = 0;
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u32 addr = R[15] - (CPSR&0x20 ? 4:8);
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u32 cpsr = CPSR;
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while (Cycles < CyclesToRun)
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{
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//if(Num==1)printf("%08X %08X\n", R[15] - (CPSR&0x20 ? 4:8), NextInstr);
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if (CPSR & 0x20) // THUMB
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{
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// prefetch
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R[15] += 2;
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CurInstr = NextInstr[0];
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NextInstr[0] = NextInstr[1];
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NextInstr[1] = CodeRead16(R[15]);
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// actually execute
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u32 icode = (CurInstr >> 6);
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ARMInterpreter::THUMBInstrTable[icode](this);
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}
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else
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{
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// prefetch
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R[15] += 4;
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CurInstr = NextInstr[0];
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NextInstr[0] = NextInstr[1];
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NextInstr[1] = CodeRead32(R[15]);
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// actually execute
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if (CheckCondition(CurInstr >> 28))
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{
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u32 icode = ((CurInstr >> 4) & 0xF) | ((CurInstr >> 16) & 0xFF0);
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ARMInterpreter::ARMInstrTable[icode](this);
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}
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else if ((CurInstr & 0xFE000000) == 0xFA000000)
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{
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ARMInterpreter::A_BLX_IMM(this);
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}
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}
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// TODO optimize this shit!!!
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if (Halted)
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{
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if (Halted == 1)
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Cycles = CyclesToRun;
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break;
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}
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if (NDS::HaltInterrupted(Num))
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{
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if (NDS::IME[Num]&1)
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TriggerIRQ();
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}
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// temp. debug cruft
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addr = R[15] - (CPSR&0x20 ? 4:8);
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cpsr = CPSR;
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}
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if (Halted == 2)
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Halted = 0;
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return Cycles;
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}
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