361 lines
9.7 KiB
C++
361 lines
9.7 KiB
C++
#include "ARM.h"
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namespace ARMInterpreter
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{
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// copypasta from ALU. bad
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#define LSL_IMM(x, s) \
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x <<= s;
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#define LSR_IMM(x, s) \
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if (s == 0) s = 32; \
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x >>= s;
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#define ASR_IMM(x, s) \
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if (s == 0) s = 32; \
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x = ((s32)x) >> s;
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#define ROR_IMM(x, s) \
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if (s == 0) \
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{ \
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x = (x >> 1) | ((cpu->CPSR & 0x20000000) << 2); \
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} \
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else \
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{ \
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x = ROR(x, s); \
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}
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#define A_WB_CALC_OFFSET_IMM \
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u32 offset = (cpu->CurInstr & 0xFFF); \
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if (!(cpu->CurInstr & (1<<23))) offset = -offset;
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#define A_WB_CALC_OFFSET_REG(shiftop) \
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u32 offset = cpu->R[cpu->CurInstr & 0xF]; \
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u32 shift = ((cpu->CurInstr>>7)&0x1F); \
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shiftop(offset, shift); \
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if (!(cpu->CurInstr & (1<<23))) offset = -offset;
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#define A_STR \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write32(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
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if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_STR_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write32(addr, cpu->R[(cpu->CurInstr>>12) & 0xF], cpu->CurInstr & (1<<21)); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_STRB \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write8(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
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if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_STRB_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write8(addr, cpu->R[(cpu->CurInstr>>12) & 0xF], cpu->CurInstr & (1<<21)); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDR \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 val = ROR(cpu->Read32(offset), ((offset&0x3)<<3)); \
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if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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if (((cpu->CurInstr>>12) & 0xF) == 15) \
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{ \
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if (cpu->Num==1) val &= ~0x1; \
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cpu->JumpTo(val); \
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return C_S(2) + C_N(2) + C_I(1) + cpu->MemWaitstate(3, offset); \
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} \
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else \
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{ \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset); \
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}
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#define A_LDR_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 val = ROR(cpu->Read32(addr, cpu->CurInstr & (1<<21)), ((addr&0x3)<<3)); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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if (((cpu->CurInstr>>12) & 0xF) == 15) \
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{ \
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if (cpu->Num==1) val &= ~0x1; \
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cpu->JumpTo(val); \
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return C_S(2) + C_N(2) + C_I(1) + cpu->MemWaitstate(3, addr); \
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} \
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else \
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{ \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr); \
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}
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#define A_LDRB \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 val = cpu->Read8(offset); \
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if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset);
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#define A_LDRB_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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u32 val = cpu->Read8(addr, cpu->CurInstr & (1<<21)); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = val; \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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#define A_IMPLEMENT_WB_LDRSTR(x) \
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\
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s32 A_##x##_IMM(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_IMM \
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A_##x \
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} \
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\
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s32 A_##x##_REG_LSL(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(LSL_IMM) \
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A_##x \
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} \
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\
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s32 A_##x##_REG_LSR(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(LSR_IMM) \
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A_##x \
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} \
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\
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s32 A_##x##_REG_ASR(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(ASR_IMM) \
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A_##x \
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} \
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\
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s32 A_##x##_REG_ROR(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(ROR_IMM) \
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A_##x \
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} \
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\
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s32 A_##x##_POST_IMM(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_IMM \
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A_##x##_POST \
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} \
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\
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s32 A_##x##_POST_REG_LSL(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(LSL_IMM) \
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A_##x##_POST \
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} \
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\
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s32 A_##x##_POST_REG_LSR(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(LSR_IMM) \
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A_##x##_POST \
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} \
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\
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s32 A_##x##_POST_REG_ASR(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(ASR_IMM) \
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A_##x##_POST \
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} \
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\
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s32 A_##x##_POST_REG_ROR(ARM* cpu) \
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{ \
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A_WB_CALC_OFFSET_REG(ROR_IMM) \
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A_##x##_POST \
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}
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A_IMPLEMENT_WB_LDRSTR(STR)
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A_IMPLEMENT_WB_LDRSTR(STRB)
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A_IMPLEMENT_WB_LDRSTR(LDR)
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A_IMPLEMENT_WB_LDRSTR(LDRB)
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#define A_HD_CALC_OFFSET_IMM \
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u32 offset = (cpu->CurInstr & 0xF) | ((cpu->CurInstr >> 4) & 0xF0); \
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if (!(cpu->CurInstr & (1<<23))) offset = -offset;
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#define A_HD_CALC_OFFSET_REG \
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u32 offset = cpu->R[cpu->CurInstr & 0xF]; \
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if (!(cpu->CurInstr & (1<<23))) offset = -offset;
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#define A_STRH \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write16(offset, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_STRH_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->Write16(addr, cpu->R[(cpu->CurInstr>>12) & 0xF]); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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// TODO: CHECK LDRD/STRD TIMINGS!!
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#define A_LDRD \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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if (cpu->CurInstr & (1<<21)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->R[r ] = cpu->Read32(offset ); \
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cpu->R[r+1] = cpu->Read32(offset+4); \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, offset);
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#define A_LDRD_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->R[r ] = cpu->Read32(addr ); \
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cpu->R[r+1] = cpu->Read32(addr+4); \
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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#define A_STRD \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->Write32(offset , cpu->R[r ]); \
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cpu->Write32(offset+4, cpu->R[r+1]); \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_STRD_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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u32 r = (cpu->CurInstr>>12) & 0xF; \
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cpu->Write32(offset , cpu->R[r ]); \
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cpu->Write32(offset+4, cpu->R[r+1]); \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDRH \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(offset); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_LDRH_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = cpu->Read16(addr); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDRSB \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s8)cpu->Read8(offset); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_LDRSB_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s8)cpu->Read8(addr); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_LDRSH \
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offset += cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(offset); \
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if (cpu->CurInstr & (1<<24)) cpu->R[(cpu->CurInstr>>16) & 0xF] = offset; \
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return C_N(2) + cpu->MemWaitstate(3, offset);
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#define A_LDRSH_POST \
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u32 addr = cpu->R[(cpu->CurInstr>>16) & 0xF]; \
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cpu->R[(cpu->CurInstr>>12) & 0xF] = (s32)(s16)cpu->Read16(addr); \
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cpu->R[(cpu->CurInstr>>16) & 0xF] += offset; \
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return C_N(2) + cpu->MemWaitstate(3, addr);
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#define A_IMPLEMENT_HD_LDRSTR(x) \
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\
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s32 A_##x##_IMM(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_IMM \
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A_##x \
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} \
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\
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s32 A_##x##_REG(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_REG \
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A_##x \
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} \
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s32 A_##x##_POST_IMM(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_IMM \
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A_##x##_POST \
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} \
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\
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s32 A_##x##_POST_REG(ARM* cpu) \
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{ \
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A_HD_CALC_OFFSET_REG \
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A_##x##_POST \
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}
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A_IMPLEMENT_HD_LDRSTR(STRH)
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A_IMPLEMENT_HD_LDRSTR(LDRD)
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A_IMPLEMENT_HD_LDRSTR(STRD)
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A_IMPLEMENT_HD_LDRSTR(LDRH)
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A_IMPLEMENT_HD_LDRSTR(LDRSB)
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A_IMPLEMENT_HD_LDRSTR(LDRSH)
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// ---- THUMB -----------------------
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s32 T_LDR_PCREL(ARM* cpu)
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{
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u32 addr = cpu->R[15] + ((cpu->CurInstr & 0xFF) << 2);
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cpu->R[(cpu->CurInstr >> 8) & 0x7] = cpu->Read32(addr);
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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}
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s32 T_STR_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->Write32(addr, cpu->R[cpu->CurInstr & 0x7]);
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return C_N(2) + cpu->MemWaitstate(3, addr);
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}
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s32 T_STRB_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->Write8(addr, cpu->R[cpu->CurInstr & 0x7]);
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return C_N(2) + cpu->MemWaitstate(3, addr);
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}
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s32 T_LDR_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->R[cpu->CurInstr & 0x7] = cpu->Read32(addr);
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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}
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s32 T_LDRB_REG(ARM* cpu)
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{
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u32 addr = cpu->R[(cpu->CurInstr >> 3) & 0x7] + cpu->R[(cpu->CurInstr >> 6) & 0x7];
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cpu->R[cpu->CurInstr & 0x7] = cpu->Read8(addr);
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return C_S(1) + C_N(1) + C_I(1) + cpu->MemWaitstate(3, addr);
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}
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}
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