Commit Graph

20 Commits

Author SHA1 Message Date
RSDuck 436b3c4c1d update copyright year and add missing GPL headers 2021-03-12 20:07:40 +01:00
WaluigiWare64 532dc57025
Fix the JIT Code Memory on ARM64 Macs (#916) 2021-02-22 15:13:39 +00:00
RSDuck 1494d7aa24 fix ARM64 again 2021-01-21 15:32:02 +01:00
RSDuck 3b994fe892 fix last commit for ARM64 2021-01-20 18:01:21 +01:00
RSDuck 771dfaca2e JIT: handle STR post with rd == rn
fixes Zelda Four Swords
2021-01-19 23:50:08 +01:00
RSDuck ef75e3cdd1 JIT A64: fixes
also update Switch code for latest libnx
2021-01-05 14:36:50 +01:00
RSDuck 49b5860f0f aligned_alloc instead of memalign
also carry over new Switch changes
2020-12-09 18:58:51 +01:00
Filippo Scognamiglio 45ea1fa990
Fix compilation issues on pedantic cpp compilers. (#783)
* Fix compilation issues on pedantic cpp compilers.

* Avoid using fullblown static function.
2020-10-31 17:40:05 +01:00
RSDuck 9772201345 remove some UB
- savestates used to read a four bytes from a single byte value
- a few unassigned variables
- some other things
- also make the ROR macro an inline function
2020-09-04 20:37:14 +02:00
RSDuck 5903b11bda subtract cycles after checking IRQ and Halt
also switch back to adding to ARM::Cycles instead of subtracting from them
2020-07-27 23:14:39 +02:00
RSDuck 961b4252e2 Make it buildable on aarch64 2020-07-23 19:07:33 +00:00
RSDuck 3827fa562f another try 2020-07-09 00:11:47 +02:00
RSDuck e335a8ca76 first steps in bringing over the JIT refactor/fastmem 2020-06-16 12:11:19 +02:00
RSDuck 0f53a34551 rewrite JIT memory emulation 2020-05-09 00:45:05 +02:00
RSDuck 5d0f244f3c include more information in DataRegion 2020-04-26 13:05:16 +02:00
RSDuck 05962d9798 the time of good commit names is long gone 2020-04-26 13:05:14 +02:00
RSDuck 266fd20ea5 fixup for aarch64 JIT 2020-04-26 13:05:12 +02:00
RSDuck 42d67c8145 fix LDM usermode for aarch64 as well 2020-04-26 13:05:12 +02:00
RSDuck 899cf97c51 apply fixes for aarch64 linux by @nadiaholmquist 2020-04-26 13:05:10 +02:00
RSDuck d6cc7de6c4 move ARM64 JIT backend here 2020-04-26 13:05:09 +02:00