Commit Graph

66 Commits

Author SHA1 Message Date
Jaklyy 3bd6274477 Merge remote-tracking branch 'upstream/master' into interpreter-fixes 2024-11-06 08:27:50 -05:00
Arisotura 7a4255b732 fix LDM bugs 2024-10-29 14:18:57 +01:00
Jaklyy e0e78a2bc8 make empty r-list instructions a bit nicer
pass bools as a single u8 instead and combine thumb and restore cpsr flags since they're mutually exclusive
2024-10-12 11:10:06 -04:00
Jaklyy 7fb18b1155 clean up code 2024-09-23 20:03:58 -04:00
Jaklyy 3b73f21bb7 str r15 is incremented by +2/+4 oop 2024-09-23 16:12:23 -04:00
Jaklyy 8af790beee ldm/str with empty rlist 2024-09-23 15:00:35 -04:00
Jaklyy a0d71135a1 very minor optimization attempt 2024-09-13 07:33:18 -04:00
Jaklyy c5ac682f04 improve data abort handling further 2024-09-12 18:25:54 -04:00
Jaklyy 0003821738 apparently i never tested this 2024-08-28 22:04:22 -04:00
Jaklyy 685c4828a2 try not forgetting about stores lol 2024-08-28 13:45:46 -04:00
Jaklyy be290da23c de-duplicate swp(b) 2024-08-27 17:23:18 -04:00
Jaklyy a9aad74539 implement user mode load/stores 2024-08-26 20:43:27 -04:00
Jaklyy 40e8e8e7bd rework single load/stores to use a shared instruction 2024-08-24 11:46:23 -04:00
Jaklyy ab2a8f128f revert timing tweaks, finish thumb interwork code 2024-08-04 14:54:36 -04:00
Jaklyy 4fcd52ed16 someday i will learn to test things before pushing them 2024-07-11 20:19:25 -04:00
Jaklyy 038ffa3a35 revert the *entire* interlock implemention
too slow, not accurate enough.
we need to do a *lot* more research into the specifics of how this works with all the various aspects of the cpu's timings before we can make a good implementation
2024-07-11 20:08:35 -04:00
Jaklyy 0060958fed Merge remote-tracking branch 'upstream/master' into jump-after-writeback 2024-07-03 15:26:58 -04:00
Jaklyy c5b035a973 SWP and SWPB use the same behavior as STR on the ARM9 2024-06-25 11:20:01 -04:00
Jaklyy 541e1e6388 proper timings for ldr/str 2024-06-25 09:08:11 -04:00
Jaklyy c5258d6377 verify interlocks for alu and load/store
remove some checks for interlock that im pretty sure can't trigger
2024-06-17 18:07:53 -04:00
Jaklyy f00f1f6ca4 im smart 2024-06-16 20:50:42 -04:00
Jaklyy 5b37ca70d1 implement correct/guess interlocks for remaining instructions 2024-06-16 20:47:01 -04:00
Jaklyy a973c0bf5b initial implementation of interlock cycles 2024-06-15 16:07:36 -04:00
Arisotura 8fc403cdad update copyright headers 2024-06-15 17:01:19 +02:00
Jaklyy 5a174a2ce3 track interlock cycles for load instructions 2024-06-14 00:51:55 -04:00
Jaklyy 42218106b0 verify writable msr bits 2024-06-11 10:30:30 -04:00
Jaklyy 048b0b8878 swp/swpb jumps work on the arm 7? 2024-06-10 18:03:56 -04:00
Jaklyy 3ddccde5b9 verified
also remove no longer needed variable
2024-06-10 13:23:18 -04:00
Jaklyy ca04710deb ldrd is just ldm 2024-06-09 22:31:10 -04:00
Jaklyy ae0824fdd3 it all makes sense now... 2024-06-09 19:10:43 -04:00
Jaklyy b846c6f100 remove out of date comments 2024-06-08 22:17:07 -04:00
Jaklyy 849d4e51ac imma be real, i have no idea what is going on here 2024-06-08 22:12:44 -04:00
Jaklyy 659763f903 clarification 2024-06-08 16:15:02 -04:00
Jaklyy 0c887202e7 fix some more instructions? 2024-06-08 10:40:23 -04:00
Jaklyy 73507621f5 idk why it took me two tries to get these instructions to work properly 2024-06-07 23:50:31 -04:00
Jaklyy 2b0ed459e1 fully implement r15 stores being +12 of addr 2024-06-07 23:46:49 -04:00
Jaklyy bd3611b51d unaligned registers with strd/ldrd raise an exception 2024-06-07 20:43:02 -04:00
Jaklyy 8bc7e4591c thumb ldmia/pop data aborts 2024-06-06 19:05:28 -04:00
Jaklyy d6cd189455 rework data abort handling for ldm/stm; implement thumb stmia+push 2024-06-06 18:58:43 -04:00
Jaklyy 13ae96b4e3 simple thumb instructions (untested but probably right) 2024-06-05 14:32:12 -04:00
Jaklyy 7c3108e20f handle swp instruction aborts 2024-06-05 14:31:44 -04:00
Jaklyy 1871c48849 fix double data aborts with strd 2024-06-05 10:28:51 -04:00
Jaklyy 317a8c61e5 data abort handling for (almost) all (arm) instructions
full list: strb, ldrb, strh, ldrd, strd, ldrh, ldrsb, ldrsh
2024-06-05 00:14:14 -04:00
Jaklyy 1e8194e367 fix ldr and str 2024-06-04 19:06:54 -04:00
Jaklyy c2a57b79a0 fix stmd(a/b) writeback 2024-06-02 22:41:01 -04:00
Jaklyy 5e760a1536 slightly cleaner code 2024-06-02 19:34:29 -04:00
Jaklyy b5c1ee33fb implement stm 2024-06-02 10:33:29 -04:00
Jaklyy 63d4b78733 improve implementation 2024-06-02 10:13:50 -04:00
Jaklyy 960f063eaa improve data aborts for ldm 2024-06-02 00:11:01 -04:00
Jaklyy 065573f316 fix writebacks overwriting registers swapped with spsr
fixes gbarunner3
2024-05-31 18:09:45 -04:00