ab2a8f128f
revert timing tweaks, finish thumb interwork code
2024-08-04 14:54:36 -04:00
4fcd52ed16
someday i will learn to test things before pushing them
2024-07-11 20:19:25 -04:00
038ffa3a35
revert the *entire* interlock implemention
...
too slow, not accurate enough.
we need to do a *lot* more research into the specifics of how this works with all the various aspects of the cpu's timings before we can make a good implementation
2024-07-11 20:08:35 -04:00
0060958fed
Merge remote-tracking branch 'upstream/master' into jump-after-writeback
2024-07-03 15:26:58 -04:00
c5b035a973
SWP and SWPB use the same behavior as STR on the ARM9
2024-06-25 11:20:01 -04:00
541e1e6388
proper timings for ldr/str
2024-06-25 09:08:11 -04:00
c5258d6377
verify interlocks for alu and load/store
...
remove some checks for interlock that im pretty sure can't trigger
2024-06-17 18:07:53 -04:00
f00f1f6ca4
im smart
2024-06-16 20:50:42 -04:00
5b37ca70d1
implement correct/guess interlocks for remaining instructions
2024-06-16 20:47:01 -04:00
a973c0bf5b
initial implementation of interlock cycles
2024-06-15 16:07:36 -04:00
8fc403cdad
update copyright headers
2024-06-15 17:01:19 +02:00
5a174a2ce3
track interlock cycles for load instructions
2024-06-14 00:51:55 -04:00
42218106b0
verify writable msr bits
2024-06-11 10:30:30 -04:00
048b0b8878
swp/swpb jumps work on the arm 7?
2024-06-10 18:03:56 -04:00
3ddccde5b9
verified
...
also remove no longer needed variable
2024-06-10 13:23:18 -04:00
ca04710deb
ldrd is just ldm
2024-06-09 22:31:10 -04:00
ae0824fdd3
it all makes sense now...
2024-06-09 19:10:43 -04:00
b846c6f100
remove out of date comments
2024-06-08 22:17:07 -04:00
849d4e51ac
imma be real, i have no idea what is going on here
2024-06-08 22:12:44 -04:00
659763f903
clarification
2024-06-08 16:15:02 -04:00
0c887202e7
fix some more instructions?
2024-06-08 10:40:23 -04:00
73507621f5
idk why it took me two tries to get these instructions to work properly
2024-06-07 23:50:31 -04:00
2b0ed459e1
fully implement r15 stores being +12 of addr
2024-06-07 23:46:49 -04:00
bd3611b51d
unaligned registers with strd/ldrd raise an exception
2024-06-07 20:43:02 -04:00
8bc7e4591c
thumb ldmia/pop data aborts
2024-06-06 19:05:28 -04:00
d6cd189455
rework data abort handling for ldm/stm; implement thumb stmia+push
2024-06-06 18:58:43 -04:00
13ae96b4e3
simple thumb instructions (untested but probably right)
2024-06-05 14:32:12 -04:00
7c3108e20f
handle swp instruction aborts
2024-06-05 14:31:44 -04:00
1871c48849
fix double data aborts with strd
2024-06-05 10:28:51 -04:00
317a8c61e5
data abort handling for (almost) all (arm) instructions
...
full list: strb, ldrb, strh, ldrd, strd, ldrh, ldrsb, ldrsh
2024-06-05 00:14:14 -04:00
1e8194e367
fix ldr and str
2024-06-04 19:06:54 -04:00
c2a57b79a0
fix stmd(a/b) writeback
2024-06-02 22:41:01 -04:00
5e760a1536
slightly cleaner code
2024-06-02 19:34:29 -04:00
b5c1ee33fb
implement stm
2024-06-02 10:33:29 -04:00
63d4b78733
improve implementation
2024-06-02 10:13:50 -04:00
960f063eaa
improve data aborts for ldm
2024-06-02 00:11:01 -04:00
065573f316
fix writebacks overwriting registers swapped with spsr
...
fixes gbarunner3
2024-05-31 18:09:45 -04:00
346dd4006e
Move all core types into namespaces ( #1886 )
...
* Reorganize namespaces
- Most types are now moved into the `melonDS` namespace
- Only good chance to do this for a while, since a big refactor is next
* Fix the build
2023-11-25 18:32:09 +01:00
ac38faef14
update copyright years
2023-11-04 00:21:46 +01:00
3d58a338a1
store pc+12 when storing r15
2023-10-22 15:21:03 +02:00
35cc79787d
update copyright headers
2022-01-09 02:15:50 +01:00
e121953c9a
more complete (and accurate) CP15 setup for direct boot
2021-10-28 21:15:12 +02:00
436b3c4c1d
update copyright year and add missing GPL headers
2021-03-12 20:07:40 +01:00
83f8e11bc1
update copyright years
2020-02-14 20:18:08 +01:00
b0efde8bf7
also, update copyright name
2019-01-22 15:58:29 +01:00
694d6cafa2
fix STRD_POST (dumbest copypaste bug of the year)
...
fixes #276
2018-12-18 01:56:21 +01:00
29bca33bc6
take it somewhere.
...
still need to speed it up a tad.
2018-12-09 01:17:05 +01:00
172fb4876a
begin work on general timing renovation. way shitty because it behaves as if caches were off, so everything will be slow as shit.
2018-12-04 17:54:10 +01:00
fea7955675
fixor copyright years.
2018-09-15 02:32:13 +02:00
49f8aec656
fix some shit
2017-06-13 17:44:35 +02:00
Jaklyy