Removed Thumb Check on CP15 Access restriction as MCR/MRC are not present in thumb
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parent
02d6fbacf6
commit
f9a831e446
105
src/CP15.cpp
105
src/CP15.cpp
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@ -928,10 +928,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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ICacheInvalidateByAddr(val);
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//Halt(255);
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@ -940,10 +937,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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// Cache invalidat by line number and set number
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@ -959,10 +953,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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DCacheInvalidateAll();
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//printf("inval data cache %08X\n", val);
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@ -971,10 +962,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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DCacheInvalidateByAddr(val);
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//printf("inval data cache SI\n");
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@ -983,10 +971,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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// Cache invalidat by line number and set number
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@ -1007,10 +992,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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//Log(LogLevel::Debug,"clean data cache\n");
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DCacheClearAll();
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@ -1019,10 +1001,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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//Log(LogLevel::Debug,"clean data cache MVA\n");
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DCacheClearByAddr(val);
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@ -1032,10 +1011,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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// Cache invalidat by line number and set number
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@ -1048,10 +1024,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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// Test and clean (optional)
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// Is not present on the NDS/DSi
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@ -1067,10 +1040,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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// we force a fill by looking up the value from cache
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// if it wasn't cached yet, it will be loaded into cache
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@ -1082,10 +1052,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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DCacheClearAll();
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DCacheInvalidateAll();
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@ -1095,10 +1062,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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DCacheClearByAddr(val);
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DCacheInvalidateByAddr(val);
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@ -1108,10 +1072,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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// Cache invalidat by line number and set number
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@ -1126,10 +1087,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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// Cache Lockdown - Format B
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// Bit 31: Lock bit
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@ -1143,10 +1101,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// requires priv mode or causes UNKNOWN INSTRUCTION exception
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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// Cache Lockdown - Format B
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// Bit 31: Lock bit
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@ -1175,10 +1130,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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case 0xF00:
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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if (((id >> 12) & 0x0f) == 0x03)
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@ -1187,10 +1139,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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CP15BISTTestStateRegister = val;
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else
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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}
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}
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@ -1200,10 +1149,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// instruction cache Tag register
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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uint8_t segment = (CacheDebugRegisterIndex >> (32-ICACHE_SETS_LOG2)) & (ICACHE_SETS-1);
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@ -1216,10 +1162,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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// data cache Tag register
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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uint8_t segment = (CacheDebugRegisterIndex >> (32-DCACHE_SETS_LOG2)) & (DCACHE_SETS-1);
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@ -1233,10 +1176,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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//printf("cache debug instruction cache %08X\n", val);
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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uint8_t segment = (CacheDebugRegisterIndex >> (32-ICACHE_SETS_LOG2)) & (ICACHE_SETS-1);
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@ -1250,10 +1190,7 @@ void ARMv5::CP15Write(u32 id, u32 val)
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//printf("cache debug data cache %08X\n", val);
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if (PU_Map != PU_PrivMap)
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{
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if (CPSR & 0x20) // THUMB
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return ARMInterpreter::T_UNK(this);
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else
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return ARMInterpreter::A_UNK(this);
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return ARMInterpreter::A_UNK(this);
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} else
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{
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uint8_t segment = (CacheDebugRegisterIndex >> (32-DCACHE_SETS_LOG2)) & (DCACHE_SETS-1);
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