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improve interlock emulation 

add cycles to the instruction execution time rather than the timestamp directly.
This commit is contained in:
Jaklyy 2024-07-04 12:58:58 -04:00
parent bd1665c1d3
commit ea429a1b8d
2 changed files with 11 additions and 8 deletions
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9
src/ARM.cpp
View File

@ -696,6 +696,7 @@ void ARMv5::Execute()
NDS.ARM9Timestamp += Cycles; NDS.ARM9Timestamp += Cycles;
Cycles = 0; Cycles = 0;
CyclesILed = 0;
} }
if (Halted == 2) if (Halted == 2)
@ -1262,7 +1263,7 @@ bool ARMv4::DataWrite32S(u32 addr, u32 val, bool dataabort)
void ARMv5::AddCycles_CD_STR() void ARMv5::AddCycles_CD_STR()
{ {
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles; s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles; s32 numD = DataCycles + CyclesILed;
s32 early; s32 early;
if (DataRegion == Mem9_ITCM) if (DataRegion == Mem9_ITCM)
@ -1287,7 +1288,7 @@ void ARMv5::AddCycles_CD_STR()
void ARMv5::AddCycles_CD_STM() void ARMv5::AddCycles_CD_STM()
{ {
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles; s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles; s32 numD = DataCycles + CyclesILed;
s32 early; s32 early;
if (DataRegion == Mem9_ITCM) if (DataRegion == Mem9_ITCM)
@ -1313,7 +1314,7 @@ void ARMv5::AddCycles_CDI_LDR()
{ {
// LDR cycles. ARM9 seems to skip the internal cycle here. // LDR cycles. ARM9 seems to skip the internal cycle here.
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles; s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles; s32 numD = DataCycles + CyclesILed;
// if a 32 bit bus, start 2 cycles early; else, start 4 cycles early // if a 32 bit bus, start 2 cycles early; else, start 4 cycles early
s32 early; s32 early;
@ -1340,7 +1341,7 @@ void ARMv5::AddCycles_CDI_LDM()
{ {
// LDM cycles. ARM9 seems to skip the internal cycle here. // LDM cycles. ARM9 seems to skip the internal cycle here.
s32 numC = (R[15] & 0x2) ? 0 : CodeCycles; s32 numC = (R[15] & 0x2) ? 0 : CodeCycles;
s32 numD = DataCycles; s32 numD = DataCycles + CyclesILed;
// if a 32 bit bus, start 2 cycles early; else, start 4 cycles early // if a 32 bit bus, start 2 cycles early; else, start 4 cycles early
s32 early; s32 early;

10
src/ARM.h
View File

@ -30,7 +30,7 @@
#include "debug/GdbStub.h" #include "debug/GdbStub.h"
#endif #endif
//#define INTERLOCK #define INTERLOCK
namespace melonDS namespace melonDS
{ {
@ -318,14 +318,14 @@ public:
{ {
// code only. always nonseq 32-bit for ARM9. // code only. always nonseq 32-bit for ARM9.
s32 numC = CodeCycles; s32 numC = CodeCycles;
Cycles += numC; Cycles += std::max(numC, CyclesILed + 1);
} }
void AddCycles_CI(s32 numI) override void AddCycles_CI(s32 numI) override
{ {
// code+internal // code+internal
s32 numC = CodeCycles; s32 numC = CodeCycles;
numI += 1; numI += 1 + CyclesILed;
Cycles += std::max(numC, numI); Cycles += std::max(numC, numI);
} }
@ -340,7 +340,7 @@ public:
inline u32 GetReg(const u32 reg, const u32 delay = 0) override inline u32 GetReg(const u32 reg, const u32 delay = 0) override
{ {
if (InterlockTimestamp[reg] > (Timestamp() + delay)) if (InterlockTimestamp[reg] > (Timestamp() + delay))
Timestamp() = InterlockTimestamp[reg] - delay; CyclesILed = InterlockTimestamp[reg] - (Timestamp() + delay);
return R[reg]; return R[reg];
} }
@ -417,6 +417,8 @@ public:
bool (*GetMemRegion)(u32 addr, bool write, MemRegion* region); bool (*GetMemRegion)(u32 addr, bool write, MemRegion* region);
s32 CyclesILed;
#ifdef GDBSTUB_ENABLED #ifdef GDBSTUB_ENABLED
u32 ReadMem(u32 addr, int size) override; u32 ReadMem(u32 addr, int size) override;
void WriteMem(u32 addr, int size, u32 v) override; void WriteMem(u32 addr, int size, u32 v) override;