for some reason tabs and spaces were mixed

This commit is contained in:
RSDuck 2020-07-23 17:43:25 +02:00
parent 2f9a6b7c03
commit e63bd7e38c
5 changed files with 1805 additions and 1805 deletions

File diff suppressed because it is too large Load Diff

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@ -16,10 +16,10 @@ namespace ARMJIT
enum enum
{ {
branch_IdleBranch = 1 << 0, branch_IdleBranch = 1 << 0,
branch_FollowCondTaken = 1 << 1, branch_FollowCondTaken = 1 << 1,
branch_FollowCondNotTaken = 1 << 2, branch_FollowCondNotTaken = 1 << 2,
branch_StaticTarget = 1 << 3, branch_StaticTarget = 1 << 3,
}; };
struct FetchedInstr struct FetchedInstr
@ -39,155 +39,155 @@ struct FetchedInstr
return Instr >> 28; return Instr >> 28;
} }
u8 BranchFlags; u8 BranchFlags;
u8 SetFlags; u8 SetFlags;
u32 Instr; u32 Instr;
u32 Addr; u32 Addr;
u8 DataCycles; u8 DataCycles;
u16 CodeCycles; u16 CodeCycles;
u32 DataRegion; u32 DataRegion;
ARMInstrInfo::Info Info; ARMInstrInfo::Info Info;
}; };
/* /*
TinyVector TinyVector
- because reinventing the wheel is the best! - because reinventing the wheel is the best!
- meant to be used very often, with not so many elements - meant to be used very often, with not so many elements
max 1 << 16 elements max 1 << 16 elements
- doesn't allocate while no elements are inserted - doesn't allocate while no elements are inserted
- not stl confirmant of course - not stl confirmant of course
- probably only works with POD types - probably only works with POD types
- remove operations don't preserve order, but O(1)! - remove operations don't preserve order, but O(1)!
*/ */
template <typename T> template <typename T>
struct __attribute__((packed)) TinyVector struct __attribute__((packed)) TinyVector
{ {
T* Data = NULL; T* Data = NULL;
u16 Capacity = 0; u16 Capacity = 0;
u16 Length = 0; u16 Length = 0;
~TinyVector() ~TinyVector()
{ {
delete[] Data; delete[] Data;
} }
void MakeCapacity(u32 capacity) void MakeCapacity(u32 capacity)
{ {
assert(capacity <= UINT16_MAX); assert(capacity <= UINT16_MAX);
assert(capacity > Capacity); assert(capacity > Capacity);
T* newMem = new T[capacity]; T* newMem = new T[capacity];
if (Data != NULL) if (Data != NULL)
memcpy(newMem, Data, sizeof(T) * Length); memcpy(newMem, Data, sizeof(T) * Length);
T* oldData = Data; T* oldData = Data;
Data = newMem; Data = newMem;
if (oldData != NULL) if (oldData != NULL)
delete[] oldData; delete[] oldData;
Capacity = capacity; Capacity = capacity;
} }
void SetLength(u16 length) void SetLength(u16 length)
{ {
if (Capacity < length) if (Capacity < length)
MakeCapacity(length); MakeCapacity(length);
Length = length; Length = length;
} }
void Clear() void Clear()
{ {
Length = 0; Length = 0;
} }
void Add(T element) void Add(T element)
{ {
assert(Length + 1 <= UINT16_MAX); assert(Length + 1 <= UINT16_MAX);
if (Length + 1 > Capacity) if (Length + 1 > Capacity)
MakeCapacity(((Capacity + 4) * 3) / 2); MakeCapacity(((Capacity + 4) * 3) / 2);
Data[Length++] = element; Data[Length++] = element;
} }
void Remove(int index) void Remove(int index)
{ {
assert(index >= 0 && index < Length); assert(index >= 0 && index < Length);
Length--; Length--;
Data[index] = Data[Length]; Data[index] = Data[Length];
/*for (int i = index; i < Length; i++) /*for (int i = index; i < Length; i++)
Data[i] = Data[i + 1];*/ Data[i] = Data[i + 1];*/
} }
int Find(T needle) int Find(T needle)
{ {
for (int i = 0; i < Length; i++) for (int i = 0; i < Length; i++)
{ {
if (Data[i] == needle) if (Data[i] == needle)
return i; return i;
} }
return -1; return -1;
} }
bool RemoveByValue(T needle) bool RemoveByValue(T needle)
{ {
for (int i = 0; i < Length; i++) for (int i = 0; i < Length; i++)
{ {
if (Data[i] == needle) if (Data[i] == needle)
{ {
Remove(i); Remove(i);
return true; return true;
} }
} }
return false; return false;
} }
T& operator[](int index) T& operator[](int index)
{ {
assert(index >= 0 && index < Length); assert(index >= 0 && index < Length);
return Data[index]; return Data[index];
} }
}; };
class JitBlock class JitBlock
{ {
public: public:
JitBlock(u32 num, u32 literalHash, u32 numAddresses, u32 numLiterals) JitBlock(u32 num, u32 literalHash, u32 numAddresses, u32 numLiterals)
{ {
Num = num; Num = num;
NumAddresses = numAddresses; NumAddresses = numAddresses;
NumLiterals = numLiterals; NumLiterals = numLiterals;
Data.SetLength(numAddresses * 2 + numLiterals); Data.SetLength(numAddresses * 2 + numLiterals);
} }
u32 StartAddr; u32 StartAddr;
u32 StartAddrLocal; u32 StartAddrLocal;
u32 InstrHash, LiteralHash; u32 InstrHash, LiteralHash;
u8 Num; u8 Num;
u16 NumAddresses; u16 NumAddresses;
u16 NumLiterals; u16 NumLiterals;
JitBlockEntry EntryPoint; JitBlockEntry EntryPoint;
u32* AddressRanges() u32* AddressRanges()
{ return &Data[0]; } { return &Data[0]; }
u32* AddressMasks() u32* AddressMasks()
{ return &Data[NumAddresses]; } { return &Data[NumAddresses]; }
u32* Literals() u32* Literals()
{ return &Data[NumAddresses * 2]; } { return &Data[NumAddresses * 2]; }
private: private:
TinyVector<u32> Data; TinyVector<u32> Data;
}; };
// size should be 16 bytes because I'm to lazy to use mul and whatnot // size should be 16 bytes because I'm to lazy to use mul and whatnot
struct __attribute__((packed)) AddressRange struct __attribute__((packed)) AddressRange
{ {
TinyVector<JitBlock*> Blocks; TinyVector<JitBlock*> Blocks;
u32 Code; u32 Code;
}; };
@ -201,12 +201,12 @@ extern AddressRange* const CodeMemRegions[ARMJIT_Memory::memregions_Count];
inline bool PageContainsCode(AddressRange* range) inline bool PageContainsCode(AddressRange* range)
{ {
for (int i = 0; i < 8; i++) for (int i = 0; i < 8; i++)
{ {
if (range[i].Blocks.Length > 0) if (range[i].Blocks.Length > 0)
return true; return true;
} }
return false; return false;
} }
u32 LocaliseCodeAddress(u32 num, u32 addr); u32 LocaliseCodeAddress(u32 num, u32 addr);

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@ -18,28 +18,28 @@ void Reset();
enum enum
{ {
memregion_Other = 0, memregion_Other = 0,
memregion_ITCM, memregion_ITCM,
memregion_DTCM, memregion_DTCM,
memregion_BIOS9, memregion_BIOS9,
memregion_MainRAM, memregion_MainRAM,
memregion_SharedWRAM, memregion_SharedWRAM,
memregion_IO9, memregion_IO9,
memregion_VRAM, memregion_VRAM,
memregion_BIOS7, memregion_BIOS7,
memregion_WRAM7, memregion_WRAM7,
memregion_IO7, memregion_IO7,
memregion_Wifi, memregion_Wifi,
memregion_VWRAM, memregion_VWRAM,
// DSi // DSi
memregion_BIOS9DSi, memregion_BIOS9DSi,
memregion_BIOS7DSi, memregion_BIOS7DSi,
memregion_NewSharedWRAM_A, memregion_NewSharedWRAM_A,
memregion_NewSharedWRAM_B, memregion_NewSharedWRAM_B,
memregion_NewSharedWRAM_C, memregion_NewSharedWRAM_C,
memregions_Count memregions_Count
}; };
int ClassifyAddress9(u32 addr); int ClassifyAddress9(u32 addr);

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@ -18,8 +18,8 @@ public:
RegisterCache() RegisterCache()
{} {}
RegisterCache(T* compiler, FetchedInstr instrs[], int instrsCount, bool pcAllocatableAsSrc = false) RegisterCache(T* compiler, FetchedInstr instrs[], int instrsCount, bool pcAllocatableAsSrc = false)
: Compiler(compiler), Instrs(instrs), InstrsCount(instrsCount) : Compiler(compiler), Instrs(instrs), InstrsCount(instrsCount)
{ {
for (int i = 0; i < 16; i++) for (int i = 0; i < 16; i++)
Mapping[i] = (Reg)-1; Mapping[i] = (Reg)-1;
@ -95,7 +95,7 @@ public:
LiteralsLoaded = 0; LiteralsLoaded = 0;
} }
void Prepare(bool thumb, int i) void Prepare(bool thumb, int i)
{ {
FetchedInstr instr = Instrs[i]; FetchedInstr instr = Instrs[i];
@ -175,23 +175,23 @@ public:
DirtyRegs |= (LoadedRegs & instr.Info.DstRegs) & ~(1 << 15); DirtyRegs |= (LoadedRegs & instr.Info.DstRegs) & ~(1 << 15);
} }
static const Reg NativeRegAllocOrder[]; static const Reg NativeRegAllocOrder[];
static const int NativeRegsAvailable; static const int NativeRegsAvailable;
Reg Mapping[16]; Reg Mapping[16];
u32 LiteralValues[16]; u32 LiteralValues[16];
u16 LiteralsLoaded = 0; u16 LiteralsLoaded = 0;
u32 NativeRegsUsed = 0; u32 NativeRegsUsed = 0;
u16 LoadedRegs = 0; u16 LoadedRegs = 0;
u16 DirtyRegs = 0; u16 DirtyRegs = 0;
u16 PCAllocatableAsSrc = 0; u16 PCAllocatableAsSrc = 0;
T* Compiler; T* Compiler;
FetchedInstr* Instrs; FetchedInstr* Instrs;
int InstrsCount; int InstrsCount;
}; };
} }