start decoupling the cart classes from the global NDSCart state
This commit is contained in:
Arisotura
parent
02620026dd
commit
e423c234e3
194
src/NDSCart.cpp
194
src/NDSCart.cpp
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@ -623,10 +623,14 @@ void ApplyModcrypt(u32 addr, u32 len, u8* iv)
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}
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CartCommon::CartCommon(u8* rom, u32 len)
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CartCommon::CartCommon(u8* rom, u32 len, u32 chipid)
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{
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ROM = rom;
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ROMLength = len;
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ChipID = chipid;
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u8 unitcode = ROM[0x12];
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IsDSi = (unitcode & 0x02) != 0;
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}
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CartCommon::~CartCommon()
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@ -654,47 +658,44 @@ void CartCommon::FlushSRAMFile()
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{
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}
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void CartCommon::ROMCommandStart(u8* cmd)
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int CartCommon::ROMCommandStart(u8* cmd, u8* data, u32 len)
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{
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switch (cmd[0])
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{
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case 0x9F:
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memset(TransferData, 0xFF, TransferLen);
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break;
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memset(data, 0xFF, len);
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return 0;
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case 0x00:
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memset(TransferData, 0, TransferLen);
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if (TransferLen > 0x1000)
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memset(data, 0, len);
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if (len > 0x1000)
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{
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ReadROM(0, 0x1000, 0);
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for (u32 pos = 0x1000; pos < TransferLen; pos += 0x1000)
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memcpy(TransferData+pos, TransferData, 0x1000);
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ReadROM(0, 0x1000, data, 0);
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for (u32 pos = 0x1000; pos < len; pos += 0x1000)
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memcpy(data+pos, data, 0x1000);
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}
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else
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ReadROM(0, TransferLen, 0);
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break;
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ReadROM(0, len, data, 0);
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return 0;
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case 0x90:
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case 0xB8:
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for (u32 pos = 0; pos < TransferLen; pos += 4)
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*(u32*)&TransferData[pos] = CartID;
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break;
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for (u32 pos = 0; pos < len; pos += 4)
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*(u32*)&data[pos] = ChipID;
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return 0;
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case 0x3C:
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if (CartInserted)
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{
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CmdEncMode = 1;
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Key1_InitKeycode(false, *(u32*)&CartROM[0xC], 2, 2);
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}
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break;
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CmdEncMode = 1;
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Key1_InitKeycode(false, *(u32*)&ROM[0xC], 2, 2);
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return 0;
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case 0x3D:
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if (CartInserted && CartIsDSi)
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if (IsDSi)
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{
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CmdEncMode = 11;
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Key1_InitKeycode(true, *(u32*)&CartROM[0xC], 1, 2);
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Key1_InitKeycode(true, *(u32*)&ROM[0xC], 1, 2);
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}
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break;
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return 0;
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default:
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if (CmdEncMode == 1 || CmdEncMode == 11)
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@ -703,12 +704,12 @@ void CartCommon::ROMCommandStart(u8* cmd)
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{
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case 0x40:
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DataEncMode = 2;
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break;
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return 0;
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case 0x10:
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for (u32 pos = 0; pos < TransferLen; pos += 4)
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*(u32*)&TransferData[pos] = CartID;
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break;
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for (u32 pos = 0; pos < len; pos += 4)
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*(u32*)&data[pos] = ChipID;
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return 0;
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case 0x20:
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{
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@ -721,20 +722,20 @@ void CartCommon::ROMCommandStart(u8* cmd)
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addr -= 0x4000;
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addr += arm9i_base;
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}
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ReadROM(addr, 0x1000, 0);
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ReadROM(addr, 0x1000, data, 0);
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}
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break;
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return 0;
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case 0xA0:
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CmdEncMode = 2;
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break;
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return 0;
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}
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}
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break;
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return 0;
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}
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}
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void CartCommon::ROMCommandFinish(u8* cmd)
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void CartCommon::ROMCommandFinish(u8* cmd, u8* data, u32 len)
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{
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}
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@ -743,17 +744,17 @@ u8 CartCommon::SPIWrite(u8 val, u32 pos, bool last)
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return 0xFF;
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}
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void CartCommon::ReadROM(u32 addr, u32 len, u32 offset)
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void CartCommon::ReadROM(u32 addr, u32 len, u8* data, u32 offset)
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{
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if (addr >= ROMLength) return;
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if ((addr+len) > ROMLength)
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len = ROMLength - addr;
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memcpy(TransferData+offset, ROM+addr, len);
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memcpy(data+offset, ROM+addr, len);
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}
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CartRetail::CartRetail(u8* rom, u32 len) : CartCommon(rom, len)
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CartRetail::CartRetail(u8* rom, u32 len, u32 chipid) : CartCommon(rom, len, chipid)
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{
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SRAM = nullptr;
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}
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@ -849,28 +850,28 @@ void CartRetail::FlushSRAMFile()
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NDSCart_SRAMManager::RequestFlush();
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}
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void CartRetail::ROMCommandStart(u8* cmd)
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int CartRetail::ROMCommandStart(u8* cmd, u8* data, u32 len)
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{
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switch (cmd[0])
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{
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case 0xB7:
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{
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u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
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memset(TransferData, 0, TransferLen);
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memset(data, 0, len);
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if (((addr + TransferLen - 1) >> 12) != (addr >> 12))
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if (((addr + len - 1) >> 12) != (addr >> 12))
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{
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u32 len1 = 0x1000 - (addr & 0xFFF);
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ReadROM_B7(addr, len1, 0);
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ReadROM_B7(addr+len1, TransferLen-len1, len1);
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ReadROM_B7(addr, len1, data, 0);
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ReadROM_B7(addr+len1, len-len1, data, len1);
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}
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else
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ReadROM_B7(addr, TransferLen, 0);
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ReadROM_B7(addr, len, data, 0);
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}
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break;
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return 0;
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default:
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return CartCommon::ROMCommandStart(cmd);
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return CartCommon::ROMCommandStart(cmd, data, len);
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}
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}
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@ -910,7 +911,7 @@ u8 CartRetail::SPIWrite(u8 val, u32 pos, bool last)
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//return ret;
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}
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void CartRetail::ReadROM_B7(u32 addr, u32 len, u32 offset)
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void CartRetail::ReadROM_B7(u32 addr, u32 len, u8* data, u32 offset)
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{
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addr &= (ROMLength-1);
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@ -921,7 +922,7 @@ void CartRetail::ReadROM_B7(u32 addr, u32 len, u32 offset)
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// also protect DSi region if not unlocked
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// and other security shenanigans
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memcpy(TransferData+offset, ROM+addr, len);
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memcpy(data+offset, ROM+addr, len);
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}
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u8 CartRetail::SRAMWrite_EEPROMTiny(u8 val, u32 pos, bool last)
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@ -1147,9 +1148,8 @@ u8 CartRetail::SRAMWrite_FLASH(u8 val, u32 pos, bool last)
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}
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CartRetailNAND::CartRetailNAND(u8* rom, u32 len) : CartRetail(rom, len)
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CartRetailNAND::CartRetailNAND(u8* rom, u32 len, u32 chipid) : CartRetail(rom, len, chipid)
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{
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printf("ohai I am a NAND cart\n");
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}
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CartRetailNAND::~CartRetailNAND()
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@ -1191,7 +1191,7 @@ void CartRetailNAND::LoadSave(const char* path, u32 type)
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}
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}
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void CartRetailNAND::ROMCommandStart(u8* cmd)
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int CartRetailNAND::ROMCommandStart(u8* cmd, u8* data, u32 len)
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{
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// ROM header 94/96 = save addr start / 0x20000
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@ -1199,11 +1199,11 @@ void CartRetailNAND::ROMCommandStart(u8* cmd)
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{
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case 0x85: // write enable?
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SRAMStatus |= (1<<4);
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break;
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return 0;
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case 0x8B: // revert to ROM read mode
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SRAMReadWindow = 0;
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break;
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return 0;
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case 0x94: // return ID data
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{
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@ -1219,12 +1219,12 @@ void CartRetailNAND::ROMCommandStart(u8* cmd)
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if (SRAMLength) memcpy(&iddata[0x18], &SRAM[SRAMLength - 0x800], 16);
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memset(TransferData, 0, TransferLen);
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memcpy(TransferData, iddata, std::min(TransferLen, 0x30u));
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memset(data, 0, len);
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memcpy(data, iddata, std::min(len, 0x30u));
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}
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break;
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return 0;
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case 0xB2: // set window for reading SRAM
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case 0xB2: // set window for accessing SRAM
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{
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u32 addr = (cmd[1]<<24) | ((cmd[2]&0xFE)<<16);
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@ -1234,7 +1234,7 @@ void CartRetailNAND::ROMCommandStart(u8* cmd)
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SRAMReadWindow = addr;
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}
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break;
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return 0;
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case 0xB7:
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{
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@ -1242,20 +1242,20 @@ void CartRetailNAND::ROMCommandStart(u8* cmd)
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if (SRAMReadWindow == 0)
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{
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memset(TransferData, 0, TransferLen);
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memset(data, 0, len);
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if (((addr + TransferLen - 1) >> 12) != (addr >> 12))
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if (((addr + len - 1) >> 12) != (addr >> 12))
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{
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u32 len1 = 0x1000 - (addr & 0xFFF);
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ReadROM_B7(addr, len1, 0);
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ReadROM_B7(addr+len1, TransferLen-len1, len1);
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ReadROM_B7(addr, len1, data, 0);
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ReadROM_B7(addr+len1, len-len1, data, len1);
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}
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else
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ReadROM_B7(addr, TransferLen, 0);
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ReadROM_B7(addr, len, data, 0);
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}
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else
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{
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memset(TransferData, 0xFF, TransferLen);
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memset(data, 0xFF, len);
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u32 sramstart = *(u16*)&ROM[0x96] << 17;
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u32 sramend = sramstart + 0x800000; // CHECKME
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@ -1267,13 +1267,13 @@ void CartRetailNAND::ROMCommandStart(u8* cmd)
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if (addr == (sramstart+0x7FF800))
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{
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u8 iddata[0x10] = {0xEC, 0x00, 0x9E, 0xA1, 0x51, 0x65, 0x34, 0x35, 0x30, 0x35, 0x30, 0x31, 0x19, 0x19, 0x02, 0x0A};
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memcpy(TransferData, iddata, std::min(TransferLen, 0x10u));
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memcpy(data, iddata, std::min(len, 0x10u));
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printf("READING ID BLOCK @ %08X\n", addr);
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}
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}
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}
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}
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break;
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return 0;
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case 0xD6: // read NAND status
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{
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@ -1281,28 +1281,28 @@ void CartRetailNAND::ROMCommandStart(u8* cmd)
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// bit5: ready
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// bit4: write enable
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printf("NAND STATUS %02X\n", SRAMStatus);
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for (u32 i = 0; i < TransferLen; i+=4)
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*(u32*)&TransferData[i] = SRAMStatus * 0x01010101;
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for (u32 i = 0; i < len; i+=4)
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*(u32*)&data[i] = SRAMStatus * 0x01010101;
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}
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break;
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return 0;
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default:
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/*if (cmd[0] != 0xB8)
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printf("shitty command %02X %02X %02X %02X %02X %02X %02X %02X - %08X\n",
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cmd[0], cmd[1], cmd[2], cmd[3],
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cmd[4], cmd[5], cmd[6], cmd[7], TransferLen);*/
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return CartRetail::ROMCommandStart(cmd);
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cmd[4], cmd[5], cmd[6], cmd[7], len);*/
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return CartRetail::ROMCommandStart(cmd, data, len);
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}
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}
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void CartRetailNAND::ROMCommandFinish(u8* cmd)
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void CartRetailNAND::ROMCommandFinish(u8* cmd, u8* data, u32 len)
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{
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switch (cmd[0])
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{
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// TODO!
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default:
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return CartCommon::ROMCommandFinish(cmd);
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return CartCommon::ROMCommandFinish(cmd, data, len);
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}
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}
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@ -1315,8 +1315,10 @@ u8 CartRetailNAND::SPIWrite(u8 val, u32 pos, bool last)
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//
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CartHomebrew::CartHomebrew(u8* rom, u32 len) : CartCommon(rom, len)
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CartHomebrew::CartHomebrew(u8* rom, u32 len, u32 chipid) : CartCommon(rom, len, chipid)
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{
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// TODO: presumably CartSD loading should go here
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if (Config::DLDIEnable)
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ApplyDLDIPatch(melonDLDI, sizeof(melonDLDI));
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}
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@ -1334,25 +1336,25 @@ void CartHomebrew::DoSavestate(Savestate* file)
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// TODO?
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}
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void CartHomebrew::ROMCommandStart(u8* cmd)
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int CartHomebrew::ROMCommandStart(u8* cmd, u8* data, u32 len)
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{
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switch (cmd[0])
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{
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case 0xB7:
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{
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u32 addr = (cmd[1]<<24) | (cmd[2]<<16) | (cmd[3]<<8) | cmd[4];
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memset(TransferData, 0, TransferLen);
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memset(data, 0, len);
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if (((addr + TransferLen - 1) >> 12) != (addr >> 12))
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if (((addr + len - 1) >> 12) != (addr >> 12))
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{
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u32 len1 = 0x1000 - (addr & 0xFFF);
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ReadROM_B7(addr, len1, 0);
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ReadROM_B7(addr+len1, TransferLen-len1, len1);
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ReadROM_B7(addr, len1, data, 0);
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ReadROM_B7(addr+len1, len-len1, data, len1);
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}
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else
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ReadROM_B7(addr, TransferLen, 0);
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ReadROM_B7(addr, len, data, 0);
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}
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break;
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return 0;
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case 0xC0: // SD read
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{
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@ -1362,23 +1364,20 @@ void CartHomebrew::ROMCommandStart(u8* cmd)
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if (CartSD)
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{
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fseek(CartSD, addr, SEEK_SET);
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fread(TransferData, TransferLen, 1, CartSD);
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fread(data, len, 1, CartSD);
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}
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}
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break;
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return 0;
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case 0xC1: // SD write
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{
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TransferDir = 1;
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}
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break;
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return 1;
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default:
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return CartCommon::ROMCommandStart(cmd);
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return CartCommon::ROMCommandStart(cmd, data, len);
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}
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}
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void CartHomebrew::ROMCommandFinish(u8* cmd)
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void CartHomebrew::ROMCommandFinish(u8* cmd, u8* data, u32 len)
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{
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switch (cmd[0])
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{
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@ -1390,13 +1389,13 @@ void CartHomebrew::ROMCommandFinish(u8* cmd)
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if (CartSD)
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{
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fseek(CartSD, addr, SEEK_SET);
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fwrite(TransferData, TransferLen, 1, CartSD);
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fwrite(data, len, 1, CartSD);
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}
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}
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break;
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default:
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return CartCommon::ROMCommandFinish(cmd);
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return CartCommon::ROMCommandFinish(cmd, data, len);
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}
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}
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@ -1520,13 +1519,13 @@ void CartHomebrew::ApplyDLDIPatch(const u8* patch, u32 len)
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printf("applied DLDI patch\n");
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}
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void CartHomebrew::ReadROM_B7(u32 addr, u32 len, u32 offset)
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void CartHomebrew::ReadROM_B7(u32 addr, u32 len, u8* data, u32 offset)
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{
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// TODO: how strict should this be for homebrew?
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addr &= (ROMLength-1);
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memcpy(TransferData+offset, ROM+addr, len);
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memcpy(data+offset, ROM+addr, len);
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}
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@ -1786,13 +1785,13 @@ bool LoadROMCommon(u32 filelength, const char *sram, bool direct)
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ROMCommandHandler = ROMCommand_Retail;*/
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// TODO: add case for pokémon typing game
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if (CartIsHomebrew)
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Cart = new CartHomebrew(CartROM, CartROMSize);
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Cart = new CartHomebrew(CartROM, CartROMSize, CartID);
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else if (CartID & 0x08000000)
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Cart = new CartRetailNAND(CartROM, CartROMSize);
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Cart = new CartRetailNAND(CartROM, CartROMSize, CartID);
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//else if (CartID & 0x00010000)
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// Cart = new CartRetailIR(CartROM, CartROMSize);
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// Cart = new CartRetailIR(CartROM, CartROMSize, CartID);
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else
|
||||
Cart = new CartRetail(CartROM, CartROMSize);
|
||||
Cart = new CartRetail(CartROM, CartROMSize, CartID);
|
||||
|
||||
if (Cart) Cart->Reset();
|
||||
|
||||
|
|
@ -1971,7 +1970,7 @@ void ROMEndTransfer(u32 param)
|
|||
break;
|
||||
}
|
||||
}*/
|
||||
if (Cart) Cart->ROMCommandFinish(TransferCmd);
|
||||
if (Cart) Cart->ROMCommandFinish(TransferCmd, TransferData, TransferLen);
|
||||
}
|
||||
|
||||
void ROMPrepareData(u32 param)
|
||||
|
|
@ -2265,7 +2264,10 @@ void WriteROMCnt(u32 val)
|
|||
ROMCommandHandler(cmd);
|
||||
break;
|
||||
}*/
|
||||
if (Cart) Cart->ROMCommandStart(TransferCmd);
|
||||
// TODO: how should we detect that the transfer should be a write?
|
||||
// you're supposed to set bit30 of ROMCNT for a write, but it's also
|
||||
// possible to do reads just fine when that bit is set
|
||||
if (Cart) TransferDir = Cart->ROMCommandStart(TransferCmd, TransferData, TransferLen);
|
||||
|
||||
ROMCnt &= ~(1<<23);
|
||||
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@ namespace NDSCart
|
|||
class CartCommon
|
||||
{
|
||||
public:
|
||||
CartCommon(u8* rom, u32 len);
|
||||
CartCommon(u8* rom, u32 len, u32 chipid);
|
||||
virtual ~CartCommon();
|
||||
|
||||
virtual void Reset();
|
||||
|
|
@ -80,23 +80,25 @@ public:
|
|||
virtual void RelocateSave(const char* path, bool write);
|
||||
virtual void FlushSRAMFile();
|
||||
|
||||
virtual void ROMCommandStart(u8* cmd);
|
||||
virtual void ROMCommandFinish(u8* cmd);
|
||||
virtual int ROMCommandStart(u8* cmd, u8* data, u32 len);
|
||||
virtual void ROMCommandFinish(u8* cmd, u8* data, u32 len);
|
||||
|
||||
virtual u8 SPIWrite(u8 val, u32 pos, bool last);
|
||||
|
||||
protected:
|
||||
void ReadROM(u32 addr, u32 len, u32 offset);
|
||||
void ReadROM(u32 addr, u32 len, u8* data, u32 offset);
|
||||
|
||||
u8* ROM;
|
||||
u32 ROMLength;
|
||||
u32 ChipID;
|
||||
bool IsDSi;
|
||||
};
|
||||
|
||||
// CartRetail -- regular retail cart (ROM, SPI SRAM)
|
||||
class CartRetail : public CartCommon
|
||||
{
|
||||
public:
|
||||
CartRetail(u8* rom, u32 len);
|
||||
CartRetail(u8* rom, u32 len, u32 chipid);
|
||||
virtual ~CartRetail();
|
||||
|
||||
virtual void Reset();
|
||||
|
|
@ -107,12 +109,12 @@ public:
|
|||
virtual void RelocateSave(const char* path, bool write);
|
||||
virtual void FlushSRAMFile();
|
||||
|
||||
virtual void ROMCommandStart(u8* cmd);
|
||||
virtual int ROMCommandStart(u8* cmd, u8* data, u32 len);
|
||||
|
||||
virtual u8 SPIWrite(u8 val, u32 pos, bool last);
|
||||
|
||||
protected:
|
||||
void ReadROM_B7(u32 addr, u32 len, u32 offset);
|
||||
void ReadROM_B7(u32 addr, u32 len, u8* data, u32 offset);
|
||||
|
||||
u8 SRAMWrite_EEPROMTiny(u8 val, u32 pos, bool last);
|
||||
u8 SRAMWrite_EEPROM(u8 val, u32 pos, bool last);
|
||||
|
|
@ -134,7 +136,7 @@ protected:
|
|||
class CartRetailNAND : public CartRetail
|
||||
{
|
||||
public:
|
||||
CartRetailNAND(u8* rom, u32 len);
|
||||
CartRetailNAND(u8* rom, u32 len, u32 chipid);
|
||||
~CartRetailNAND();
|
||||
|
||||
void Reset();
|
||||
|
|
@ -143,8 +145,8 @@ public:
|
|||
|
||||
void LoadSave(const char* path, u32 type);
|
||||
|
||||
void ROMCommandStart(u8* cmd);
|
||||
void ROMCommandFinish(u8* cmd);
|
||||
int ROMCommandStart(u8* cmd, u8* data, u32 len);
|
||||
void ROMCommandFinish(u8* cmd, u8* data, u32 len);
|
||||
|
||||
u8 SPIWrite(u8 val, u32 pos, bool last);
|
||||
|
||||
|
|
@ -156,7 +158,7 @@ private:
|
|||
class CartRetailIR : public CartRetail
|
||||
{
|
||||
public:
|
||||
CartRetailIR(u8* rom, u32 len);
|
||||
CartRetailIR(u8* rom, u32 len, u32 chipid);
|
||||
~CartRetailIR();
|
||||
|
||||
void Reset();
|
||||
|
|
@ -173,7 +175,7 @@ private:
|
|||
class CartRetailBT : public CartRetail
|
||||
{
|
||||
public:
|
||||
CartRetailBT(u8* rom, u32 len);
|
||||
CartRetailBT(u8* rom, u32 len, u32 chipid);
|
||||
~CartRetailBT();
|
||||
|
||||
void Reset();
|
||||
|
|
@ -187,19 +189,19 @@ public:
|
|||
class CartHomebrew : public CartCommon
|
||||
{
|
||||
public:
|
||||
CartHomebrew(u8* rom, u32 len);
|
||||
CartHomebrew(u8* rom, u32 len, u32 chipid);
|
||||
~CartHomebrew();
|
||||
|
||||
void Reset();
|
||||
|
||||
void DoSavestate(Savestate* file);
|
||||
|
||||
void ROMCommandStart(u8* cmd);
|
||||
void ROMCommandFinish(u8* cmd);
|
||||
int ROMCommandStart(u8* cmd, u8* data, u32 len);
|
||||
void ROMCommandFinish(u8* cmd, u8* data, u32 len);
|
||||
|
||||
private:
|
||||
void ApplyDLDIPatch(const u8* patch, u32 len);
|
||||
void ReadROM_B7(u32 addr, u32 len, u32 offset);
|
||||
void ReadROM_B7(u32 addr, u32 len, u8* data, u32 offset);
|
||||
};
|
||||
|
||||
extern u16 SPICnt;
|
||||
|
|
|
|||
Loading…
Reference in New Issue